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[platform/adaptation/renesas_rcar/renesas_kernel.git] / drivers / spi / spi-tegra114.c
1 /*
2  * SPI driver for NVIDIA's Tegra114 SPI Controller.
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/delay.h>
22 #include <linux/dmaengine.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmapool.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/kernel.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/platform_device.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/reset.h>
36 #include <linux/spi/spi.h>
37
38 #define SPI_COMMAND1                            0x000
39 #define SPI_BIT_LENGTH(x)                       (((x) & 0x1f) << 0)
40 #define SPI_PACKED                              (1 << 5)
41 #define SPI_TX_EN                               (1 << 11)
42 #define SPI_RX_EN                               (1 << 12)
43 #define SPI_BOTH_EN_BYTE                        (1 << 13)
44 #define SPI_BOTH_EN_BIT                         (1 << 14)
45 #define SPI_LSBYTE_FE                           (1 << 15)
46 #define SPI_LSBIT_FE                            (1 << 16)
47 #define SPI_BIDIROE                             (1 << 17)
48 #define SPI_IDLE_SDA_DRIVE_LOW                  (0 << 18)
49 #define SPI_IDLE_SDA_DRIVE_HIGH                 (1 << 18)
50 #define SPI_IDLE_SDA_PULL_LOW                   (2 << 18)
51 #define SPI_IDLE_SDA_PULL_HIGH                  (3 << 18)
52 #define SPI_IDLE_SDA_MASK                       (3 << 18)
53 #define SPI_CS_SS_VAL                           (1 << 20)
54 #define SPI_CS_SW_HW                            (1 << 21)
55 /* SPI_CS_POL_INACTIVE bits are default high */
56                                                 /* n from 0 to 3 */
57 #define SPI_CS_POL_INACTIVE(n)                  (1 << (22 + (n)))
58 #define SPI_CS_POL_INACTIVE_MASK                (0xF << 22)
59
60 #define SPI_CS_SEL_0                            (0 << 26)
61 #define SPI_CS_SEL_1                            (1 << 26)
62 #define SPI_CS_SEL_2                            (2 << 26)
63 #define SPI_CS_SEL_3                            (3 << 26)
64 #define SPI_CS_SEL_MASK                         (3 << 26)
65 #define SPI_CS_SEL(x)                           (((x) & 0x3) << 26)
66 #define SPI_CONTROL_MODE_0                      (0 << 28)
67 #define SPI_CONTROL_MODE_1                      (1 << 28)
68 #define SPI_CONTROL_MODE_2                      (2 << 28)
69 #define SPI_CONTROL_MODE_3                      (3 << 28)
70 #define SPI_CONTROL_MODE_MASK                   (3 << 28)
71 #define SPI_MODE_SEL(x)                         (((x) & 0x3) << 28)
72 #define SPI_M_S                                 (1 << 30)
73 #define SPI_PIO                                 (1 << 31)
74
75 #define SPI_COMMAND2                            0x004
76 #define SPI_TX_TAP_DELAY(x)                     (((x) & 0x3F) << 6)
77 #define SPI_RX_TAP_DELAY(x)                     (((x) & 0x3F) << 0)
78
79 #define SPI_CS_TIMING1                          0x008
80 #define SPI_SETUP_HOLD(setup, hold)             (((setup) << 4) | (hold))
81 #define SPI_CS_SETUP_HOLD(reg, cs, val)                 \
82                 ((((val) & 0xFFu) << ((cs) * 8)) |      \
83                 ((reg) & ~(0xFFu << ((cs) * 8))))
84
85 #define SPI_CS_TIMING2                          0x00C
86 #define CYCLES_BETWEEN_PACKETS_0(x)             (((x) & 0x1F) << 0)
87 #define CS_ACTIVE_BETWEEN_PACKETS_0             (1 << 5)
88 #define CYCLES_BETWEEN_PACKETS_1(x)             (((x) & 0x1F) << 8)
89 #define CS_ACTIVE_BETWEEN_PACKETS_1             (1 << 13)
90 #define CYCLES_BETWEEN_PACKETS_2(x)             (((x) & 0x1F) << 16)
91 #define CS_ACTIVE_BETWEEN_PACKETS_2             (1 << 21)
92 #define CYCLES_BETWEEN_PACKETS_3(x)             (((x) & 0x1F) << 24)
93 #define CS_ACTIVE_BETWEEN_PACKETS_3             (1 << 29)
94 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val)         \
95                 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) |      \
96                         ((reg) & ~(1 << ((cs) * 8 + 5))))
97 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val)            \
98                 (reg = (((val) & 0xF) << ((cs) * 8)) |          \
99                         ((reg) & ~(0xF << ((cs) * 8))))
100
101 #define SPI_TRANS_STATUS                        0x010
102 #define SPI_BLK_CNT(val)                        (((val) >> 0) & 0xFFFF)
103 #define SPI_SLV_IDLE_COUNT(val)                 (((val) >> 16) & 0xFF)
104 #define SPI_RDY                                 (1 << 30)
105
106 #define SPI_FIFO_STATUS                         0x014
107 #define SPI_RX_FIFO_EMPTY                       (1 << 0)
108 #define SPI_RX_FIFO_FULL                        (1 << 1)
109 #define SPI_TX_FIFO_EMPTY                       (1 << 2)
110 #define SPI_TX_FIFO_FULL                        (1 << 3)
111 #define SPI_RX_FIFO_UNF                         (1 << 4)
112 #define SPI_RX_FIFO_OVF                         (1 << 5)
113 #define SPI_TX_FIFO_UNF                         (1 << 6)
114 #define SPI_TX_FIFO_OVF                         (1 << 7)
115 #define SPI_ERR                                 (1 << 8)
116 #define SPI_TX_FIFO_FLUSH                       (1 << 14)
117 #define SPI_RX_FIFO_FLUSH                       (1 << 15)
118 #define SPI_TX_FIFO_EMPTY_COUNT(val)            (((val) >> 16) & 0x7F)
119 #define SPI_RX_FIFO_FULL_COUNT(val)             (((val) >> 23) & 0x7F)
120 #define SPI_FRAME_END                           (1 << 30)
121 #define SPI_CS_INACTIVE                         (1 << 31)
122
123 #define SPI_FIFO_ERROR                          (SPI_RX_FIFO_UNF | \
124                         SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF)
125 #define SPI_FIFO_EMPTY                  (SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY)
126
127 #define SPI_TX_DATA                             0x018
128 #define SPI_RX_DATA                             0x01C
129
130 #define SPI_DMA_CTL                             0x020
131 #define SPI_TX_TRIG_1                           (0 << 15)
132 #define SPI_TX_TRIG_4                           (1 << 15)
133 #define SPI_TX_TRIG_8                           (2 << 15)
134 #define SPI_TX_TRIG_16                          (3 << 15)
135 #define SPI_TX_TRIG_MASK                        (3 << 15)
136 #define SPI_RX_TRIG_1                           (0 << 19)
137 #define SPI_RX_TRIG_4                           (1 << 19)
138 #define SPI_RX_TRIG_8                           (2 << 19)
139 #define SPI_RX_TRIG_16                          (3 << 19)
140 #define SPI_RX_TRIG_MASK                        (3 << 19)
141 #define SPI_IE_TX                               (1 << 28)
142 #define SPI_IE_RX                               (1 << 29)
143 #define SPI_CONT                                (1 << 30)
144 #define SPI_DMA                                 (1 << 31)
145 #define SPI_DMA_EN                              SPI_DMA
146
147 #define SPI_DMA_BLK                             0x024
148 #define SPI_DMA_BLK_SET(x)                      (((x) & 0xFFFF) << 0)
149
150 #define SPI_TX_FIFO                             0x108
151 #define SPI_RX_FIFO                             0x188
152 #define MAX_CHIP_SELECT                         4
153 #define SPI_FIFO_DEPTH                          64
154 #define DATA_DIR_TX                             (1 << 0)
155 #define DATA_DIR_RX                             (1 << 1)
156
157 #define SPI_DMA_TIMEOUT                         (msecs_to_jiffies(1000))
158 #define DEFAULT_SPI_DMA_BUF_LEN                 (16*1024)
159 #define TX_FIFO_EMPTY_COUNT_MAX                 SPI_TX_FIFO_EMPTY_COUNT(0x40)
160 #define RX_FIFO_FULL_COUNT_ZERO                 SPI_RX_FIFO_FULL_COUNT(0)
161 #define MAX_HOLD_CYCLES                         16
162 #define SPI_DEFAULT_SPEED                       25000000
163
164 struct tegra_spi_data {
165         struct device                           *dev;
166         struct spi_master                       *master;
167         spinlock_t                              lock;
168
169         struct clk                              *clk;
170         struct reset_control                    *rst;
171         void __iomem                            *base;
172         phys_addr_t                             phys;
173         unsigned                                irq;
174         u32                                     spi_max_frequency;
175         u32                                     cur_speed;
176
177         struct spi_device                       *cur_spi;
178         struct spi_device                       *cs_control;
179         unsigned                                cur_pos;
180         unsigned                                words_per_32bit;
181         unsigned                                bytes_per_word;
182         unsigned                                curr_dma_words;
183         unsigned                                cur_direction;
184
185         unsigned                                cur_rx_pos;
186         unsigned                                cur_tx_pos;
187
188         unsigned                                dma_buf_size;
189         unsigned                                max_buf_size;
190         bool                                    is_curr_dma_xfer;
191
192         struct completion                       rx_dma_complete;
193         struct completion                       tx_dma_complete;
194
195         u32                                     tx_status;
196         u32                                     rx_status;
197         u32                                     status_reg;
198         bool                                    is_packed;
199
200         u32                                     command1_reg;
201         u32                                     dma_control_reg;
202         u32                                     def_command1_reg;
203
204         struct completion                       xfer_completion;
205         struct spi_transfer                     *curr_xfer;
206         struct dma_chan                         *rx_dma_chan;
207         u32                                     *rx_dma_buf;
208         dma_addr_t                              rx_dma_phys;
209         struct dma_async_tx_descriptor          *rx_dma_desc;
210
211         struct dma_chan                         *tx_dma_chan;
212         u32                                     *tx_dma_buf;
213         dma_addr_t                              tx_dma_phys;
214         struct dma_async_tx_descriptor          *tx_dma_desc;
215 };
216
217 static int tegra_spi_runtime_suspend(struct device *dev);
218 static int tegra_spi_runtime_resume(struct device *dev);
219
220 static inline u32 tegra_spi_readl(struct tegra_spi_data *tspi,
221                 unsigned long reg)
222 {
223         return readl(tspi->base + reg);
224 }
225
226 static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
227                 u32 val, unsigned long reg)
228 {
229         writel(val, tspi->base + reg);
230
231         /* Read back register to make sure that register writes completed */
232         if (reg != SPI_TX_FIFO)
233                 readl(tspi->base + SPI_COMMAND1);
234 }
235
236 static void tegra_spi_clear_status(struct tegra_spi_data *tspi)
237 {
238         u32 val;
239
240         /* Write 1 to clear status register */
241         val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
242         tegra_spi_writel(tspi, val, SPI_TRANS_STATUS);
243
244         /* Clear fifo status error if any */
245         val = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
246         if (val & SPI_ERR)
247                 tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR,
248                                 SPI_FIFO_STATUS);
249 }
250
251 static unsigned tegra_spi_calculate_curr_xfer_param(
252         struct spi_device *spi, struct tegra_spi_data *tspi,
253         struct spi_transfer *t)
254 {
255         unsigned remain_len = t->len - tspi->cur_pos;
256         unsigned max_word;
257         unsigned bits_per_word = t->bits_per_word;
258         unsigned max_len;
259         unsigned total_fifo_words;
260
261         tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
262
263         if (bits_per_word == 8 || bits_per_word == 16) {
264                 tspi->is_packed = 1;
265                 tspi->words_per_32bit = 32/bits_per_word;
266         } else {
267                 tspi->is_packed = 0;
268                 tspi->words_per_32bit = 1;
269         }
270
271         if (tspi->is_packed) {
272                 max_len = min(remain_len, tspi->max_buf_size);
273                 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
274                 total_fifo_words = (max_len + 3) / 4;
275         } else {
276                 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
277                 max_word = min(max_word, tspi->max_buf_size/4);
278                 tspi->curr_dma_words = max_word;
279                 total_fifo_words = max_word;
280         }
281         return total_fifo_words;
282 }
283
284 static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
285         struct tegra_spi_data *tspi, struct spi_transfer *t)
286 {
287         unsigned nbytes;
288         unsigned tx_empty_count;
289         u32 fifo_status;
290         unsigned max_n_32bit;
291         unsigned i, count;
292         unsigned int written_words;
293         unsigned fifo_words_left;
294         u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
295
296         fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
297         tx_empty_count = SPI_TX_FIFO_EMPTY_COUNT(fifo_status);
298
299         if (tspi->is_packed) {
300                 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
301                 written_words = min(fifo_words_left, tspi->curr_dma_words);
302                 nbytes = written_words * tspi->bytes_per_word;
303                 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
304                 for (count = 0; count < max_n_32bit; count++) {
305                         u32 x = 0;
306                         for (i = 0; (i < 4) && nbytes; i++, nbytes--)
307                                 x |= (u32)(*tx_buf++) << (i * 8);
308                         tegra_spi_writel(tspi, x, SPI_TX_FIFO);
309                 }
310         } else {
311                 max_n_32bit = min(tspi->curr_dma_words,  tx_empty_count);
312                 written_words = max_n_32bit;
313                 nbytes = written_words * tspi->bytes_per_word;
314                 for (count = 0; count < max_n_32bit; count++) {
315                         u32 x = 0;
316                         for (i = 0; nbytes && (i < tspi->bytes_per_word);
317                                                         i++, nbytes--)
318                                 x |= (u32)(*tx_buf++) << (i * 8);
319                         tegra_spi_writel(tspi, x, SPI_TX_FIFO);
320                 }
321         }
322         tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
323         return written_words;
324 }
325
326 static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
327                 struct tegra_spi_data *tspi, struct spi_transfer *t)
328 {
329         unsigned rx_full_count;
330         u32 fifo_status;
331         unsigned i, count;
332         unsigned int read_words = 0;
333         unsigned len;
334         u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
335
336         fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
337         rx_full_count = SPI_RX_FIFO_FULL_COUNT(fifo_status);
338         if (tspi->is_packed) {
339                 len = tspi->curr_dma_words * tspi->bytes_per_word;
340                 for (count = 0; count < rx_full_count; count++) {
341                         u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO);
342                         for (i = 0; len && (i < 4); i++, len--)
343                                 *rx_buf++ = (x >> i*8) & 0xFF;
344                 }
345                 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
346                 read_words += tspi->curr_dma_words;
347         } else {
348                 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
349                 for (count = 0; count < rx_full_count; count++) {
350                         u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask;
351                         for (i = 0; (i < tspi->bytes_per_word); i++)
352                                 *rx_buf++ = (x >> (i*8)) & 0xFF;
353                 }
354                 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
355                 read_words += rx_full_count;
356         }
357         return read_words;
358 }
359
360 static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
361                 struct tegra_spi_data *tspi, struct spi_transfer *t)
362 {
363         /* Make the dma buffer to read by cpu */
364         dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
365                                 tspi->dma_buf_size, DMA_TO_DEVICE);
366
367         if (tspi->is_packed) {
368                 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
369                 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
370         } else {
371                 unsigned int i;
372                 unsigned int count;
373                 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
374                 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
375
376                 for (count = 0; count < tspi->curr_dma_words; count++) {
377                         u32 x = 0;
378                         for (i = 0; consume && (i < tspi->bytes_per_word);
379                                                         i++, consume--)
380                                 x |= (u32)(*tx_buf++) << (i * 8);
381                         tspi->tx_dma_buf[count] = x;
382                 }
383         }
384         tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
385
386         /* Make the dma buffer to read by dma */
387         dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
388                                 tspi->dma_buf_size, DMA_TO_DEVICE);
389 }
390
391 static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
392                 struct tegra_spi_data *tspi, struct spi_transfer *t)
393 {
394         /* Make the dma buffer to read by cpu */
395         dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
396                 tspi->dma_buf_size, DMA_FROM_DEVICE);
397
398         if (tspi->is_packed) {
399                 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
400                 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
401         } else {
402                 unsigned int i;
403                 unsigned int count;
404                 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
405                 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
406
407                 for (count = 0; count < tspi->curr_dma_words; count++) {
408                         u32 x = tspi->rx_dma_buf[count] & rx_mask;
409                         for (i = 0; (i < tspi->bytes_per_word); i++)
410                                 *rx_buf++ = (x >> (i*8)) & 0xFF;
411                 }
412         }
413         tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
414
415         /* Make the dma buffer to read by dma */
416         dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
417                 tspi->dma_buf_size, DMA_FROM_DEVICE);
418 }
419
420 static void tegra_spi_dma_complete(void *args)
421 {
422         struct completion *dma_complete = args;
423
424         complete(dma_complete);
425 }
426
427 static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len)
428 {
429         reinit_completion(&tspi->tx_dma_complete);
430         tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
431                                 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
432                                 DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
433         if (!tspi->tx_dma_desc) {
434                 dev_err(tspi->dev, "Not able to get desc for Tx\n");
435                 return -EIO;
436         }
437
438         tspi->tx_dma_desc->callback = tegra_spi_dma_complete;
439         tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
440
441         dmaengine_submit(tspi->tx_dma_desc);
442         dma_async_issue_pending(tspi->tx_dma_chan);
443         return 0;
444 }
445
446 static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len)
447 {
448         reinit_completion(&tspi->rx_dma_complete);
449         tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
450                                 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
451                                 DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
452         if (!tspi->rx_dma_desc) {
453                 dev_err(tspi->dev, "Not able to get desc for Rx\n");
454                 return -EIO;
455         }
456
457         tspi->rx_dma_desc->callback = tegra_spi_dma_complete;
458         tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
459
460         dmaengine_submit(tspi->rx_dma_desc);
461         dma_async_issue_pending(tspi->rx_dma_chan);
462         return 0;
463 }
464
465 static int tegra_spi_start_dma_based_transfer(
466                 struct tegra_spi_data *tspi, struct spi_transfer *t)
467 {
468         u32 val;
469         unsigned int len;
470         int ret = 0;
471         u32 status;
472
473         /* Make sure that Rx and Tx fifo are empty */
474         status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
475         if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
476                 dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n",
477                         (unsigned)status);
478                 return -EIO;
479         }
480
481         val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1);
482         tegra_spi_writel(tspi, val, SPI_DMA_BLK);
483
484         if (tspi->is_packed)
485                 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
486                                         4) * 4;
487         else
488                 len = tspi->curr_dma_words * 4;
489
490         /* Set attention level based on length of transfer */
491         if (len & 0xF)
492                 val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1;
493         else if (((len) >> 4) & 0x1)
494                 val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4;
495         else
496                 val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8;
497
498         if (tspi->cur_direction & DATA_DIR_TX)
499                 val |= SPI_IE_TX;
500
501         if (tspi->cur_direction & DATA_DIR_RX)
502                 val |= SPI_IE_RX;
503
504         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
505         tspi->dma_control_reg = val;
506
507         if (tspi->cur_direction & DATA_DIR_TX) {
508                 tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t);
509                 ret = tegra_spi_start_tx_dma(tspi, len);
510                 if (ret < 0) {
511                         dev_err(tspi->dev,
512                                 "Starting tx dma failed, err %d\n", ret);
513                         return ret;
514                 }
515         }
516
517         if (tspi->cur_direction & DATA_DIR_RX) {
518                 /* Make the dma buffer to read by dma */
519                 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
520                                 tspi->dma_buf_size, DMA_FROM_DEVICE);
521
522                 ret = tegra_spi_start_rx_dma(tspi, len);
523                 if (ret < 0) {
524                         dev_err(tspi->dev,
525                                 "Starting rx dma failed, err %d\n", ret);
526                         if (tspi->cur_direction & DATA_DIR_TX)
527                                 dmaengine_terminate_all(tspi->tx_dma_chan);
528                         return ret;
529                 }
530         }
531         tspi->is_curr_dma_xfer = true;
532         tspi->dma_control_reg = val;
533
534         val |= SPI_DMA_EN;
535         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
536         return ret;
537 }
538
539 static int tegra_spi_start_cpu_based_transfer(
540                 struct tegra_spi_data *tspi, struct spi_transfer *t)
541 {
542         u32 val;
543         unsigned cur_words;
544
545         if (tspi->cur_direction & DATA_DIR_TX)
546                 cur_words = tegra_spi_fill_tx_fifo_from_client_txbuf(tspi, t);
547         else
548                 cur_words = tspi->curr_dma_words;
549
550         val = SPI_DMA_BLK_SET(cur_words - 1);
551         tegra_spi_writel(tspi, val, SPI_DMA_BLK);
552
553         val = 0;
554         if (tspi->cur_direction & DATA_DIR_TX)
555                 val |= SPI_IE_TX;
556
557         if (tspi->cur_direction & DATA_DIR_RX)
558                 val |= SPI_IE_RX;
559
560         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
561         tspi->dma_control_reg = val;
562
563         tspi->is_curr_dma_xfer = false;
564
565         val |= SPI_DMA_EN;
566         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
567         return 0;
568 }
569
570 static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
571                         bool dma_to_memory)
572 {
573         struct dma_chan *dma_chan;
574         u32 *dma_buf;
575         dma_addr_t dma_phys;
576         int ret;
577         struct dma_slave_config dma_sconfig;
578
579         dma_chan = dma_request_slave_channel_reason(tspi->dev,
580                                         dma_to_memory ? "rx" : "tx");
581         if (IS_ERR(dma_chan)) {
582                 ret = PTR_ERR(dma_chan);
583                 if (ret != -EPROBE_DEFER)
584                         dev_err(tspi->dev,
585                                 "Dma channel is not available: %d\n", ret);
586                 return ret;
587         }
588
589         dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
590                                 &dma_phys, GFP_KERNEL);
591         if (!dma_buf) {
592                 dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
593                 dma_release_channel(dma_chan);
594                 return -ENOMEM;
595         }
596
597         if (dma_to_memory) {
598                 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
599                 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
600                 dma_sconfig.src_maxburst = 0;
601         } else {
602                 dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO;
603                 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
604                 dma_sconfig.dst_maxburst = 0;
605         }
606
607         ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
608         if (ret)
609                 goto scrub;
610         if (dma_to_memory) {
611                 tspi->rx_dma_chan = dma_chan;
612                 tspi->rx_dma_buf = dma_buf;
613                 tspi->rx_dma_phys = dma_phys;
614         } else {
615                 tspi->tx_dma_chan = dma_chan;
616                 tspi->tx_dma_buf = dma_buf;
617                 tspi->tx_dma_phys = dma_phys;
618         }
619         return 0;
620
621 scrub:
622         dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
623         dma_release_channel(dma_chan);
624         return ret;
625 }
626
627 static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
628         bool dma_to_memory)
629 {
630         u32 *dma_buf;
631         dma_addr_t dma_phys;
632         struct dma_chan *dma_chan;
633
634         if (dma_to_memory) {
635                 dma_buf = tspi->rx_dma_buf;
636                 dma_chan = tspi->rx_dma_chan;
637                 dma_phys = tspi->rx_dma_phys;
638                 tspi->rx_dma_chan = NULL;
639                 tspi->rx_dma_buf = NULL;
640         } else {
641                 dma_buf = tspi->tx_dma_buf;
642                 dma_chan = tspi->tx_dma_chan;
643                 dma_phys = tspi->tx_dma_phys;
644                 tspi->tx_dma_buf = NULL;
645                 tspi->tx_dma_chan = NULL;
646         }
647         if (!dma_chan)
648                 return;
649
650         dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
651         dma_release_channel(dma_chan);
652 }
653
654 static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
655                 struct spi_transfer *t, bool is_first_of_msg)
656 {
657         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
658         u32 speed = t->speed_hz;
659         u8 bits_per_word = t->bits_per_word;
660         u32 command1;
661         int req_mode;
662
663         if (speed != tspi->cur_speed) {
664                 clk_set_rate(tspi->clk, speed);
665                 tspi->cur_speed = speed;
666         }
667
668         tspi->cur_spi = spi;
669         tspi->cur_pos = 0;
670         tspi->cur_rx_pos = 0;
671         tspi->cur_tx_pos = 0;
672         tspi->curr_xfer = t;
673
674         if (is_first_of_msg) {
675                 tegra_spi_clear_status(tspi);
676
677                 command1 = tspi->def_command1_reg;
678                 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
679
680                 command1 &= ~SPI_CONTROL_MODE_MASK;
681                 req_mode = spi->mode & 0x3;
682                 if (req_mode == SPI_MODE_0)
683                         command1 |= SPI_CONTROL_MODE_0;
684                 else if (req_mode == SPI_MODE_1)
685                         command1 |= SPI_CONTROL_MODE_1;
686                 else if (req_mode == SPI_MODE_2)
687                         command1 |= SPI_CONTROL_MODE_2;
688                 else if (req_mode == SPI_MODE_3)
689                         command1 |= SPI_CONTROL_MODE_3;
690
691                 if (tspi->cs_control) {
692                         if (tspi->cs_control != spi)
693                                 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
694                         tspi->cs_control = NULL;
695                 } else
696                         tegra_spi_writel(tspi, command1, SPI_COMMAND1);
697
698                 command1 |= SPI_CS_SW_HW;
699                 if (spi->mode & SPI_CS_HIGH)
700                         command1 |= SPI_CS_SS_VAL;
701                 else
702                         command1 &= ~SPI_CS_SS_VAL;
703
704                 tegra_spi_writel(tspi, 0, SPI_COMMAND2);
705         } else {
706                 command1 = tspi->command1_reg;
707                 command1 &= ~SPI_BIT_LENGTH(~0);
708                 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
709         }
710
711         return command1;
712 }
713
714 static int tegra_spi_start_transfer_one(struct spi_device *spi,
715                 struct spi_transfer *t, u32 command1)
716 {
717         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
718         unsigned total_fifo_words;
719         int ret;
720
721         total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t);
722
723         if (tspi->is_packed)
724                 command1 |= SPI_PACKED;
725
726         command1 &= ~(SPI_CS_SEL_MASK | SPI_TX_EN | SPI_RX_EN);
727         tspi->cur_direction = 0;
728         if (t->rx_buf) {
729                 command1 |= SPI_RX_EN;
730                 tspi->cur_direction |= DATA_DIR_RX;
731         }
732         if (t->tx_buf) {
733                 command1 |= SPI_TX_EN;
734                 tspi->cur_direction |= DATA_DIR_TX;
735         }
736         command1 |= SPI_CS_SEL(spi->chip_select);
737         tegra_spi_writel(tspi, command1, SPI_COMMAND1);
738         tspi->command1_reg = command1;
739
740         dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n",
741                 tspi->def_command1_reg, (unsigned)command1);
742
743         if (total_fifo_words > SPI_FIFO_DEPTH)
744                 ret = tegra_spi_start_dma_based_transfer(tspi, t);
745         else
746                 ret = tegra_spi_start_cpu_based_transfer(tspi, t);
747         return ret;
748 }
749
750 static int tegra_spi_setup(struct spi_device *spi)
751 {
752         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
753         u32 val;
754         unsigned long flags;
755         int ret;
756
757         dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
758                 spi->bits_per_word,
759                 spi->mode & SPI_CPOL ? "" : "~",
760                 spi->mode & SPI_CPHA ? "" : "~",
761                 spi->max_speed_hz);
762
763         BUG_ON(spi->chip_select >= MAX_CHIP_SELECT);
764
765         /* Set speed to the spi max fequency if spi device has not set */
766         spi->max_speed_hz = spi->max_speed_hz ? : tspi->spi_max_frequency;
767
768         ret = pm_runtime_get_sync(tspi->dev);
769         if (ret < 0) {
770                 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
771                 return ret;
772         }
773
774         spin_lock_irqsave(&tspi->lock, flags);
775         val = tspi->def_command1_reg;
776         if (spi->mode & SPI_CS_HIGH)
777                 val &= ~SPI_CS_POL_INACTIVE(spi->chip_select);
778         else
779                 val |= SPI_CS_POL_INACTIVE(spi->chip_select);
780         tspi->def_command1_reg = val;
781         tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
782         spin_unlock_irqrestore(&tspi->lock, flags);
783
784         pm_runtime_put(tspi->dev);
785         return 0;
786 }
787
788 static void tegra_spi_transfer_delay(int delay)
789 {
790         if (!delay)
791                 return;
792
793         if (delay >= 1000)
794                 mdelay(delay / 1000);
795
796         udelay(delay % 1000);
797 }
798
799 static int tegra_spi_transfer_one_message(struct spi_master *master,
800                         struct spi_message *msg)
801 {
802         bool is_first_msg = true;
803         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
804         struct spi_transfer *xfer;
805         struct spi_device *spi = msg->spi;
806         int ret;
807         bool skip = false;
808
809         msg->status = 0;
810         msg->actual_length = 0;
811
812         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
813                 u32 cmd1;
814
815                 reinit_completion(&tspi->xfer_completion);
816
817                 cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg);
818
819                 if (!xfer->len) {
820                         ret = 0;
821                         skip = true;
822                         goto complete_xfer;
823                 }
824
825                 ret = tegra_spi_start_transfer_one(spi, xfer, cmd1);
826                 if (ret < 0) {
827                         dev_err(tspi->dev,
828                                 "spi can not start transfer, err %d\n", ret);
829                         goto complete_xfer;
830                 }
831
832                 is_first_msg = false;
833                 ret = wait_for_completion_timeout(&tspi->xfer_completion,
834                                                 SPI_DMA_TIMEOUT);
835                 if (WARN_ON(ret == 0)) {
836                         dev_err(tspi->dev,
837                                 "spi trasfer timeout, err %d\n", ret);
838                         ret = -EIO;
839                         goto complete_xfer;
840                 }
841
842                 if (tspi->tx_status ||  tspi->rx_status) {
843                         dev_err(tspi->dev, "Error in Transfer\n");
844                         ret = -EIO;
845                         goto complete_xfer;
846                 }
847                 msg->actual_length += xfer->len;
848
849 complete_xfer:
850                 if (ret < 0 || skip) {
851                         tegra_spi_writel(tspi, tspi->def_command1_reg,
852                                         SPI_COMMAND1);
853                         tegra_spi_transfer_delay(xfer->delay_usecs);
854                         goto exit;
855                 } else if (msg->transfers.prev == &xfer->transfer_list) {
856                         /* This is the last transfer in message */
857                         if (xfer->cs_change)
858                                 tspi->cs_control = spi;
859                         else {
860                                 tegra_spi_writel(tspi, tspi->def_command1_reg,
861                                                 SPI_COMMAND1);
862                                 tegra_spi_transfer_delay(xfer->delay_usecs);
863                         }
864                 } else if (xfer->cs_change) {
865                         tegra_spi_writel(tspi, tspi->def_command1_reg,
866                                         SPI_COMMAND1);
867                         tegra_spi_transfer_delay(xfer->delay_usecs);
868                 }
869
870         }
871         ret = 0;
872 exit:
873         msg->status = ret;
874         spi_finalize_current_message(master);
875         return ret;
876 }
877
878 static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
879 {
880         struct spi_transfer *t = tspi->curr_xfer;
881         unsigned long flags;
882
883         spin_lock_irqsave(&tspi->lock, flags);
884         if (tspi->tx_status ||  tspi->rx_status) {
885                 dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n",
886                         tspi->status_reg);
887                 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
888                         tspi->command1_reg, tspi->dma_control_reg);
889                 reset_control_assert(tspi->rst);
890                 udelay(2);
891                 reset_control_deassert(tspi->rst);
892                 complete(&tspi->xfer_completion);
893                 goto exit;
894         }
895
896         if (tspi->cur_direction & DATA_DIR_RX)
897                 tegra_spi_read_rx_fifo_to_client_rxbuf(tspi, t);
898
899         if (tspi->cur_direction & DATA_DIR_TX)
900                 tspi->cur_pos = tspi->cur_tx_pos;
901         else
902                 tspi->cur_pos = tspi->cur_rx_pos;
903
904         if (tspi->cur_pos == t->len) {
905                 complete(&tspi->xfer_completion);
906                 goto exit;
907         }
908
909         tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
910         tegra_spi_start_cpu_based_transfer(tspi, t);
911 exit:
912         spin_unlock_irqrestore(&tspi->lock, flags);
913         return IRQ_HANDLED;
914 }
915
916 static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
917 {
918         struct spi_transfer *t = tspi->curr_xfer;
919         long wait_status;
920         int err = 0;
921         unsigned total_fifo_words;
922         unsigned long flags;
923
924         /* Abort dmas if any error */
925         if (tspi->cur_direction & DATA_DIR_TX) {
926                 if (tspi->tx_status) {
927                         dmaengine_terminate_all(tspi->tx_dma_chan);
928                         err += 1;
929                 } else {
930                         wait_status = wait_for_completion_interruptible_timeout(
931                                 &tspi->tx_dma_complete, SPI_DMA_TIMEOUT);
932                         if (wait_status <= 0) {
933                                 dmaengine_terminate_all(tspi->tx_dma_chan);
934                                 dev_err(tspi->dev, "TxDma Xfer failed\n");
935                                 err += 1;
936                         }
937                 }
938         }
939
940         if (tspi->cur_direction & DATA_DIR_RX) {
941                 if (tspi->rx_status) {
942                         dmaengine_terminate_all(tspi->rx_dma_chan);
943                         err += 2;
944                 } else {
945                         wait_status = wait_for_completion_interruptible_timeout(
946                                 &tspi->rx_dma_complete, SPI_DMA_TIMEOUT);
947                         if (wait_status <= 0) {
948                                 dmaengine_terminate_all(tspi->rx_dma_chan);
949                                 dev_err(tspi->dev, "RxDma Xfer failed\n");
950                                 err += 2;
951                         }
952                 }
953         }
954
955         spin_lock_irqsave(&tspi->lock, flags);
956         if (err) {
957                 dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n",
958                         tspi->status_reg);
959                 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
960                         tspi->command1_reg, tspi->dma_control_reg);
961                 reset_control_assert(tspi->rst);
962                 udelay(2);
963                 reset_control_deassert(tspi->rst);
964                 complete(&tspi->xfer_completion);
965                 spin_unlock_irqrestore(&tspi->lock, flags);
966                 return IRQ_HANDLED;
967         }
968
969         if (tspi->cur_direction & DATA_DIR_RX)
970                 tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
971
972         if (tspi->cur_direction & DATA_DIR_TX)
973                 tspi->cur_pos = tspi->cur_tx_pos;
974         else
975                 tspi->cur_pos = tspi->cur_rx_pos;
976
977         if (tspi->cur_pos == t->len) {
978                 complete(&tspi->xfer_completion);
979                 goto exit;
980         }
981
982         /* Continue transfer in current message */
983         total_fifo_words = tegra_spi_calculate_curr_xfer_param(tspi->cur_spi,
984                                                         tspi, t);
985         if (total_fifo_words > SPI_FIFO_DEPTH)
986                 err = tegra_spi_start_dma_based_transfer(tspi, t);
987         else
988                 err = tegra_spi_start_cpu_based_transfer(tspi, t);
989
990 exit:
991         spin_unlock_irqrestore(&tspi->lock, flags);
992         return IRQ_HANDLED;
993 }
994
995 static irqreturn_t tegra_spi_isr_thread(int irq, void *context_data)
996 {
997         struct tegra_spi_data *tspi = context_data;
998
999         if (!tspi->is_curr_dma_xfer)
1000                 return handle_cpu_based_xfer(tspi);
1001         return handle_dma_based_xfer(tspi);
1002 }
1003
1004 static irqreturn_t tegra_spi_isr(int irq, void *context_data)
1005 {
1006         struct tegra_spi_data *tspi = context_data;
1007
1008         tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
1009         if (tspi->cur_direction & DATA_DIR_TX)
1010                 tspi->tx_status = tspi->status_reg &
1011                                         (SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF);
1012
1013         if (tspi->cur_direction & DATA_DIR_RX)
1014                 tspi->rx_status = tspi->status_reg &
1015                                         (SPI_RX_FIFO_OVF | SPI_RX_FIFO_UNF);
1016         tegra_spi_clear_status(tspi);
1017
1018         return IRQ_WAKE_THREAD;
1019 }
1020
1021 static void tegra_spi_parse_dt(struct platform_device *pdev,
1022         struct tegra_spi_data *tspi)
1023 {
1024         struct device_node *np = pdev->dev.of_node;
1025
1026         if (of_property_read_u32(np, "spi-max-frequency",
1027                                 &tspi->spi_max_frequency))
1028                 tspi->spi_max_frequency = 25000000; /* 25MHz */
1029 }
1030
1031 static struct of_device_id tegra_spi_of_match[] = {
1032         { .compatible = "nvidia,tegra114-spi", },
1033         {}
1034 };
1035 MODULE_DEVICE_TABLE(of, tegra_spi_of_match);
1036
1037 static int tegra_spi_probe(struct platform_device *pdev)
1038 {
1039         struct spi_master       *master;
1040         struct tegra_spi_data   *tspi;
1041         struct resource         *r;
1042         int ret, spi_irq;
1043
1044         master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1045         if (!master) {
1046                 dev_err(&pdev->dev, "master allocation failed\n");
1047                 return -ENOMEM;
1048         }
1049         platform_set_drvdata(pdev, master);
1050         tspi = spi_master_get_devdata(master);
1051
1052         /* Parse DT */
1053         tegra_spi_parse_dt(pdev, tspi);
1054
1055         /* the spi->mode bits understood by this driver: */
1056         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1057         master->setup = tegra_spi_setup;
1058         master->transfer_one_message = tegra_spi_transfer_one_message;
1059         master->num_chipselect = MAX_CHIP_SELECT;
1060         master->bus_num = -1;
1061         master->auto_runtime_pm = true;
1062
1063         tspi->master = master;
1064         tspi->dev = &pdev->dev;
1065         spin_lock_init(&tspi->lock);
1066
1067         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1068         tspi->base = devm_ioremap_resource(&pdev->dev, r);
1069         if (IS_ERR(tspi->base)) {
1070                 ret = PTR_ERR(tspi->base);
1071                 goto exit_free_master;
1072         }
1073         tspi->phys = r->start;
1074
1075         spi_irq = platform_get_irq(pdev, 0);
1076         tspi->irq = spi_irq;
1077         ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
1078                         tegra_spi_isr_thread, IRQF_ONESHOT,
1079                         dev_name(&pdev->dev), tspi);
1080         if (ret < 0) {
1081                 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1082                                         tspi->irq);
1083                 goto exit_free_master;
1084         }
1085
1086         tspi->clk = devm_clk_get(&pdev->dev, "spi");
1087         if (IS_ERR(tspi->clk)) {
1088                 dev_err(&pdev->dev, "can not get clock\n");
1089                 ret = PTR_ERR(tspi->clk);
1090                 goto exit_free_irq;
1091         }
1092
1093         tspi->rst = devm_reset_control_get(&pdev->dev, "spi");
1094         if (IS_ERR(tspi->rst)) {
1095                 dev_err(&pdev->dev, "can not get reset\n");
1096                 ret = PTR_ERR(tspi->rst);
1097                 goto exit_free_irq;
1098         }
1099
1100         tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
1101         tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1102
1103         ret = tegra_spi_init_dma_param(tspi, true);
1104         if (ret < 0)
1105                 goto exit_free_irq;
1106         ret = tegra_spi_init_dma_param(tspi, false);
1107         if (ret < 0)
1108                 goto exit_rx_dma_free;
1109         tspi->max_buf_size = tspi->dma_buf_size;
1110         init_completion(&tspi->tx_dma_complete);
1111         init_completion(&tspi->rx_dma_complete);
1112
1113         init_completion(&tspi->xfer_completion);
1114
1115         pm_runtime_enable(&pdev->dev);
1116         if (!pm_runtime_enabled(&pdev->dev)) {
1117                 ret = tegra_spi_runtime_resume(&pdev->dev);
1118                 if (ret)
1119                         goto exit_pm_disable;
1120         }
1121
1122         ret = pm_runtime_get_sync(&pdev->dev);
1123         if (ret < 0) {
1124                 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1125                 goto exit_pm_disable;
1126         }
1127         tspi->def_command1_reg  = SPI_M_S;
1128         tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1129         pm_runtime_put(&pdev->dev);
1130
1131         master->dev.of_node = pdev->dev.of_node;
1132         ret = devm_spi_register_master(&pdev->dev, master);
1133         if (ret < 0) {
1134                 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1135                 goto exit_pm_disable;
1136         }
1137         return ret;
1138
1139 exit_pm_disable:
1140         pm_runtime_disable(&pdev->dev);
1141         if (!pm_runtime_status_suspended(&pdev->dev))
1142                 tegra_spi_runtime_suspend(&pdev->dev);
1143         tegra_spi_deinit_dma_param(tspi, false);
1144 exit_rx_dma_free:
1145         tegra_spi_deinit_dma_param(tspi, true);
1146 exit_free_irq:
1147         free_irq(spi_irq, tspi);
1148 exit_free_master:
1149         spi_master_put(master);
1150         return ret;
1151 }
1152
1153 static int tegra_spi_remove(struct platform_device *pdev)
1154 {
1155         struct spi_master *master = platform_get_drvdata(pdev);
1156         struct tegra_spi_data   *tspi = spi_master_get_devdata(master);
1157
1158         free_irq(tspi->irq, tspi);
1159
1160         if (tspi->tx_dma_chan)
1161                 tegra_spi_deinit_dma_param(tspi, false);
1162
1163         if (tspi->rx_dma_chan)
1164                 tegra_spi_deinit_dma_param(tspi, true);
1165
1166         pm_runtime_disable(&pdev->dev);
1167         if (!pm_runtime_status_suspended(&pdev->dev))
1168                 tegra_spi_runtime_suspend(&pdev->dev);
1169
1170         return 0;
1171 }
1172
1173 #ifdef CONFIG_PM_SLEEP
1174 static int tegra_spi_suspend(struct device *dev)
1175 {
1176         struct spi_master *master = dev_get_drvdata(dev);
1177
1178         return spi_master_suspend(master);
1179 }
1180
1181 static int tegra_spi_resume(struct device *dev)
1182 {
1183         struct spi_master *master = dev_get_drvdata(dev);
1184         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1185         int ret;
1186
1187         ret = pm_runtime_get_sync(dev);
1188         if (ret < 0) {
1189                 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1190                 return ret;
1191         }
1192         tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
1193         pm_runtime_put(dev);
1194
1195         return spi_master_resume(master);
1196 }
1197 #endif
1198
1199 static int tegra_spi_runtime_suspend(struct device *dev)
1200 {
1201         struct spi_master *master = dev_get_drvdata(dev);
1202         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1203
1204         /* Flush all write which are in PPSB queue by reading back */
1205         tegra_spi_readl(tspi, SPI_COMMAND1);
1206
1207         clk_disable_unprepare(tspi->clk);
1208         return 0;
1209 }
1210
1211 static int tegra_spi_runtime_resume(struct device *dev)
1212 {
1213         struct spi_master *master = dev_get_drvdata(dev);
1214         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1215         int ret;
1216
1217         ret = clk_prepare_enable(tspi->clk);
1218         if (ret < 0) {
1219                 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1220                 return ret;
1221         }
1222         return 0;
1223 }
1224
1225 static const struct dev_pm_ops tegra_spi_pm_ops = {
1226         SET_RUNTIME_PM_OPS(tegra_spi_runtime_suspend,
1227                 tegra_spi_runtime_resume, NULL)
1228         SET_SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend, tegra_spi_resume)
1229 };
1230 static struct platform_driver tegra_spi_driver = {
1231         .driver = {
1232                 .name           = "spi-tegra114",
1233                 .owner          = THIS_MODULE,
1234                 .pm             = &tegra_spi_pm_ops,
1235                 .of_match_table = tegra_spi_of_match,
1236         },
1237         .probe =        tegra_spi_probe,
1238         .remove =       tegra_spi_remove,
1239 };
1240 module_platform_driver(tegra_spi_driver);
1241
1242 MODULE_ALIAS("platform:spi-tegra114");
1243 MODULE_DESCRIPTION("NVIDIA Tegra114 SPI Controller Driver");
1244 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1245 MODULE_LICENSE("GPL v2");