drivers/spi/spi-sunxi.c

   1 /*
   2  * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
   3  * S.J.R. van Schaik <stephan@whiteboxsystems.nl>
   4  * M.B.W. Wajer <merlijn@whiteboxsystems.nl>
   5  *
   6  * (C) Copyright 2017 Olimex Ltd..
   7  * Stefan Mavrodiev <stefan@olimex.com>
   8  *
   9  * Based on linux spi driver. Original copyright follows:
  10  * linux/drivers/spi/spi-sun4i.c
  11  *
  12  * Copyright (C) 2012 - 2014 Allwinner Tech
  13  * Pan Nan <pannan@allwinnertech.com>
  14  *
  15  * Copyright (C) 2014 Maxime Ripard
  16  * Maxime Ripard <maxime.ripard@free-electrons.com>
  17  *
  18  * SPDX-License-Identifier:     GPL-2.0+
  19  */
  20
  21 #include <common.h>
  22 #include <clk.h>
  23 #include <dm.h>
  24 #include <log.h>
  25 #include <spi.h>
  26 #include <errno.h>
  27 #include <fdt_support.h>
  28 #include <reset.h>
  29 #include <wait_bit.h>
  30 #include <asm/global_data.h>
  31 #include <dm/device_compat.h>
  32 #include <linux/bitops.h>
  33
  34 #include <asm/bitops.h>
  35 #include <asm/io.h>
  36
  37 #include <linux/iopoll.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 /* sun4i spi registers */
  42 #define SUN4I_RXDATA_REG                0x00
  43 #define SUN4I_TXDATA_REG                0x04
  44 #define SUN4I_CTL_REG                   0x08
  45 #define SUN4I_CLK_CTL_REG               0x1c
  46 #define SUN4I_BURST_CNT_REG             0x20
  47 #define SUN4I_XMIT_CNT_REG              0x24
  48 #define SUN4I_FIFO_STA_REG              0x28
  49
  50 /* sun6i spi registers */
  51 #define SUN6I_GBL_CTL_REG               0x04
  52 #define SUN6I_TFR_CTL_REG               0x08
  53 #define SUN6I_FIFO_CTL_REG              0x18
  54 #define SUN6I_FIFO_STA_REG              0x1c
  55 #define SUN6I_CLK_CTL_REG               0x24
  56 #define SUN6I_BURST_CNT_REG             0x30
  57 #define SUN6I_XMIT_CNT_REG              0x34
  58 #define SUN6I_BURST_CTL_REG             0x38
  59 #define SUN6I_TXDATA_REG                0x200
  60 #define SUN6I_RXDATA_REG                0x300
  61
  62 /* sun spi bits */
  63 #define SUN4I_CTL_ENABLE                BIT(0)
  64 #define SUN4I_CTL_MASTER                BIT(1)
  65 #define SUN4I_CLK_CTL_CDR2_MASK         0xff
  66 #define SUN4I_CLK_CTL_CDR2(div)         ((div) & SUN4I_CLK_CTL_CDR2_MASK)
  67 #define SUN4I_CLK_CTL_CDR1_MASK         0xf
  68 #define SUN4I_CLK_CTL_CDR1(div)         (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
  69 #define SUN4I_CLK_CTL_DRS               BIT(12)
  70 #define SUN4I_MAX_XFER_SIZE             0xffffff
  71 #define SUN4I_BURST_CNT(cnt)            ((cnt) & SUN4I_MAX_XFER_SIZE)
  72 #define SUN4I_XMIT_CNT(cnt)             ((cnt) & SUN4I_MAX_XFER_SIZE)
  73 #define SUN4I_FIFO_STA_RF_CNT_BITS      0
  74
  75 #define SUN4I_SPI_MAX_RATE              24000000
  76 #define SUN4I_SPI_MIN_RATE              3000
  77 #define SUN4I_SPI_DEFAULT_RATE          1000000
  78 #define SUN4I_SPI_TIMEOUT_MS            1000
  79
  80 #define SPI_REG(priv, reg)              ((priv)->base + \
  81                                         (priv)->variant->regs[reg])
  82 #define SPI_BIT(priv, bit)              ((priv)->variant->bits[bit])
  83 #define SPI_CS(priv, cs)                (((cs) << SPI_BIT(priv, SPI_TCR_CS_SEL)) & \
  84                                         SPI_BIT(priv, SPI_TCR_CS_MASK))
  85
  86 /* sun spi register set */
  87 enum sun4i_spi_regs {
  88         SPI_GCR,
  89         SPI_TCR,
  90         SPI_FCR,
  91         SPI_FSR,
  92         SPI_CCR,
  93         SPI_BC,
  94         SPI_TC,
  95         SPI_BCTL,
  96         SPI_TXD,
  97         SPI_RXD,
  98 };
  99
 100 /* sun spi register bits */
 101 enum sun4i_spi_bits {
 102         SPI_GCR_TP,
 103         SPI_GCR_SRST,
 104         SPI_TCR_CPHA,
 105         SPI_TCR_CPOL,
 106         SPI_TCR_CS_ACTIVE_LOW,
 107         SPI_TCR_CS_SEL,
 108         SPI_TCR_CS_MASK,
 109         SPI_TCR_XCH,
 110         SPI_TCR_CS_MANUAL,
 111         SPI_TCR_CS_LEVEL,
 112         SPI_FCR_TF_RST,
 113         SPI_FCR_RF_RST,
 114         SPI_FSR_RF_CNT_MASK,
 115 };
 116
 117 struct sun4i_spi_variant {
 118         const unsigned long *regs;
 119         const u32 *bits;
 120         u32 fifo_depth;
 121         bool has_soft_reset;
 122         bool has_burst_ctl;
 123 };
 124
 125 struct sun4i_spi_plat {
 126         struct sun4i_spi_variant *variant;
 127         u32 base;
 128         u32 max_hz;
 129 };
 130
 131 struct sun4i_spi_priv {
 132         struct sun4i_spi_variant *variant;
 133         struct clk clk_ahb, clk_mod;
 134         struct reset_ctl reset;
 135         u32 base;
 136         u32 freq;
 137         u32 mode;
 138
 139         const u8 *tx_buf;
 140         u8 *rx_buf;
 141 };
 142
 143 static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
 144 {
 145         u8 byte;
 146
 147         while (len--) {
 148                 byte = readb(SPI_REG(priv, SPI_RXD));
 149                 if (priv->rx_buf)
 150                         *priv->rx_buf++ = byte;
 151         }
 152 }
 153
 154 static inline void sun4i_spi_fill_fifo(struct sun4i_spi_priv *priv, int len)
 155 {
 156         u8 byte;
 157
 158         while (len--) {
 159                 byte = priv->tx_buf ? *priv->tx_buf++ : 0;
 160                 writeb(byte, SPI_REG(priv, SPI_TXD));
 161         }
 162 }
 163
 164 static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable)
 165 {
 166         struct sun4i_spi_priv *priv = dev_get_priv(bus);
 167         u32 reg;
 168
 169         reg = readl(SPI_REG(priv, SPI_TCR));
 170
 171         reg &= ~SPI_BIT(priv, SPI_TCR_CS_MASK);
 172         reg |= SPI_CS(priv, cs);
 173
 174         if (enable)
 175                 reg &= ~SPI_BIT(priv, SPI_TCR_CS_LEVEL);
 176         else
 177                 reg |= SPI_BIT(priv, SPI_TCR_CS_LEVEL);
 178
 179         writel(reg, SPI_REG(priv, SPI_TCR));
 180 }
 181
 182 static inline int sun4i_spi_set_clock(struct udevice *dev, bool enable)
 183 {
 184         struct sun4i_spi_priv *priv = dev_get_priv(dev);
 185         int ret;
 186
 187         if (!enable) {
 188                 clk_disable(&priv->clk_ahb);
 189                 clk_disable(&priv->clk_mod);
 190                 if (reset_valid(&priv->reset))
 191                         reset_assert(&priv->reset);
 192                 return 0;
 193         }
 194
 195         ret = clk_enable(&priv->clk_ahb);
 196         if (ret) {
 197                 dev_err(dev, "failed to enable ahb clock (ret=%d)\n", ret);
 198                 return ret;
 199         }
 200
 201         ret = clk_enable(&priv->clk_mod);
 202         if (ret) {
 203                 dev_err(dev, "failed to enable mod clock (ret=%d)\n", ret);
 204                 goto err_ahb;
 205         }
 206
 207         if (reset_valid(&priv->reset)) {
 208                 ret = reset_deassert(&priv->reset);
 209                 if (ret) {
 210                         dev_err(dev, "failed to deassert reset\n");
 211                         goto err_mod;
 212                 }
 213         }
 214
 215         return 0;
 216
 217 err_mod:
 218         clk_disable(&priv->clk_mod);
 219 err_ahb:
 220         clk_disable(&priv->clk_ahb);
 221         return ret;
 222 }
 223
 224 static void sun4i_spi_set_speed_mode(struct udevice *dev)
 225 {
 226         struct sun4i_spi_priv *priv = dev_get_priv(dev);
 227         unsigned int div;
 228         u32 reg;
 229
 230         /*
 231          * Setup clock divider.
 232          *
 233          * We have two choices there. Either we can use the clock
 234          * divide rate 1, which is calculated thanks to this formula:
 235          * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
 236          * Or we can use CDR2, which is calculated with the formula:
 237          * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
 238          * Whether we use the former or the latter is set through the
 239          * DRS bit.
 240          *
 241          * First try CDR2, and if we can't reach the expected
 242          * frequency, fall back to CDR1.
 243          */
 244
 245         div = SUN4I_SPI_MAX_RATE / (2 * priv->freq);
 246         reg = readl(SPI_REG(priv, SPI_CCR));
 247
 248         if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
 249                 if (div > 0)
 250                         div--;
 251
 252                 reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS);
 253                 reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
 254         } else {
 255                 div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(priv->freq);
 256                 reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS);
 257                 reg |= SUN4I_CLK_CTL_CDR1(div);
 258         }
 259
 260         writel(reg, SPI_REG(priv, SPI_CCR));
 261
 262         reg = readl(SPI_REG(priv, SPI_TCR));
 263         reg &= ~(SPI_BIT(priv, SPI_TCR_CPOL) | SPI_BIT(priv, SPI_TCR_CPHA));
 264
 265         if (priv->mode & SPI_CPOL)
 266                 reg |= SPI_BIT(priv, SPI_TCR_CPOL);
 267
 268         if (priv->mode & SPI_CPHA)
 269                 reg |= SPI_BIT(priv, SPI_TCR_CPHA);
 270
 271         writel(reg, SPI_REG(priv, SPI_TCR));
 272 }
 273
 274 static int sun4i_spi_claim_bus(struct udevice *dev)
 275 {
 276         struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
 277         int ret;
 278
 279         ret = sun4i_spi_set_clock(dev->parent, true);
 280         if (ret)
 281                 return ret;
 282
 283         setbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE |
 284                      SUN4I_CTL_MASTER | SPI_BIT(priv, SPI_GCR_TP));
 285
 286         if (priv->variant->has_soft_reset)
 287                 setbits_le32(SPI_REG(priv, SPI_GCR),
 288                              SPI_BIT(priv, SPI_GCR_SRST));
 289
 290         setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) |
 291                      SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW));
 292
 293         sun4i_spi_set_speed_mode(dev->parent);
 294
 295         return 0;
 296 }
 297
 298 static int sun4i_spi_release_bus(struct udevice *dev)
 299 {
 300         struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
 301
 302         clrbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE);
 303
 304         sun4i_spi_set_clock(dev->parent, false);
 305
 306         return 0;
 307 }
 308
 309 static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
 310                           const void *dout, void *din, unsigned long flags)
 311 {
 312         struct udevice *bus = dev->parent;
 313         struct sun4i_spi_priv *priv = dev_get_priv(bus);
 314         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 315
 316         u32 len = bitlen / 8;
 317         u8 nbytes;
 318         int ret;
 319
 320         priv->tx_buf = dout;
 321         priv->rx_buf = din;
 322
 323         if (bitlen % 8) {
 324                 debug("%s: non byte-aligned SPI transfer.\n", __func__);
 325                 return -ENAVAIL;
 326         }
 327
 328         if (flags & SPI_XFER_BEGIN)
 329                 sun4i_spi_set_cs(bus, slave_plat->cs, true);
 330
 331         /* Reset FIFOs */
 332         setbits_le32(SPI_REG(priv, SPI_FCR), SPI_BIT(priv, SPI_FCR_RF_RST) |
 333                      SPI_BIT(priv, SPI_FCR_TF_RST));
 334
 335         while (len) {
 336                 /* Setup the transfer now... */
 337                 nbytes = min(len, (priv->variant->fifo_depth - 1));
 338
 339                 /* Setup the counters */
 340                 writel(SUN4I_BURST_CNT(nbytes), SPI_REG(priv, SPI_BC));
 341                 writel(SUN4I_XMIT_CNT(nbytes), SPI_REG(priv, SPI_TC));
 342
 343                 if (priv->variant->has_burst_ctl)
 344                         writel(SUN4I_BURST_CNT(nbytes),
 345                                SPI_REG(priv, SPI_BCTL));
 346
 347                 /* Fill the TX FIFO */
 348                 sun4i_spi_fill_fifo(priv, nbytes);
 349
 350                 /* Start the transfer */
 351                 setbits_le32(SPI_REG(priv, SPI_TCR),
 352                              SPI_BIT(priv, SPI_TCR_XCH));
 353
 354                 /* Wait for the transfer to be done */
 355                 ret = wait_for_bit_le32((const void *)SPI_REG(priv, SPI_TCR),
 356                                         SPI_BIT(priv, SPI_TCR_XCH),
 357                                         false, SUN4I_SPI_TIMEOUT_MS, false);
 358                 if (ret < 0) {
 359                         printf("ERROR: sun4i_spi: Timeout transferring data\n");
 360                         sun4i_spi_set_cs(bus, slave_plat->cs, false);
 361                         return ret;
 362                 }
 363
 364                 /* Drain the RX FIFO */
 365                 sun4i_spi_drain_fifo(priv, nbytes);
 366
 367                 len -= nbytes;
 368         }
 369
 370         if (flags & SPI_XFER_END)
 371                 sun4i_spi_set_cs(bus, slave_plat->cs, false);
 372
 373         return 0;
 374 }
 375
 376 static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
 377 {
 378         struct sun4i_spi_plat *plat = dev_get_plat(dev);
 379         struct sun4i_spi_priv *priv = dev_get_priv(dev);
 380
 381         if (speed > plat->max_hz)
 382                 speed = plat->max_hz;
 383
 384         if (speed < SUN4I_SPI_MIN_RATE)
 385                 speed = SUN4I_SPI_MIN_RATE;
 386
 387         priv->freq = speed;
 388
 389         return 0;
 390 }
 391
 392 static int sun4i_spi_set_mode(struct udevice *dev, uint mode)
 393 {
 394         struct sun4i_spi_priv *priv = dev_get_priv(dev);
 395
 396         priv->mode = mode;
 397
 398         return 0;
 399 }
 400
 401 static const struct dm_spi_ops sun4i_spi_ops = {
 402         .claim_bus              = sun4i_spi_claim_bus,
 403         .release_bus            = sun4i_spi_release_bus,
 404         .xfer                   = sun4i_spi_xfer,
 405         .set_speed              = sun4i_spi_set_speed,
 406         .set_mode               = sun4i_spi_set_mode,
 407 };
 408
 409 static int sun4i_spi_probe(struct udevice *bus)
 410 {
 411         struct sun4i_spi_plat *plat = dev_get_plat(bus);
 412         struct sun4i_spi_priv *priv = dev_get_priv(bus);
 413         int ret;
 414
 415         ret = clk_get_by_name(bus, "ahb", &priv->clk_ahb);
 416         if (ret) {
 417                 dev_err(bus, "failed to get ahb clock\n");
 418                 return ret;
 419         }
 420
 421         ret = clk_get_by_name(bus, "mod", &priv->clk_mod);
 422         if (ret) {
 423                 dev_err(bus, "failed to get mod clock\n");
 424                 return ret;
 425         }
 426
 427         ret = reset_get_by_index(bus, 0, &priv->reset);
 428         if (ret && ret != -ENOENT) {
 429                 dev_err(bus, "failed to get reset\n");
 430                 return ret;
 431         }
 432
 433         priv->variant = plat->variant;
 434         priv->base = plat->base;
 435         priv->freq = plat->max_hz;
 436
 437         return 0;
 438 }
 439
 440 static int sun4i_spi_of_to_plat(struct udevice *bus)
 441 {
 442         struct sun4i_spi_plat *plat = dev_get_plat(bus);
 443         int node = dev_of_offset(bus);
 444
 445         plat->base = dev_read_addr(bus);
 446         plat->variant = (struct sun4i_spi_variant *)dev_get_driver_data(bus);
 447         plat->max_hz = fdtdec_get_int(gd->fdt_blob, node,
 448                                       "spi-max-frequency",
 449                                       SUN4I_SPI_DEFAULT_RATE);
 450
 451         if (plat->max_hz > SUN4I_SPI_MAX_RATE)
 452                 plat->max_hz = SUN4I_SPI_MAX_RATE;
 453
 454         return 0;
 455 }
 456
 457 static const unsigned long sun4i_spi_regs[] = {
 458         [SPI_GCR]               = SUN4I_CTL_REG,
 459         [SPI_TCR]               = SUN4I_CTL_REG,
 460         [SPI_FCR]               = SUN4I_CTL_REG,
 461         [SPI_FSR]               = SUN4I_FIFO_STA_REG,
 462         [SPI_CCR]               = SUN4I_CLK_CTL_REG,
 463         [SPI_BC]                = SUN4I_BURST_CNT_REG,
 464         [SPI_TC]                = SUN4I_XMIT_CNT_REG,
 465         [SPI_TXD]               = SUN4I_TXDATA_REG,
 466         [SPI_RXD]               = SUN4I_RXDATA_REG,
 467 };
 468
 469 static const u32 sun4i_spi_bits[] = {
 470         [SPI_GCR_TP]            = BIT(18),
 471         [SPI_TCR_CPHA]          = BIT(2),
 472         [SPI_TCR_CPOL]          = BIT(3),
 473         [SPI_TCR_CS_ACTIVE_LOW] = BIT(4),
 474         [SPI_TCR_XCH]           = BIT(10),
 475         [SPI_TCR_CS_SEL]        = 12,
 476         [SPI_TCR_CS_MASK]       = 0x3000,
 477         [SPI_TCR_CS_MANUAL]     = BIT(16),
 478         [SPI_TCR_CS_LEVEL]      = BIT(17),
 479         [SPI_FCR_TF_RST]        = BIT(8),
 480         [SPI_FCR_RF_RST]        = BIT(9),
 481         [SPI_FSR_RF_CNT_MASK]   = GENMASK(6, 0),
 482 };
 483
 484 static const unsigned long sun6i_spi_regs[] = {
 485         [SPI_GCR]               = SUN6I_GBL_CTL_REG,
 486         [SPI_TCR]               = SUN6I_TFR_CTL_REG,
 487         [SPI_FCR]               = SUN6I_FIFO_CTL_REG,
 488         [SPI_FSR]               = SUN6I_FIFO_STA_REG,
 489         [SPI_CCR]               = SUN6I_CLK_CTL_REG,
 490         [SPI_BC]                = SUN6I_BURST_CNT_REG,
 491         [SPI_TC]                = SUN6I_XMIT_CNT_REG,
 492         [SPI_BCTL]              = SUN6I_BURST_CTL_REG,
 493         [SPI_TXD]               = SUN6I_TXDATA_REG,
 494         [SPI_RXD]               = SUN6I_RXDATA_REG,
 495 };
 496
 497 static const u32 sun6i_spi_bits[] = {
 498         [SPI_GCR_TP]            = BIT(7),
 499         [SPI_GCR_SRST]          = BIT(31),
 500         [SPI_TCR_CPHA]          = BIT(0),
 501         [SPI_TCR_CPOL]          = BIT(1),
 502         [SPI_TCR_CS_ACTIVE_LOW] = BIT(2),
 503         [SPI_TCR_CS_SEL]        = 4,
 504         [SPI_TCR_CS_MASK]       = 0x30,
 505         [SPI_TCR_CS_MANUAL]     = BIT(6),
 506         [SPI_TCR_CS_LEVEL]      = BIT(7),
 507         [SPI_TCR_XCH]           = BIT(31),
 508         [SPI_FCR_RF_RST]        = BIT(15),
 509         [SPI_FCR_TF_RST]        = BIT(31),
 510         [SPI_FSR_RF_CNT_MASK]   = GENMASK(7, 0),
 511 };
 512
 513 static const struct sun4i_spi_variant sun4i_a10_spi_variant = {
 514         .regs                   = sun4i_spi_regs,
 515         .bits                   = sun4i_spi_bits,
 516         .fifo_depth             = 64,
 517 };
 518
 519 static const struct sun4i_spi_variant sun6i_a31_spi_variant = {
 520         .regs                   = sun6i_spi_regs,
 521         .bits                   = sun6i_spi_bits,
 522         .fifo_depth             = 128,
 523         .has_soft_reset         = true,
 524         .has_burst_ctl          = true,
 525 };
 526
 527 static const struct sun4i_spi_variant sun8i_h3_spi_variant = {
 528         .regs                   = sun6i_spi_regs,
 529         .bits                   = sun6i_spi_bits,
 530         .fifo_depth             = 64,
 531         .has_soft_reset         = true,
 532         .has_burst_ctl          = true,
 533 };
 534
 535 static const struct udevice_id sun4i_spi_ids[] = {
 536         {
 537           .compatible = "allwinner,sun4i-a10-spi",
 538           .data = (ulong)&sun4i_a10_spi_variant,
 539         },
 540         {
 541           .compatible = "allwinner,sun6i-a31-spi",
 542           .data = (ulong)&sun6i_a31_spi_variant,
 543         },
 544         {
 545           .compatible = "allwinner,sun8i-h3-spi",
 546           .data = (ulong)&sun8i_h3_spi_variant,
 547         },
 548         { /* sentinel */ }
 549 };
 550
 551 U_BOOT_DRIVER(sun4i_spi) = {
 552         .name   = "sun4i_spi",
 553         .id     = UCLASS_SPI,
 554         .of_match       = sun4i_spi_ids,
 555         .ops    = &sun4i_spi_ops,
 556         .of_to_plat     = sun4i_spi_of_to_plat,
 557         .plat_auto      = sizeof(struct sun4i_spi_plat),
 558         .priv_auto      = sizeof(struct sun4i_spi_priv),
 559         .probe  = sun4i_spi_probe,
 560 };