drivers/spi/spi-sun6i.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2012 - 2014 Allwinner Tech
   4  * Pan Nan <pannan@allwinnertech.com>
   5  *
   6  * Copyright (C) 2014 Maxime Ripard
   7  * Maxime Ripard <maxime.ripard@free-electrons.com>
   8  */
   9
  10 #include <linux/bitfield.h>
  11 #include <linux/clk.h>
  12 #include <linux/delay.h>
  13 #include <linux/device.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/reset.h>
  21 #include <linux/dmaengine.h>
  22
  23 #include <linux/spi/spi.h>
  24
  25 #define SUN6I_AUTOSUSPEND_TIMEOUT       2000
  26
  27 #define SUN6I_FIFO_DEPTH                128
  28 #define SUN8I_FIFO_DEPTH                64
  29
  30 #define SUN6I_GBL_CTL_REG               0x04
  31 #define SUN6I_GBL_CTL_BUS_ENABLE                BIT(0)
  32 #define SUN6I_GBL_CTL_MASTER                    BIT(1)
  33 #define SUN6I_GBL_CTL_TP                        BIT(7)
  34 #define SUN6I_GBL_CTL_RST                       BIT(31)
  35
  36 #define SUN6I_TFR_CTL_REG               0x08
  37 #define SUN6I_TFR_CTL_CPHA                      BIT(0)
  38 #define SUN6I_TFR_CTL_CPOL                      BIT(1)
  39 #define SUN6I_TFR_CTL_SPOL                      BIT(2)
  40 #define SUN6I_TFR_CTL_CS_MASK                   0x30
  41 #define SUN6I_TFR_CTL_CS(cs)                    (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
  42 #define SUN6I_TFR_CTL_CS_MANUAL                 BIT(6)
  43 #define SUN6I_TFR_CTL_CS_LEVEL                  BIT(7)
  44 #define SUN6I_TFR_CTL_DHB                       BIT(8)
  45 #define SUN6I_TFR_CTL_SDC                       BIT(11)
  46 #define SUN6I_TFR_CTL_FBS                       BIT(12)
  47 #define SUN6I_TFR_CTL_SDM                       BIT(13)
  48 #define SUN6I_TFR_CTL_XCH                       BIT(31)
  49
  50 #define SUN6I_INT_CTL_REG               0x10
  51 #define SUN6I_INT_CTL_RF_RDY                    BIT(0)
  52 #define SUN6I_INT_CTL_TF_ERQ                    BIT(4)
  53 #define SUN6I_INT_CTL_RF_OVF                    BIT(8)
  54 #define SUN6I_INT_CTL_TC                        BIT(12)
  55
  56 #define SUN6I_INT_STA_REG               0x14
  57
  58 #define SUN6I_FIFO_CTL_REG              0x18
  59 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK   0xff
  60 #define SUN6I_FIFO_CTL_RF_DRQ_EN                BIT(8)
  61 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS   0
  62 #define SUN6I_FIFO_CTL_RF_RST                   BIT(15)
  63 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK   0xff
  64 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS   16
  65 #define SUN6I_FIFO_CTL_TF_DRQ_EN                BIT(24)
  66 #define SUN6I_FIFO_CTL_TF_RST                   BIT(31)
  67
  68 #define SUN6I_FIFO_STA_REG              0x1c
  69 #define SUN6I_FIFO_STA_RF_CNT_MASK              GENMASK(7, 0)
  70 #define SUN6I_FIFO_STA_TF_CNT_MASK              GENMASK(23, 16)
  71
  72 #define SUN6I_CLK_CTL_REG               0x24
  73 #define SUN6I_CLK_CTL_CDR2_MASK                 0xff
  74 #define SUN6I_CLK_CTL_CDR2(div)                 (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
  75 #define SUN6I_CLK_CTL_CDR1_MASK                 0xf
  76 #define SUN6I_CLK_CTL_CDR1(div)                 (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
  77 #define SUN6I_CLK_CTL_DRS                       BIT(12)
  78
  79 #define SUN6I_MAX_XFER_SIZE             0xffffff
  80
  81 #define SUN6I_BURST_CNT_REG             0x30
  82
  83 #define SUN6I_XMIT_CNT_REG              0x34
  84
  85 #define SUN6I_BURST_CTL_CNT_REG         0x38
  86 #define SUN6I_BURST_CTL_CNT_STC_MASK            GENMASK(23, 0)
  87 #define SUN6I_BURST_CTL_CNT_DRM                 BIT(28)
  88 #define SUN6I_BURST_CTL_CNT_QUAD_EN             BIT(29)
  89
  90 #define SUN6I_TXDATA_REG                0x200
  91 #define SUN6I_RXDATA_REG                0x300
  92
  93 struct sun6i_spi_cfg {
  94         unsigned long           fifo_depth;
  95         bool                    has_clk_ctl;
  96         u32                     mode_bits;
  97 };
  98
  99 struct sun6i_spi {
 100         struct spi_master       *master;
 101         void __iomem            *base_addr;
 102         dma_addr_t              dma_addr_rx;
 103         dma_addr_t              dma_addr_tx;
 104         struct clk              *hclk;
 105         struct clk              *mclk;
 106         struct reset_control    *rstc;
 107
 108         struct completion       done;
 109         struct completion       dma_rx_done;
 110
 111         const u8                *tx_buf;
 112         u8                      *rx_buf;
 113         int                     len;
 114         const struct sun6i_spi_cfg *cfg;
 115 };
 116
 117 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
 118 {
 119         return readl(sspi->base_addr + reg);
 120 }
 121
 122 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
 123 {
 124         writel(value, sspi->base_addr + reg);
 125 }
 126
 127 static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi)
 128 {
 129         u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
 130
 131         return FIELD_GET(SUN6I_FIFO_STA_RF_CNT_MASK, reg);
 132 }
 133
 134 static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
 135 {
 136         u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
 137
 138         return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg);
 139 }
 140
 141 static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
 142 {
 143         u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
 144
 145         reg &= ~mask;
 146         sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
 147 }
 148
 149 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi)
 150 {
 151         u32 len;
 152         u8 byte;
 153
 154         /* See how much data is available */
 155         len = sun6i_spi_get_rx_fifo_count(sspi);
 156
 157         while (len--) {
 158                 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
 159                 if (sspi->rx_buf)
 160                         *sspi->rx_buf++ = byte;
 161         }
 162 }
 163
 164 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi)
 165 {
 166         u32 cnt;
 167         int len;
 168         u8 byte;
 169
 170         /* See how much data we can fit */
 171         cnt = sspi->cfg->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
 172
 173         len = min((int)cnt, sspi->len);
 174
 175         while (len--) {
 176                 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
 177                 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
 178                 sspi->len--;
 179         }
 180 }
 181
 182 static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
 183 {
 184         struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
 185         u32 reg;
 186
 187         reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 188         reg &= ~SUN6I_TFR_CTL_CS_MASK;
 189         reg |= SUN6I_TFR_CTL_CS(spi_get_chipselect(spi, 0));
 190
 191         if (enable)
 192                 reg |= SUN6I_TFR_CTL_CS_LEVEL;
 193         else
 194                 reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
 195
 196         sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
 197 }
 198
 199 static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
 200 {
 201         return SUN6I_MAX_XFER_SIZE - 1;
 202 }
 203
 204 static void sun6i_spi_dma_rx_cb(void *param)
 205 {
 206         struct sun6i_spi *sspi = param;
 207
 208         complete(&sspi->dma_rx_done);
 209 }
 210
 211 static int sun6i_spi_prepare_dma(struct sun6i_spi *sspi,
 212                                  struct spi_transfer *tfr)
 213 {
 214         struct dma_async_tx_descriptor *rxdesc, *txdesc;
 215         struct spi_master *master = sspi->master;
 216
 217         rxdesc = NULL;
 218         if (tfr->rx_buf) {
 219                 struct dma_slave_config rxconf = {
 220                         .direction = DMA_DEV_TO_MEM,
 221                         .src_addr = sspi->dma_addr_rx,
 222                         .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
 223                         .src_maxburst = 8,
 224                 };
 225
 226                 dmaengine_slave_config(master->dma_rx, &rxconf);
 227
 228                 rxdesc = dmaengine_prep_slave_sg(master->dma_rx,
 229                                                  tfr->rx_sg.sgl,
 230                                                  tfr->rx_sg.nents,
 231                                                  DMA_DEV_TO_MEM,
 232                                                  DMA_PREP_INTERRUPT);
 233                 if (!rxdesc)
 234                         return -EINVAL;
 235                 rxdesc->callback_param = sspi;
 236                 rxdesc->callback = sun6i_spi_dma_rx_cb;
 237         }
 238
 239         txdesc = NULL;
 240         if (tfr->tx_buf) {
 241                 struct dma_slave_config txconf = {
 242                         .direction = DMA_MEM_TO_DEV,
 243                         .dst_addr = sspi->dma_addr_tx,
 244                         .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
 245                         .dst_maxburst = 8,
 246                 };
 247
 248                 dmaengine_slave_config(master->dma_tx, &txconf);
 249
 250                 txdesc = dmaengine_prep_slave_sg(master->dma_tx,
 251                                                  tfr->tx_sg.sgl,
 252                                                  tfr->tx_sg.nents,
 253                                                  DMA_MEM_TO_DEV,
 254                                                  DMA_PREP_INTERRUPT);
 255                 if (!txdesc) {
 256                         if (rxdesc)
 257                                 dmaengine_terminate_sync(master->dma_rx);
 258                         return -EINVAL;
 259                 }
 260         }
 261
 262         if (tfr->rx_buf) {
 263                 dmaengine_submit(rxdesc);
 264                 dma_async_issue_pending(master->dma_rx);
 265         }
 266
 267         if (tfr->tx_buf) {
 268                 dmaengine_submit(txdesc);
 269                 dma_async_issue_pending(master->dma_tx);
 270         }
 271
 272         return 0;
 273 }
 274
 275 static int sun6i_spi_transfer_one(struct spi_master *master,
 276                                   struct spi_device *spi,
 277                                   struct spi_transfer *tfr)
 278 {
 279         struct sun6i_spi *sspi = spi_master_get_devdata(master);
 280         unsigned int div, div_cdr1, div_cdr2, timeout;
 281         unsigned int start, end, tx_time;
 282         unsigned int trig_level;
 283         unsigned int tx_len = 0, rx_len = 0, nbits = 0;
 284         bool use_dma;
 285         int ret = 0;
 286         u32 reg;
 287
 288         if (tfr->len > SUN6I_MAX_XFER_SIZE)
 289                 return -EINVAL;
 290
 291         reinit_completion(&sspi->done);
 292         reinit_completion(&sspi->dma_rx_done);
 293         sspi->tx_buf = tfr->tx_buf;
 294         sspi->rx_buf = tfr->rx_buf;
 295         sspi->len = tfr->len;
 296         use_dma = master->can_dma ? master->can_dma(master, spi, tfr) : false;
 297
 298         /* Clear pending interrupts */
 299         sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
 300
 301         /* Reset FIFO */
 302         sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
 303                         SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
 304
 305         reg = 0;
 306
 307         if (!use_dma) {
 308                 /*
 309                  * Setup FIFO interrupt trigger level
 310                  * Here we choose 3/4 of the full fifo depth, as it's
 311                  * the hardcoded value used in old generation of Allwinner
 312                  * SPI controller. (See spi-sun4i.c)
 313                  */
 314                 trig_level = sspi->cfg->fifo_depth / 4 * 3;
 315         } else {
 316                 /*
 317                  * Setup FIFO DMA request trigger level
 318                  * We choose 1/2 of the full fifo depth, that value will
 319                  * be used as DMA burst length.
 320                  */
 321                 trig_level = sspi->cfg->fifo_depth / 2;
 322
 323                 if (tfr->tx_buf)
 324                         reg |= SUN6I_FIFO_CTL_TF_DRQ_EN;
 325                 if (tfr->rx_buf)
 326                         reg |= SUN6I_FIFO_CTL_RF_DRQ_EN;
 327         }
 328
 329         reg |= (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
 330                (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS);
 331
 332         sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, reg);
 333
 334         /*
 335          * Setup the transfer control register: Chip Select,
 336          * polarities, etc.
 337          */
 338         reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 339
 340         if (spi->mode & SPI_CPOL)
 341                 reg |= SUN6I_TFR_CTL_CPOL;
 342         else
 343                 reg &= ~SUN6I_TFR_CTL_CPOL;
 344
 345         if (spi->mode & SPI_CPHA)
 346                 reg |= SUN6I_TFR_CTL_CPHA;
 347         else
 348                 reg &= ~SUN6I_TFR_CTL_CPHA;
 349
 350         if (spi->mode & SPI_LSB_FIRST)
 351                 reg |= SUN6I_TFR_CTL_FBS;
 352         else
 353                 reg &= ~SUN6I_TFR_CTL_FBS;
 354
 355         /*
 356          * If it's a TX only transfer, we don't want to fill the RX
 357          * FIFO with bogus data
 358          */
 359         if (sspi->rx_buf) {
 360                 reg &= ~SUN6I_TFR_CTL_DHB;
 361                 rx_len = tfr->len;
 362         } else {
 363                 reg |= SUN6I_TFR_CTL_DHB;
 364         }
 365
 366         /* We want to control the chip select manually */
 367         reg |= SUN6I_TFR_CTL_CS_MANUAL;
 368
 369         sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
 370
 371         if (sspi->cfg->has_clk_ctl) {
 372                 unsigned int mclk_rate = clk_get_rate(sspi->mclk);
 373
 374                 /* Ensure that we have a parent clock fast enough */
 375                 if (mclk_rate < (2 * tfr->speed_hz)) {
 376                         clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
 377                         mclk_rate = clk_get_rate(sspi->mclk);
 378                 }
 379
 380                 /*
 381                  * Setup clock divider.
 382                  *
 383                  * We have two choices there. Either we can use the clock
 384                  * divide rate 1, which is calculated thanks to this formula:
 385                  * SPI_CLK = MOD_CLK / (2 ^ cdr)
 386                  * Or we can use CDR2, which is calculated with the formula:
 387                  * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
 388                  * Wether we use the former or the latter is set through the
 389                  * DRS bit.
 390                  *
 391                  * First try CDR2, and if we can't reach the expected
 392                  * frequency, fall back to CDR1.
 393                  */
 394                 div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
 395                 div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
 396                 if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
 397                         reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
 398                         tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
 399                 } else {
 400                         div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
 401                         reg = SUN6I_CLK_CTL_CDR1(div);
 402                         tfr->effective_speed_hz = mclk_rate / (1 << div);
 403                 }
 404
 405                 sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
 406         } else {
 407                 clk_set_rate(sspi->mclk, tfr->speed_hz);
 408                 tfr->effective_speed_hz = clk_get_rate(sspi->mclk);
 409
 410                 /*
 411                  * Configure work mode.
 412                  *
 413                  * There are three work modes depending on the controller clock
 414                  * frequency:
 415                  * - normal sample mode           : CLK <= 24MHz SDM=1 SDC=0
 416                  * - delay half-cycle sample mode : CLK <= 40MHz SDM=0 SDC=0
 417                  * - delay one-cycle sample mode  : CLK >= 80MHz SDM=0 SDC=1
 418                  */
 419                 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 420                 reg &= ~(SUN6I_TFR_CTL_SDM | SUN6I_TFR_CTL_SDC);
 421
 422                 if (tfr->effective_speed_hz <= 24000000)
 423                         reg |= SUN6I_TFR_CTL_SDM;
 424                 else if (tfr->effective_speed_hz >= 80000000)
 425                         reg |= SUN6I_TFR_CTL_SDC;
 426
 427                 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
 428         }
 429
 430         /* Finally enable the bus - doing so before might raise SCK to HIGH */
 431         reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG);
 432         reg |= SUN6I_GBL_CTL_BUS_ENABLE;
 433         sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg);
 434
 435         /* Setup the transfer now... */
 436         if (sspi->tx_buf) {
 437                 tx_len = tfr->len;
 438                 nbits = tfr->tx_nbits;
 439         } else if (tfr->rx_buf) {
 440                 nbits = tfr->rx_nbits;
 441         }
 442
 443         switch (nbits) {
 444         case SPI_NBITS_DUAL:
 445                 reg = SUN6I_BURST_CTL_CNT_DRM;
 446                 break;
 447         case SPI_NBITS_QUAD:
 448                 reg = SUN6I_BURST_CTL_CNT_QUAD_EN;
 449                 break;
 450         case SPI_NBITS_SINGLE:
 451         default:
 452                 reg = FIELD_PREP(SUN6I_BURST_CTL_CNT_STC_MASK, tx_len);
 453         }
 454
 455         /* Setup the counters */
 456         sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, reg);
 457         sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
 458         sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
 459
 460         if (!use_dma) {
 461                 /* Fill the TX FIFO */
 462                 sun6i_spi_fill_fifo(sspi);
 463         } else {
 464                 ret = sun6i_spi_prepare_dma(sspi, tfr);
 465                 if (ret) {
 466                         dev_warn(&master->dev,
 467                                  "%s: prepare DMA failed, ret=%d",
 468                                  dev_name(&spi->dev), ret);
 469                         return ret;
 470                 }
 471         }
 472
 473         /* Enable the interrupts */
 474         reg = SUN6I_INT_CTL_TC;
 475
 476         if (!use_dma) {
 477                 if (rx_len > sspi->cfg->fifo_depth)
 478                         reg |= SUN6I_INT_CTL_RF_RDY;
 479                 if (tx_len > sspi->cfg->fifo_depth)
 480                         reg |= SUN6I_INT_CTL_TF_ERQ;
 481         }
 482
 483         sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
 484
 485         /* Start the transfer */
 486         reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 487         sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
 488
 489         tx_time = spi_controller_xfer_timeout(master, tfr);
 490         start = jiffies;
 491         timeout = wait_for_completion_timeout(&sspi->done,
 492                                               msecs_to_jiffies(tx_time));
 493
 494         if (!use_dma) {
 495                 sun6i_spi_drain_fifo(sspi);
 496         } else {
 497                 if (timeout && rx_len) {
 498                         /*
 499                          * Even though RX on the peripheral side has finished
 500                          * RX DMA might still be in flight
 501                          */
 502                         timeout = wait_for_completion_timeout(&sspi->dma_rx_done,
 503                                                               timeout);
 504                         if (!timeout)
 505                                 dev_warn(&master->dev, "RX DMA timeout\n");
 506                 }
 507         }
 508
 509         end = jiffies;
 510         if (!timeout) {
 511                 dev_warn(&master->dev,
 512                          "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
 513                          dev_name(&spi->dev), tfr->len, tfr->speed_hz,
 514                          jiffies_to_msecs(end - start), tx_time);
 515                 ret = -ETIMEDOUT;
 516         }
 517
 518         sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
 519
 520         if (ret && use_dma) {
 521                 dmaengine_terminate_sync(master->dma_rx);
 522                 dmaengine_terminate_sync(master->dma_tx);
 523         }
 524
 525         return ret;
 526 }
 527
 528 static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
 529 {
 530         struct sun6i_spi *sspi = dev_id;
 531         u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
 532
 533         /* Transfer complete */
 534         if (status & SUN6I_INT_CTL_TC) {
 535                 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
 536                 complete(&sspi->done);
 537                 return IRQ_HANDLED;
 538         }
 539
 540         /* Receive FIFO 3/4 full */
 541         if (status & SUN6I_INT_CTL_RF_RDY) {
 542                 sun6i_spi_drain_fifo(sspi);
 543                 /* Only clear the interrupt _after_ draining the FIFO */
 544                 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
 545                 return IRQ_HANDLED;
 546         }
 547
 548         /* Transmit FIFO 3/4 empty */
 549         if (status & SUN6I_INT_CTL_TF_ERQ) {
 550                 sun6i_spi_fill_fifo(sspi);
 551
 552                 if (!sspi->len)
 553                         /* nothing left to transmit */
 554                         sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
 555
 556                 /* Only clear the interrupt _after_ re-seeding the FIFO */
 557                 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
 558
 559                 return IRQ_HANDLED;
 560         }
 561
 562         return IRQ_NONE;
 563 }
 564
 565 static int sun6i_spi_runtime_resume(struct device *dev)
 566 {
 567         struct spi_master *master = dev_get_drvdata(dev);
 568         struct sun6i_spi *sspi = spi_master_get_devdata(master);
 569         int ret;
 570
 571         ret = clk_prepare_enable(sspi->hclk);
 572         if (ret) {
 573                 dev_err(dev, "Couldn't enable AHB clock\n");
 574                 goto out;
 575         }
 576
 577         ret = clk_prepare_enable(sspi->mclk);
 578         if (ret) {
 579                 dev_err(dev, "Couldn't enable module clock\n");
 580                 goto err;
 581         }
 582
 583         ret = reset_control_deassert(sspi->rstc);
 584         if (ret) {
 585                 dev_err(dev, "Couldn't deassert the device from reset\n");
 586                 goto err2;
 587         }
 588
 589         sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
 590                         SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
 591
 592         return 0;
 593
 594 err2:
 595         clk_disable_unprepare(sspi->mclk);
 596 err:
 597         clk_disable_unprepare(sspi->hclk);
 598 out:
 599         return ret;
 600 }
 601
 602 static int sun6i_spi_runtime_suspend(struct device *dev)
 603 {
 604         struct spi_master *master = dev_get_drvdata(dev);
 605         struct sun6i_spi *sspi = spi_master_get_devdata(master);
 606
 607         reset_control_assert(sspi->rstc);
 608         clk_disable_unprepare(sspi->mclk);
 609         clk_disable_unprepare(sspi->hclk);
 610
 611         return 0;
 612 }
 613
 614 static bool sun6i_spi_can_dma(struct spi_master *master,
 615                               struct spi_device *spi,
 616                               struct spi_transfer *xfer)
 617 {
 618         struct sun6i_spi *sspi = spi_master_get_devdata(master);
 619
 620         /*
 621          * If the number of spi words to transfer is less or equal than
 622          * the fifo length we can just fill the fifo and wait for a single
 623          * irq, so don't bother setting up dma
 624          */
 625         return xfer->len > sspi->cfg->fifo_depth;
 626 }
 627
 628 static int sun6i_spi_probe(struct platform_device *pdev)
 629 {
 630         struct spi_master *master;
 631         struct sun6i_spi *sspi;
 632         struct resource *mem;
 633         int ret = 0, irq;
 634
 635         master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
 636         if (!master) {
 637                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
 638                 return -ENOMEM;
 639         }
 640
 641         platform_set_drvdata(pdev, master);
 642         sspi = spi_master_get_devdata(master);
 643
 644         sspi->base_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
 645         if (IS_ERR(sspi->base_addr)) {
 646                 ret = PTR_ERR(sspi->base_addr);
 647                 goto err_free_master;
 648         }
 649
 650         irq = platform_get_irq(pdev, 0);
 651         if (irq < 0) {
 652                 ret = -ENXIO;
 653                 goto err_free_master;
 654         }
 655
 656         ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
 657                                0, "sun6i-spi", sspi);
 658         if (ret) {
 659                 dev_err(&pdev->dev, "Cannot request IRQ\n");
 660                 goto err_free_master;
 661         }
 662
 663         sspi->master = master;
 664         sspi->cfg = of_device_get_match_data(&pdev->dev);
 665
 666         master->max_speed_hz = 100 * 1000 * 1000;
 667         master->min_speed_hz = 3 * 1000;
 668         master->use_gpio_descriptors = true;
 669         master->set_cs = sun6i_spi_set_cs;
 670         master->transfer_one = sun6i_spi_transfer_one;
 671         master->num_chipselect = 4;
 672         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
 673                             sspi->cfg->mode_bits;
 674         master->bits_per_word_mask = SPI_BPW_MASK(8);
 675         master->dev.of_node = pdev->dev.of_node;
 676         master->auto_runtime_pm = true;
 677         master->max_transfer_size = sun6i_spi_max_transfer_size;
 678
 679         sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
 680         if (IS_ERR(sspi->hclk)) {
 681                 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
 682                 ret = PTR_ERR(sspi->hclk);
 683                 goto err_free_master;
 684         }
 685
 686         sspi->mclk = devm_clk_get(&pdev->dev, "mod");
 687         if (IS_ERR(sspi->mclk)) {
 688                 dev_err(&pdev->dev, "Unable to acquire module clock\n");
 689                 ret = PTR_ERR(sspi->mclk);
 690                 goto err_free_master;
 691         }
 692
 693         init_completion(&sspi->done);
 694         init_completion(&sspi->dma_rx_done);
 695
 696         sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 697         if (IS_ERR(sspi->rstc)) {
 698                 dev_err(&pdev->dev, "Couldn't get reset controller\n");
 699                 ret = PTR_ERR(sspi->rstc);
 700                 goto err_free_master;
 701         }
 702
 703         master->dma_tx = dma_request_chan(&pdev->dev, "tx");
 704         if (IS_ERR(master->dma_tx)) {
 705                 /* Check tx to see if we need defer probing driver */
 706                 if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) {
 707                         ret = -EPROBE_DEFER;
 708                         goto err_free_master;
 709                 }
 710                 dev_warn(&pdev->dev, "Failed to request TX DMA channel\n");
 711                 master->dma_tx = NULL;
 712         }
 713
 714         master->dma_rx = dma_request_chan(&pdev->dev, "rx");
 715         if (IS_ERR(master->dma_rx)) {
 716                 if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) {
 717                         ret = -EPROBE_DEFER;
 718                         goto err_free_dma_tx;
 719                 }
 720                 dev_warn(&pdev->dev, "Failed to request RX DMA channel\n");
 721                 master->dma_rx = NULL;
 722         }
 723
 724         if (master->dma_tx && master->dma_rx) {
 725                 sspi->dma_addr_tx = mem->start + SUN6I_TXDATA_REG;
 726                 sspi->dma_addr_rx = mem->start + SUN6I_RXDATA_REG;
 727                 master->can_dma = sun6i_spi_can_dma;
 728         }
 729
 730         /*
 731          * This wake-up/shutdown pattern is to be able to have the
 732          * device woken up, even if runtime_pm is disabled
 733          */
 734         ret = sun6i_spi_runtime_resume(&pdev->dev);
 735         if (ret) {
 736                 dev_err(&pdev->dev, "Couldn't resume the device\n");
 737                 goto err_free_dma_rx;
 738         }
 739
 740         pm_runtime_set_autosuspend_delay(&pdev->dev, SUN6I_AUTOSUSPEND_TIMEOUT);
 741         pm_runtime_use_autosuspend(&pdev->dev);
 742         pm_runtime_set_active(&pdev->dev);
 743         pm_runtime_enable(&pdev->dev);
 744
 745         ret = devm_spi_register_master(&pdev->dev, master);
 746         if (ret) {
 747                 dev_err(&pdev->dev, "cannot register SPI master\n");
 748                 goto err_pm_disable;
 749         }
 750
 751         return 0;
 752
 753 err_pm_disable:
 754         pm_runtime_disable(&pdev->dev);
 755         sun6i_spi_runtime_suspend(&pdev->dev);
 756 err_free_dma_rx:
 757         if (master->dma_rx)
 758                 dma_release_channel(master->dma_rx);
 759 err_free_dma_tx:
 760         if (master->dma_tx)
 761                 dma_release_channel(master->dma_tx);
 762 err_free_master:
 763         spi_master_put(master);
 764         return ret;
 765 }
 766
 767 static void sun6i_spi_remove(struct platform_device *pdev)
 768 {
 769         struct spi_master *master = platform_get_drvdata(pdev);
 770
 771         pm_runtime_force_suspend(&pdev->dev);
 772
 773         if (master->dma_tx)
 774                 dma_release_channel(master->dma_tx);
 775         if (master->dma_rx)
 776                 dma_release_channel(master->dma_rx);
 777 }
 778
 779 static const struct sun6i_spi_cfg sun6i_a31_spi_cfg = {
 780         .fifo_depth     = SUN6I_FIFO_DEPTH,
 781         .has_clk_ctl    = true,
 782 };
 783
 784 static const struct sun6i_spi_cfg sun8i_h3_spi_cfg = {
 785         .fifo_depth     = SUN8I_FIFO_DEPTH,
 786         .has_clk_ctl    = true,
 787 };
 788
 789 static const struct sun6i_spi_cfg sun50i_r329_spi_cfg = {
 790         .fifo_depth     = SUN8I_FIFO_DEPTH,
 791         .mode_bits      = SPI_RX_DUAL | SPI_TX_DUAL | SPI_RX_QUAD | SPI_TX_QUAD,
 792 };
 793
 794 static const struct of_device_id sun6i_spi_match[] = {
 795         { .compatible = "allwinner,sun6i-a31-spi", .data = &sun6i_a31_spi_cfg },
 796         { .compatible = "allwinner,sun8i-h3-spi",  .data = &sun8i_h3_spi_cfg },
 797         {
 798                 .compatible = "allwinner,sun50i-r329-spi",
 799                 .data = &sun50i_r329_spi_cfg
 800         },
 801         {}
 802 };
 803 MODULE_DEVICE_TABLE(of, sun6i_spi_match);
 804
 805 static const struct dev_pm_ops sun6i_spi_pm_ops = {
 806         .runtime_resume         = sun6i_spi_runtime_resume,
 807         .runtime_suspend        = sun6i_spi_runtime_suspend,
 808 };
 809
 810 static struct platform_driver sun6i_spi_driver = {
 811         .probe  = sun6i_spi_probe,
 812         .remove_new = sun6i_spi_remove,
 813         .driver = {
 814                 .name           = "sun6i-spi",
 815                 .of_match_table = sun6i_spi_match,
 816                 .pm             = &sun6i_spi_pm_ops,
 817         },
 818 };
 819 module_platform_driver(sun6i_spi_driver);
 820
 821 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
 822 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
 823 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
 824 MODULE_LICENSE("GPL");