1 // SPDX-License-Identifier: GPL-2.0
3 // STMicroelectronics STM32 SPI Controller driver (master mode only)
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 // Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
8 #include <linux/debugfs.h>
10 #include <linux/delay.h>
11 #include <linux/dmaengine.h>
12 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
14 #include <linux/module.h>
15 #include <linux/of_platform.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/reset.h>
19 #include <linux/spi/spi.h>
21 #define DRIVER_NAME "spi_stm32"
23 /* STM32F4 SPI registers */
24 #define STM32F4_SPI_CR1 0x00
25 #define STM32F4_SPI_CR2 0x04
26 #define STM32F4_SPI_SR 0x08
27 #define STM32F4_SPI_DR 0x0C
28 #define STM32F4_SPI_I2SCFGR 0x1C
30 /* STM32F4_SPI_CR1 bit fields */
31 #define STM32F4_SPI_CR1_CPHA BIT(0)
32 #define STM32F4_SPI_CR1_CPOL BIT(1)
33 #define STM32F4_SPI_CR1_MSTR BIT(2)
34 #define STM32F4_SPI_CR1_BR_SHIFT 3
35 #define STM32F4_SPI_CR1_BR GENMASK(5, 3)
36 #define STM32F4_SPI_CR1_SPE BIT(6)
37 #define STM32F4_SPI_CR1_LSBFRST BIT(7)
38 #define STM32F4_SPI_CR1_SSI BIT(8)
39 #define STM32F4_SPI_CR1_SSM BIT(9)
40 #define STM32F4_SPI_CR1_RXONLY BIT(10)
41 #define STM32F4_SPI_CR1_DFF BIT(11)
42 #define STM32F4_SPI_CR1_CRCNEXT BIT(12)
43 #define STM32F4_SPI_CR1_CRCEN BIT(13)
44 #define STM32F4_SPI_CR1_BIDIOE BIT(14)
45 #define STM32F4_SPI_CR1_BIDIMODE BIT(15)
46 #define STM32F4_SPI_CR1_BR_MIN 0
47 #define STM32F4_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3)
49 /* STM32F4_SPI_CR2 bit fields */
50 #define STM32F4_SPI_CR2_RXDMAEN BIT(0)
51 #define STM32F4_SPI_CR2_TXDMAEN BIT(1)
52 #define STM32F4_SPI_CR2_SSOE BIT(2)
53 #define STM32F4_SPI_CR2_FRF BIT(4)
54 #define STM32F4_SPI_CR2_ERRIE BIT(5)
55 #define STM32F4_SPI_CR2_RXNEIE BIT(6)
56 #define STM32F4_SPI_CR2_TXEIE BIT(7)
58 /* STM32F4_SPI_SR bit fields */
59 #define STM32F4_SPI_SR_RXNE BIT(0)
60 #define STM32F4_SPI_SR_TXE BIT(1)
61 #define STM32F4_SPI_SR_CHSIDE BIT(2)
62 #define STM32F4_SPI_SR_UDR BIT(3)
63 #define STM32F4_SPI_SR_CRCERR BIT(4)
64 #define STM32F4_SPI_SR_MODF BIT(5)
65 #define STM32F4_SPI_SR_OVR BIT(6)
66 #define STM32F4_SPI_SR_BSY BIT(7)
67 #define STM32F4_SPI_SR_FRE BIT(8)
69 /* STM32F4_SPI_I2SCFGR bit fields */
70 #define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11)
72 /* STM32F4 SPI Baud Rate min/max divisor */
73 #define STM32F4_SPI_BR_DIV_MIN (2 << STM32F4_SPI_CR1_BR_MIN)
74 #define STM32F4_SPI_BR_DIV_MAX (2 << STM32F4_SPI_CR1_BR_MAX)
76 /* STM32H7 SPI registers */
77 #define STM32H7_SPI_CR1 0x00
78 #define STM32H7_SPI_CR2 0x04
79 #define STM32H7_SPI_CFG1 0x08
80 #define STM32H7_SPI_CFG2 0x0C
81 #define STM32H7_SPI_IER 0x10
82 #define STM32H7_SPI_SR 0x14
83 #define STM32H7_SPI_IFCR 0x18
84 #define STM32H7_SPI_TXDR 0x20
85 #define STM32H7_SPI_RXDR 0x30
86 #define STM32H7_SPI_I2SCFGR 0x50
88 /* STM32H7_SPI_CR1 bit fields */
89 #define STM32H7_SPI_CR1_SPE BIT(0)
90 #define STM32H7_SPI_CR1_MASRX BIT(8)
91 #define STM32H7_SPI_CR1_CSTART BIT(9)
92 #define STM32H7_SPI_CR1_CSUSP BIT(10)
93 #define STM32H7_SPI_CR1_HDDIR BIT(11)
94 #define STM32H7_SPI_CR1_SSI BIT(12)
96 /* STM32H7_SPI_CR2 bit fields */
97 #define STM32H7_SPI_CR2_TSIZE_SHIFT 0
98 #define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
100 /* STM32H7_SPI_CFG1 bit fields */
101 #define STM32H7_SPI_CFG1_DSIZE_SHIFT 0
102 #define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
103 #define STM32H7_SPI_CFG1_FTHLV_SHIFT 5
104 #define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
105 #define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
106 #define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
107 #define STM32H7_SPI_CFG1_MBR_SHIFT 28
108 #define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
109 #define STM32H7_SPI_CFG1_MBR_MIN 0
110 #define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
112 /* STM32H7_SPI_CFG2 bit fields */
113 #define STM32H7_SPI_CFG2_MIDI_SHIFT 4
114 #define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
115 #define STM32H7_SPI_CFG2_COMM_SHIFT 17
116 #define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
117 #define STM32H7_SPI_CFG2_SP_SHIFT 19
118 #define STM32H7_SPI_CFG2_SP GENMASK(21, 19)
119 #define STM32H7_SPI_CFG2_MASTER BIT(22)
120 #define STM32H7_SPI_CFG2_LSBFRST BIT(23)
121 #define STM32H7_SPI_CFG2_CPHA BIT(24)
122 #define STM32H7_SPI_CFG2_CPOL BIT(25)
123 #define STM32H7_SPI_CFG2_SSM BIT(26)
124 #define STM32H7_SPI_CFG2_AFCNTR BIT(31)
126 /* STM32H7_SPI_IER bit fields */
127 #define STM32H7_SPI_IER_RXPIE BIT(0)
128 #define STM32H7_SPI_IER_TXPIE BIT(1)
129 #define STM32H7_SPI_IER_DXPIE BIT(2)
130 #define STM32H7_SPI_IER_EOTIE BIT(3)
131 #define STM32H7_SPI_IER_TXTFIE BIT(4)
132 #define STM32H7_SPI_IER_OVRIE BIT(6)
133 #define STM32H7_SPI_IER_MODFIE BIT(9)
134 #define STM32H7_SPI_IER_ALL GENMASK(10, 0)
136 /* STM32H7_SPI_SR bit fields */
137 #define STM32H7_SPI_SR_RXP BIT(0)
138 #define STM32H7_SPI_SR_TXP BIT(1)
139 #define STM32H7_SPI_SR_EOT BIT(3)
140 #define STM32H7_SPI_SR_OVR BIT(6)
141 #define STM32H7_SPI_SR_MODF BIT(9)
142 #define STM32H7_SPI_SR_SUSP BIT(11)
143 #define STM32H7_SPI_SR_RXPLVL_SHIFT 13
144 #define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
145 #define STM32H7_SPI_SR_RXWNE BIT(15)
147 /* STM32H7_SPI_IFCR bit fields */
148 #define STM32H7_SPI_IFCR_ALL GENMASK(11, 3)
150 /* STM32H7_SPI_I2SCFGR bit fields */
151 #define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0)
153 /* STM32H7 SPI Master Baud Rate min/max divisor */
154 #define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN)
155 #define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX)
157 /* STM32H7 SPI Communication mode */
158 #define STM32H7_SPI_FULL_DUPLEX 0
159 #define STM32H7_SPI_SIMPLEX_TX 1
160 #define STM32H7_SPI_SIMPLEX_RX 2
161 #define STM32H7_SPI_HALF_DUPLEX 3
163 /* SPI Communication type */
164 #define SPI_FULL_DUPLEX 0
165 #define SPI_SIMPLEX_TX 1
166 #define SPI_SIMPLEX_RX 2
167 #define SPI_3WIRE_TX 3
168 #define SPI_3WIRE_RX 4
170 #define SPI_1HZ_NS 1000000000
173 * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
174 * without fifo buffers.
176 #define SPI_DMA_MIN_BYTES 16
179 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
180 * @reg: register offset
181 * @mask: bitfield mask
184 struct stm32_spi_reg {
191 * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
192 * @en: enable register and SPI enable bit
193 * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
194 * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
195 * @cpol: clock polarity register and polarity bit
196 * @cpha: clock phase register and phase bit
197 * @lsb_first: LSB transmitted first register and bit
198 * @br: baud rate register and bitfields
199 * @rx: SPI RX data register
200 * @tx: SPI TX data register
202 struct stm32_spi_regspec {
203 const struct stm32_spi_reg en;
204 const struct stm32_spi_reg dma_rx_en;
205 const struct stm32_spi_reg dma_tx_en;
206 const struct stm32_spi_reg cpol;
207 const struct stm32_spi_reg cpha;
208 const struct stm32_spi_reg lsb_first;
209 const struct stm32_spi_reg br;
210 const struct stm32_spi_reg rx;
211 const struct stm32_spi_reg tx;
217 * struct stm32_spi_cfg - stm32 compatible configuration data
218 * @regs: registers descriptions
219 * @get_fifo_size: routine to get fifo size
220 * @get_bpw_mask: routine to get bits per word mask
221 * @disable: routine to disable controller
222 * @config: routine to configure controller as SPI Master
223 * @set_bpw: routine to configure registers to for bits per word
224 * @set_mode: routine to configure registers to desired mode
225 * @set_data_idleness: optional routine to configure registers to desired idle
226 * time between frames (if driver has this functionality)
227 * @set_number_of_data: optional routine to configure registers to desired
228 * number of data (if driver has this functionality)
229 * @can_dma: routine to determine if the transfer is eligible for DMA use
230 * @transfer_one_dma_start: routine to start transfer a single spi_transfer
232 * @dma_rx_cb: routine to call after DMA RX channel operation is complete
233 * @dma_tx_cb: routine to call after DMA TX channel operation is complete
234 * @transfer_one_irq: routine to configure interrupts for driver
235 * @irq_handler_event: Interrupt handler for SPI controller events
236 * @irq_handler_thread: thread of interrupt handler for SPI controller
237 * @baud_rate_div_min: minimum baud rate divisor
238 * @baud_rate_div_max: maximum baud rate divisor
239 * @has_fifo: boolean to know if fifo is used for driver
240 * @has_startbit: boolean to know if start bit is used to start transfer
242 struct stm32_spi_cfg {
243 const struct stm32_spi_regspec *regs;
244 int (*get_fifo_size)(struct stm32_spi *spi);
245 int (*get_bpw_mask)(struct stm32_spi *spi);
246 void (*disable)(struct stm32_spi *spi);
247 int (*config)(struct stm32_spi *spi);
248 void (*set_bpw)(struct stm32_spi *spi);
249 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
250 void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
251 int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
252 void (*transfer_one_dma_start)(struct stm32_spi *spi);
253 void (*dma_rx_cb)(void *data);
254 void (*dma_tx_cb)(void *data);
255 int (*transfer_one_irq)(struct stm32_spi *spi);
256 irqreturn_t (*irq_handler_event)(int irq, void *dev_id);
257 irqreturn_t (*irq_handler_thread)(int irq, void *dev_id);
258 unsigned int baud_rate_div_min;
259 unsigned int baud_rate_div_max;
264 * struct stm32_spi - private data of the SPI controller
265 * @dev: driver model representation of the controller
266 * @master: controller master interface
267 * @cfg: compatible configuration data
268 * @base: virtual memory area
269 * @clk: hw kernel clock feeding the SPI clock generator
270 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
271 * @rst: SPI controller reset line
272 * @lock: prevent I/O concurrent access
273 * @irq: SPI controller interrupt line
274 * @fifo_size: size of the embedded fifo in bytes
275 * @cur_midi: master inter-data idleness in ns
276 * @cur_speed: speed configured in Hz
277 * @cur_bpw: number of bits in a single SPI data frame
278 * @cur_fthlv: fifo threshold level (data frames in a single data packet)
279 * @cur_comm: SPI communication mode
280 * @cur_xferlen: current transfer length in bytes
281 * @cur_usedma: boolean to know if dma is used in current transfer
282 * @tx_buf: data to be written, or NULL
283 * @rx_buf: data to be read, or NULL
284 * @tx_len: number of data to be written in bytes
285 * @rx_len: number of data to be read in bytes
286 * @dma_tx: dma channel for TX transfer
287 * @dma_rx: dma channel for RX transfer
288 * @phys_addr: SPI registers physical base address
292 struct spi_master *master;
293 const struct stm32_spi_cfg *cfg;
297 struct reset_control *rst;
298 spinlock_t lock; /* prevent I/O concurrent access */
300 unsigned int fifo_size;
302 unsigned int cur_midi;
303 unsigned int cur_speed;
304 unsigned int cur_bpw;
305 unsigned int cur_fthlv;
306 unsigned int cur_comm;
307 unsigned int cur_xferlen;
314 struct dma_chan *dma_tx;
315 struct dma_chan *dma_rx;
316 dma_addr_t phys_addr;
319 static const struct stm32_spi_regspec stm32f4_spi_regspec = {
320 .en = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE },
322 .dma_rx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN },
323 .dma_tx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN },
325 .cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL },
326 .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA },
327 .lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST },
328 .br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT },
330 .rx = { STM32F4_SPI_DR },
331 .tx = { STM32F4_SPI_DR },
334 static const struct stm32_spi_regspec stm32h7_spi_regspec = {
335 /* SPI data transfer is enabled but spi_ker_ck is idle.
336 * CFG1 and CFG2 registers are write protected when SPE is enabled.
338 .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
340 .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN },
341 .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN },
343 .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
344 .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
345 .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
346 .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
347 STM32H7_SPI_CFG1_MBR_SHIFT },
349 .rx = { STM32H7_SPI_RXDR },
350 .tx = { STM32H7_SPI_TXDR },
353 static inline void stm32_spi_set_bits(struct stm32_spi *spi,
354 u32 offset, u32 bits)
356 writel_relaxed(readl_relaxed(spi->base + offset) | bits,
360 static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
361 u32 offset, u32 bits)
363 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
368 * stm32h7_spi_get_fifo_size - Return fifo size
369 * @spi: pointer to the spi controller data structure
371 static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
376 spin_lock_irqsave(&spi->lock, flags);
378 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
380 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
381 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
383 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
385 spin_unlock_irqrestore(&spi->lock, flags);
387 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
393 * stm32f4_spi_get_bpw_mask - Return bits per word mask
394 * @spi: pointer to the spi controller data structure
396 static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
398 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
399 return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
403 * stm32h7_spi_get_bpw_mask - Return bits per word mask
404 * @spi: pointer to the spi controller data structure
406 static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
411 spin_lock_irqsave(&spi->lock, flags);
414 * The most significant bit at DSIZE bit field is reserved when the
415 * maximum data size of periperal instances is limited to 16-bit
417 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
419 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
420 max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >>
421 STM32H7_SPI_CFG1_DSIZE_SHIFT;
424 spin_unlock_irqrestore(&spi->lock, flags);
426 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
428 return SPI_BPW_RANGE_MASK(4, max_bpw);
432 * stm32_spi_prepare_mbr - Determine baud rate divisor value
433 * @spi: pointer to the spi controller data structure
434 * @speed_hz: requested speed
435 * @min_div: minimum baud rate divisor
436 * @max_div: maximum baud rate divisor
438 * Return baud rate divisor value in case of success or -EINVAL
440 static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
441 u32 min_div, u32 max_div)
445 /* Ensure spi->clk_rate is even */
446 div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz);
449 * SPI framework set xfer->speed_hz to master->max_speed_hz if
450 * xfer->speed_hz is greater than master->max_speed_hz, and it returns
451 * an error when xfer->speed_hz is lower than master->min_speed_hz, so
452 * no need to check it there.
453 * However, we need to ensure the following calculations.
455 if ((div < min_div) || (div > max_div))
458 /* Determine the first power of 2 greater than or equal to div */
462 mbrdiv = fls(div) - 1;
464 spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
470 * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
471 * @spi: pointer to the spi controller data structure
472 * @xfer_len: length of the message to be transferred
474 static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
478 /* data packet should not exceed 1/2 of fifo space */
479 packet = clamp(xfer_len, 1U, spi->fifo_size / 2);
481 /* align packet size with data registers access */
482 bpw = DIV_ROUND_UP(spi->cur_bpw, 8);
483 return DIV_ROUND_UP(packet, bpw);
487 * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
488 * @spi: pointer to the spi controller data structure
490 * Read from tx_buf depends on remaining bytes to avoid to read beyond
493 static void stm32f4_spi_write_tx(struct stm32_spi *spi)
495 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
496 STM32F4_SPI_SR_TXE)) {
497 u32 offs = spi->cur_xferlen - spi->tx_len;
499 if (spi->cur_bpw == 16) {
500 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
502 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR);
503 spi->tx_len -= sizeof(u16);
505 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
507 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR);
508 spi->tx_len -= sizeof(u8);
512 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
516 * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
517 * @spi: pointer to the spi controller data structure
519 * Read from tx_buf depends on remaining bytes to avoid to read beyond
522 static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
524 while ((spi->tx_len > 0) &&
525 (readl_relaxed(spi->base + STM32H7_SPI_SR) &
526 STM32H7_SPI_SR_TXP)) {
527 u32 offs = spi->cur_xferlen - spi->tx_len;
529 if (spi->tx_len >= sizeof(u32)) {
530 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
532 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
533 spi->tx_len -= sizeof(u32);
534 } else if (spi->tx_len >= sizeof(u16)) {
535 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
537 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
538 spi->tx_len -= sizeof(u16);
540 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
542 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
543 spi->tx_len -= sizeof(u8);
547 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
551 * stm32f4_spi_read_rx - Read bytes from Receive Data Register
552 * @spi: pointer to the spi controller data structure
554 * Write in rx_buf depends on remaining bytes to avoid to write beyond
557 static void stm32f4_spi_read_rx(struct stm32_spi *spi)
559 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
560 STM32F4_SPI_SR_RXNE)) {
561 u32 offs = spi->cur_xferlen - spi->rx_len;
563 if (spi->cur_bpw == 16) {
564 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
566 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR);
567 spi->rx_len -= sizeof(u16);
569 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
571 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR);
572 spi->rx_len -= sizeof(u8);
576 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
580 * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
581 * @spi: pointer to the spi controller data structure
582 * @flush: boolean indicating that FIFO should be flushed
584 * Write in rx_buf depends on remaining bytes to avoid to write beyond
587 static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
589 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
590 u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
591 STM32H7_SPI_SR_RXPLVL_SHIFT;
593 while ((spi->rx_len > 0) &&
594 ((sr & STM32H7_SPI_SR_RXP) ||
595 (flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
596 u32 offs = spi->cur_xferlen - spi->rx_len;
598 if ((spi->rx_len >= sizeof(u32)) ||
599 (flush && (sr & STM32H7_SPI_SR_RXWNE))) {
600 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
602 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
603 spi->rx_len -= sizeof(u32);
604 } else if ((spi->rx_len >= sizeof(u16)) ||
605 (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) {
606 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
608 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
609 spi->rx_len -= sizeof(u16);
611 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
613 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
614 spi->rx_len -= sizeof(u8);
617 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
618 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
619 STM32H7_SPI_SR_RXPLVL_SHIFT;
622 dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
623 flush ? "(flush)" : "", spi->rx_len);
627 * stm32_spi_enable - Enable SPI controller
628 * @spi: pointer to the spi controller data structure
630 static void stm32_spi_enable(struct stm32_spi *spi)
632 dev_dbg(spi->dev, "enable controller\n");
634 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg,
635 spi->cfg->regs->en.mask);
639 * stm32f4_spi_disable - Disable SPI controller
640 * @spi: pointer to the spi controller data structure
642 static void stm32f4_spi_disable(struct stm32_spi *spi)
647 dev_dbg(spi->dev, "disable controller\n");
649 spin_lock_irqsave(&spi->lock, flags);
651 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) &
652 STM32F4_SPI_CR1_SPE)) {
653 spin_unlock_irqrestore(&spi->lock, flags);
657 /* Disable interrupts */
658 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE |
659 STM32F4_SPI_CR2_RXNEIE |
660 STM32F4_SPI_CR2_ERRIE);
662 /* Wait until BSY = 0 */
663 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR,
664 sr, !(sr & STM32F4_SPI_SR_BSY),
666 dev_warn(spi->dev, "disabling condition timeout\n");
669 if (spi->cur_usedma && spi->dma_tx)
670 dmaengine_terminate_all(spi->dma_tx);
671 if (spi->cur_usedma && spi->dma_rx)
672 dmaengine_terminate_all(spi->dma_rx);
674 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
676 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN |
677 STM32F4_SPI_CR2_RXDMAEN);
679 /* Sequence to clear OVR flag */
680 readl_relaxed(spi->base + STM32F4_SPI_DR);
681 readl_relaxed(spi->base + STM32F4_SPI_SR);
683 spin_unlock_irqrestore(&spi->lock, flags);
687 * stm32h7_spi_disable - Disable SPI controller
688 * @spi: pointer to the spi controller data structure
690 * RX-Fifo is flushed when SPI controller is disabled. To prevent any data
691 * loss, use stm32h7_spi_read_rxfifo(flush) to read the remaining bytes in
693 * Normally, if TSIZE has been configured, we should relax the hardware at the
694 * reception of the EOT interrupt. But in case of error, EOT will not be
695 * raised. So the subsystem unprepare_message call allows us to properly
696 * complete the transfer from an hardware point of view.
698 static void stm32h7_spi_disable(struct stm32_spi *spi)
703 dev_dbg(spi->dev, "disable controller\n");
705 spin_lock_irqsave(&spi->lock, flags);
707 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
709 if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
710 spin_unlock_irqrestore(&spi->lock, flags);
714 /* Wait on EOT or suspend the flow */
715 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR,
716 sr, !(sr & STM32H7_SPI_SR_EOT),
718 if (cr1 & STM32H7_SPI_CR1_CSTART) {
719 writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP,
720 spi->base + STM32H7_SPI_CR1);
721 if (readl_relaxed_poll_timeout_atomic(
722 spi->base + STM32H7_SPI_SR,
723 sr, !(sr & STM32H7_SPI_SR_SUSP),
726 "Suspend request timeout\n");
730 if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0))
731 stm32h7_spi_read_rxfifo(spi, true);
733 if (spi->cur_usedma && spi->dma_tx)
734 dmaengine_terminate_all(spi->dma_tx);
735 if (spi->cur_usedma && spi->dma_rx)
736 dmaengine_terminate_all(spi->dma_rx);
738 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
740 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
741 STM32H7_SPI_CFG1_RXDMAEN);
743 /* Disable interrupts and clear status flags */
744 writel_relaxed(0, spi->base + STM32H7_SPI_IER);
745 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
747 spin_unlock_irqrestore(&spi->lock, flags);
751 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
752 * @master: controller master interface
753 * @spi_dev: pointer to the spi device
754 * @transfer: pointer to spi transfer
756 * If driver has fifo and the current transfer size is greater than fifo size,
757 * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes.
759 static bool stm32_spi_can_dma(struct spi_master *master,
760 struct spi_device *spi_dev,
761 struct spi_transfer *transfer)
763 unsigned int dma_size;
764 struct stm32_spi *spi = spi_master_get_devdata(master);
766 if (spi->cfg->has_fifo)
767 dma_size = spi->fifo_size;
769 dma_size = SPI_DMA_MIN_BYTES;
771 dev_dbg(spi->dev, "%s: %s\n", __func__,
772 (transfer->len > dma_size) ? "true" : "false");
774 return (transfer->len > dma_size);
778 * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
779 * @irq: interrupt line
780 * @dev_id: SPI controller master interface
782 static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
784 struct spi_master *master = dev_id;
785 struct stm32_spi *spi = spi_master_get_devdata(master);
789 spin_lock(&spi->lock);
791 sr = readl_relaxed(spi->base + STM32F4_SPI_SR);
793 * BSY flag is not handled in interrupt but it is normal behavior when
796 sr &= ~STM32F4_SPI_SR_BSY;
798 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX ||
799 spi->cur_comm == SPI_3WIRE_TX)) {
800 /* OVR flag shouldn't be handled for TX only mode */
801 sr &= ~STM32F4_SPI_SR_OVR | STM32F4_SPI_SR_RXNE;
802 mask |= STM32F4_SPI_SR_TXE;
805 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX ||
806 spi->cur_comm == SPI_SIMPLEX_RX ||
807 spi->cur_comm == SPI_3WIRE_RX)) {
808 /* TXE flag is set and is handled when RXNE flag occurs */
809 sr &= ~STM32F4_SPI_SR_TXE;
810 mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR;
814 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
815 spin_unlock(&spi->lock);
819 if (sr & STM32F4_SPI_SR_OVR) {
820 dev_warn(spi->dev, "Overrun: received value discarded\n");
822 /* Sequence to clear OVR flag */
823 readl_relaxed(spi->base + STM32F4_SPI_DR);
824 readl_relaxed(spi->base + STM32F4_SPI_SR);
827 * If overrun is detected, it means that something went wrong,
828 * so stop the current transfer. Transfer can wait for next
829 * RXNE but DR is already read and end never happens.
835 if (sr & STM32F4_SPI_SR_TXE) {
837 stm32f4_spi_write_tx(spi);
838 if (spi->tx_len == 0)
842 if (sr & STM32F4_SPI_SR_RXNE) {
843 stm32f4_spi_read_rx(spi);
844 if (spi->rx_len == 0)
846 else if (spi->tx_buf)/* Load data for discontinuous mode */
847 stm32f4_spi_write_tx(spi);
852 /* Immediately disable interrupts to do not generate new one */
853 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2,
854 STM32F4_SPI_CR2_TXEIE |
855 STM32F4_SPI_CR2_RXNEIE |
856 STM32F4_SPI_CR2_ERRIE);
857 spin_unlock(&spi->lock);
858 return IRQ_WAKE_THREAD;
861 spin_unlock(&spi->lock);
866 * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
867 * @irq: interrupt line
868 * @dev_id: SPI controller master interface
870 static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id)
872 struct spi_master *master = dev_id;
873 struct stm32_spi *spi = spi_master_get_devdata(master);
875 spi_finalize_current_transfer(master);
876 stm32f4_spi_disable(spi);
882 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
883 * @irq: interrupt line
884 * @dev_id: SPI controller master interface
886 static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
888 struct spi_master *master = dev_id;
889 struct stm32_spi *spi = spi_master_get_devdata(master);
894 spin_lock_irqsave(&spi->lock, flags);
896 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
897 ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
900 /* EOTIE is triggered on EOT, SUSP and TXC events. */
901 mask |= STM32H7_SPI_SR_SUSP;
903 * When TXTF is set, DXPIE and TXPIE are cleared. So in case of
904 * Full-Duplex, need to poll RXP event to know if there are remaining
905 * data, before disabling SPI.
907 if (spi->rx_buf && !spi->cur_usedma)
908 mask |= STM32H7_SPI_SR_RXP;
911 dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
913 spin_unlock_irqrestore(&spi->lock, flags);
917 if (sr & STM32H7_SPI_SR_SUSP) {
918 static DEFINE_RATELIMIT_STATE(rs,
919 DEFAULT_RATELIMIT_INTERVAL * 10,
921 if (__ratelimit(&rs))
922 dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
923 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
924 stm32h7_spi_read_rxfifo(spi, false);
926 * If communication is suspended while using DMA, it means
927 * that something went wrong, so stop the current transfer
933 if (sr & STM32H7_SPI_SR_MODF) {
934 dev_warn(spi->dev, "Mode fault: transfer aborted\n");
938 if (sr & STM32H7_SPI_SR_OVR) {
939 dev_warn(spi->dev, "Overrun: received value discarded\n");
940 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
941 stm32h7_spi_read_rxfifo(spi, false);
943 * If overrun is detected while using DMA, it means that
944 * something went wrong, so stop the current transfer
950 if (sr & STM32H7_SPI_SR_EOT) {
951 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
952 stm32h7_spi_read_rxfifo(spi, true);
956 if (sr & STM32H7_SPI_SR_TXP)
957 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
958 stm32h7_spi_write_txfifo(spi);
960 if (sr & STM32H7_SPI_SR_RXP)
961 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
962 stm32h7_spi_read_rxfifo(spi, false);
964 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR);
966 spin_unlock_irqrestore(&spi->lock, flags);
969 stm32h7_spi_disable(spi);
970 spi_finalize_current_transfer(master);
977 * stm32_spi_prepare_msg - set up the controller to transfer a single message
978 * @master: controller master interface
979 * @msg: pointer to spi message
981 static int stm32_spi_prepare_msg(struct spi_master *master,
982 struct spi_message *msg)
984 struct stm32_spi *spi = spi_master_get_devdata(master);
985 struct spi_device *spi_dev = msg->spi;
986 struct device_node *np = spi_dev->dev.of_node;
988 u32 clrb = 0, setb = 0;
990 /* SPI slave device may need time between data frames */
992 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
993 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
995 if (spi_dev->mode & SPI_CPOL)
996 setb |= spi->cfg->regs->cpol.mask;
998 clrb |= spi->cfg->regs->cpol.mask;
1000 if (spi_dev->mode & SPI_CPHA)
1001 setb |= spi->cfg->regs->cpha.mask;
1003 clrb |= spi->cfg->regs->cpha.mask;
1005 if (spi_dev->mode & SPI_LSB_FIRST)
1006 setb |= spi->cfg->regs->lsb_first.mask;
1008 clrb |= spi->cfg->regs->lsb_first.mask;
1010 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
1011 !!(spi_dev->mode & SPI_CPOL),
1012 !!(spi_dev->mode & SPI_CPHA),
1013 !!(spi_dev->mode & SPI_LSB_FIRST),
1014 !!(spi_dev->mode & SPI_CS_HIGH));
1016 spin_lock_irqsave(&spi->lock, flags);
1018 /* CPOL, CPHA and LSB FIRST bits have common register */
1021 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) &
1023 spi->base + spi->cfg->regs->cpol.reg);
1025 spin_unlock_irqrestore(&spi->lock, flags);
1031 * stm32f4_spi_dma_tx_cb - dma callback
1032 * @data: pointer to the spi controller data structure
1034 * DMA callback is called when the transfer is complete for DMA TX channel.
1036 static void stm32f4_spi_dma_tx_cb(void *data)
1038 struct stm32_spi *spi = data;
1040 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1041 spi_finalize_current_transfer(spi->master);
1042 stm32f4_spi_disable(spi);
1047 * stm32f4_spi_dma_rx_cb - dma callback
1048 * @data: pointer to the spi controller data structure
1050 * DMA callback is called when the transfer is complete for DMA RX channel.
1052 static void stm32f4_spi_dma_rx_cb(void *data)
1054 struct stm32_spi *spi = data;
1056 spi_finalize_current_transfer(spi->master);
1057 stm32f4_spi_disable(spi);
1061 * stm32h7_spi_dma_cb - dma callback
1062 * @data: pointer to the spi controller data structure
1064 * DMA callback is called when the transfer is complete or when an error
1065 * occurs. If the transfer is complete, EOT flag is raised.
1067 static void stm32h7_spi_dma_cb(void *data)
1069 struct stm32_spi *spi = data;
1070 unsigned long flags;
1073 spin_lock_irqsave(&spi->lock, flags);
1075 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
1077 spin_unlock_irqrestore(&spi->lock, flags);
1079 if (!(sr & STM32H7_SPI_SR_EOT))
1080 dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr);
1082 /* Now wait for EOT, or SUSP or OVR in case of error */
1086 * stm32_spi_dma_config - configure dma slave channel depending on current
1087 * transfer bits_per_word.
1088 * @spi: pointer to the spi controller data structure
1089 * @dma_conf: pointer to the dma_slave_config structure
1090 * @dir: direction of the dma transfer
1092 static void stm32_spi_dma_config(struct stm32_spi *spi,
1093 struct dma_slave_config *dma_conf,
1094 enum dma_transfer_direction dir)
1096 enum dma_slave_buswidth buswidth;
1099 if (spi->cur_bpw <= 8)
1100 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1101 else if (spi->cur_bpw <= 16)
1102 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1104 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1106 if (spi->cfg->has_fifo) {
1107 /* Valid for DMA Half or Full Fifo threshold */
1108 if (spi->cur_fthlv == 2)
1111 maxburst = spi->cur_fthlv;
1116 memset(dma_conf, 0, sizeof(struct dma_slave_config));
1117 dma_conf->direction = dir;
1118 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
1119 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg;
1120 dma_conf->src_addr_width = buswidth;
1121 dma_conf->src_maxburst = maxburst;
1123 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
1124 buswidth, maxburst);
1125 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
1126 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg;
1127 dma_conf->dst_addr_width = buswidth;
1128 dma_conf->dst_maxburst = maxburst;
1130 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
1131 buswidth, maxburst);
1136 * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using
1138 * @spi: pointer to the spi controller data structure
1140 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1143 static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi)
1145 unsigned long flags;
1148 /* Enable the interrupts relative to the current communication mode */
1149 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1150 cr2 |= STM32F4_SPI_CR2_TXEIE;
1151 } else if (spi->cur_comm == SPI_FULL_DUPLEX ||
1152 spi->cur_comm == SPI_SIMPLEX_RX ||
1153 spi->cur_comm == SPI_3WIRE_RX) {
1154 /* In transmit-only mode, the OVR flag is set in the SR register
1155 * since the received data are never read. Therefore set OVR
1156 * interrupt only when rx buffer is available.
1158 cr2 |= STM32F4_SPI_CR2_RXNEIE | STM32F4_SPI_CR2_ERRIE;
1163 spin_lock_irqsave(&spi->lock, flags);
1165 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2);
1167 stm32_spi_enable(spi);
1169 /* starting data transfer when buffer is loaded */
1171 stm32f4_spi_write_tx(spi);
1173 spin_unlock_irqrestore(&spi->lock, flags);
1179 * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
1181 * @spi: pointer to the spi controller data structure
1183 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1186 static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
1188 unsigned long flags;
1191 /* Enable the interrupts relative to the current communication mode */
1192 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
1193 ier |= STM32H7_SPI_IER_DXPIE;
1194 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
1195 ier |= STM32H7_SPI_IER_TXPIE;
1196 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
1197 ier |= STM32H7_SPI_IER_RXPIE;
1199 /* Enable the interrupts relative to the end of transfer */
1200 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
1201 STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
1203 spin_lock_irqsave(&spi->lock, flags);
1205 stm32_spi_enable(spi);
1207 /* Be sure to have data in fifo before starting data transfer */
1209 stm32h7_spi_write_txfifo(spi);
1211 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1213 writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
1215 spin_unlock_irqrestore(&spi->lock, flags);
1221 * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
1222 * transfer using DMA
1223 * @spi: pointer to the spi controller data structure
1225 static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi)
1227 /* In DMA mode end of transfer is handled by DMA TX or RX callback. */
1228 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX ||
1229 spi->cur_comm == SPI_FULL_DUPLEX) {
1231 * In transmit-only mode, the OVR flag is set in the SR register
1232 * since the received data are never read. Therefore set OVR
1233 * interrupt only when rx buffer is available.
1235 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE);
1238 stm32_spi_enable(spi);
1242 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1243 * transfer using DMA
1244 * @spi: pointer to the spi controller data structure
1246 static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
1248 /* Enable the interrupts relative to the end of transfer */
1249 stm32_spi_set_bits(spi, STM32H7_SPI_IER, STM32H7_SPI_IER_EOTIE |
1250 STM32H7_SPI_IER_TXTFIE |
1251 STM32H7_SPI_IER_OVRIE |
1252 STM32H7_SPI_IER_MODFIE);
1254 stm32_spi_enable(spi);
1256 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1260 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
1261 * @spi: pointer to the spi controller data structure
1262 * @xfer: pointer to the spi_transfer structure
1264 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1267 static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
1268 struct spi_transfer *xfer)
1270 struct dma_slave_config tx_dma_conf, rx_dma_conf;
1271 struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
1272 unsigned long flags;
1274 spin_lock_irqsave(&spi->lock, flags);
1277 if (spi->rx_buf && spi->dma_rx) {
1278 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
1279 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
1281 /* Enable Rx DMA request */
1282 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1283 spi->cfg->regs->dma_rx_en.mask);
1285 rx_dma_desc = dmaengine_prep_slave_sg(
1286 spi->dma_rx, xfer->rx_sg.sgl,
1288 rx_dma_conf.direction,
1289 DMA_PREP_INTERRUPT);
1293 if (spi->tx_buf && spi->dma_tx) {
1294 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
1295 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
1297 tx_dma_desc = dmaengine_prep_slave_sg(
1298 spi->dma_tx, xfer->tx_sg.sgl,
1300 tx_dma_conf.direction,
1301 DMA_PREP_INTERRUPT);
1304 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) ||
1305 (spi->rx_buf && spi->dma_rx && !rx_dma_desc))
1306 goto dma_desc_error;
1308 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc))
1309 goto dma_desc_error;
1312 rx_dma_desc->callback = spi->cfg->dma_rx_cb;
1313 rx_dma_desc->callback_param = spi;
1315 if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
1316 dev_err(spi->dev, "Rx DMA submit failed\n");
1317 goto dma_desc_error;
1319 /* Enable Rx DMA channel */
1320 dma_async_issue_pending(spi->dma_rx);
1324 if (spi->cur_comm == SPI_SIMPLEX_TX ||
1325 spi->cur_comm == SPI_3WIRE_TX) {
1326 tx_dma_desc->callback = spi->cfg->dma_tx_cb;
1327 tx_dma_desc->callback_param = spi;
1330 if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
1331 dev_err(spi->dev, "Tx DMA submit failed\n");
1332 goto dma_submit_error;
1334 /* Enable Tx DMA channel */
1335 dma_async_issue_pending(spi->dma_tx);
1337 /* Enable Tx DMA request */
1338 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg,
1339 spi->cfg->regs->dma_tx_en.mask);
1342 spi->cfg->transfer_one_dma_start(spi);
1344 spin_unlock_irqrestore(&spi->lock, flags);
1350 dmaengine_terminate_all(spi->dma_rx);
1353 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1354 spi->cfg->regs->dma_rx_en.mask);
1356 spin_unlock_irqrestore(&spi->lock, flags);
1358 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
1360 spi->cur_usedma = false;
1361 return spi->cfg->transfer_one_irq(spi);
1365 * stm32f4_spi_set_bpw - Configure bits per word
1366 * @spi: pointer to the spi controller data structure
1368 static void stm32f4_spi_set_bpw(struct stm32_spi *spi)
1370 if (spi->cur_bpw == 16)
1371 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1373 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1377 * stm32h7_spi_set_bpw - configure bits per word
1378 * @spi: pointer to the spi controller data structure
1380 static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
1383 u32 cfg1_clrb = 0, cfg1_setb = 0;
1385 bpw = spi->cur_bpw - 1;
1387 cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
1388 cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
1389 STM32H7_SPI_CFG1_DSIZE;
1391 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
1392 fthlv = spi->cur_fthlv - 1;
1394 cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
1395 cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
1396 STM32H7_SPI_CFG1_FTHLV;
1399 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
1400 ~cfg1_clrb) | cfg1_setb,
1401 spi->base + STM32H7_SPI_CFG1);
1405 * stm32_spi_set_mbr - Configure baud rate divisor in master mode
1406 * @spi: pointer to the spi controller data structure
1407 * @mbrdiv: baud rate divisor value
1409 static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
1411 u32 clrb = 0, setb = 0;
1413 clrb |= spi->cfg->regs->br.mask;
1414 setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) &
1415 spi->cfg->regs->br.mask;
1417 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
1419 spi->base + spi->cfg->regs->br.reg);
1423 * stm32_spi_communication_type - return transfer communication type
1424 * @spi_dev: pointer to the spi device
1425 * @transfer: pointer to spi transfer
1427 static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev,
1428 struct spi_transfer *transfer)
1430 unsigned int type = SPI_FULL_DUPLEX;
1432 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
1434 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
1435 * is forbidden and unvalidated by SPI subsystem so depending
1436 * on the valid buffer, we can determine the direction of the
1439 if (!transfer->tx_buf)
1440 type = SPI_3WIRE_RX;
1442 type = SPI_3WIRE_TX;
1444 if (!transfer->tx_buf)
1445 type = SPI_SIMPLEX_RX;
1446 else if (!transfer->rx_buf)
1447 type = SPI_SIMPLEX_TX;
1454 * stm32f4_spi_set_mode - configure communication mode
1455 * @spi: pointer to the spi controller data structure
1456 * @comm_type: type of communication to configure
1458 static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1460 if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) {
1461 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1462 STM32F4_SPI_CR1_BIDIMODE |
1463 STM32F4_SPI_CR1_BIDIOE);
1464 } else if (comm_type == SPI_FULL_DUPLEX ||
1465 comm_type == SPI_SIMPLEX_RX) {
1466 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1467 STM32F4_SPI_CR1_BIDIMODE |
1468 STM32F4_SPI_CR1_BIDIOE);
1469 } else if (comm_type == SPI_3WIRE_RX) {
1470 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1471 STM32F4_SPI_CR1_BIDIMODE);
1472 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1473 STM32F4_SPI_CR1_BIDIOE);
1482 * stm32h7_spi_set_mode - configure communication mode
1483 * @spi: pointer to the spi controller data structure
1484 * @comm_type: type of communication to configure
1486 static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1489 u32 cfg2_clrb = 0, cfg2_setb = 0;
1491 if (comm_type == SPI_3WIRE_RX) {
1492 mode = STM32H7_SPI_HALF_DUPLEX;
1493 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1494 } else if (comm_type == SPI_3WIRE_TX) {
1495 mode = STM32H7_SPI_HALF_DUPLEX;
1496 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1497 } else if (comm_type == SPI_SIMPLEX_RX) {
1498 mode = STM32H7_SPI_SIMPLEX_RX;
1499 } else if (comm_type == SPI_SIMPLEX_TX) {
1500 mode = STM32H7_SPI_SIMPLEX_TX;
1502 mode = STM32H7_SPI_FULL_DUPLEX;
1505 cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
1506 cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) &
1507 STM32H7_SPI_CFG2_COMM;
1510 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1511 ~cfg2_clrb) | cfg2_setb,
1512 spi->base + STM32H7_SPI_CFG2);
1518 * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
1519 * consecutive data frames in master mode
1520 * @spi: pointer to the spi controller data structure
1521 * @len: transfer len
1523 static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
1525 u32 cfg2_clrb = 0, cfg2_setb = 0;
1527 cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
1528 if ((len > 1) && (spi->cur_midi > 0)) {
1529 u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
1530 u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
1531 (u32)STM32H7_SPI_CFG2_MIDI >>
1532 STM32H7_SPI_CFG2_MIDI_SHIFT);
1534 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
1535 sck_period_ns, midi, midi * sck_period_ns);
1536 cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) &
1537 STM32H7_SPI_CFG2_MIDI;
1540 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1541 ~cfg2_clrb) | cfg2_setb,
1542 spi->base + STM32H7_SPI_CFG2);
1546 * stm32h7_spi_number_of_data - configure number of data at current transfer
1547 * @spi: pointer to the spi controller data structure
1548 * @nb_words: transfer length (in words)
1550 static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
1552 u32 cr2_clrb = 0, cr2_setb = 0;
1554 if (nb_words <= (STM32H7_SPI_CR2_TSIZE >>
1555 STM32H7_SPI_CR2_TSIZE_SHIFT)) {
1556 cr2_clrb |= STM32H7_SPI_CR2_TSIZE;
1557 cr2_setb = nb_words << STM32H7_SPI_CR2_TSIZE_SHIFT;
1558 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) &
1559 ~cr2_clrb) | cr2_setb,
1560 spi->base + STM32H7_SPI_CR2);
1569 * stm32_spi_transfer_one_setup - common setup to transfer a single
1570 * spi_transfer either using DMA or
1572 * @spi: pointer to the spi controller data structure
1573 * @spi_dev: pointer to the spi device
1574 * @transfer: pointer to spi transfer
1576 static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
1577 struct spi_device *spi_dev,
1578 struct spi_transfer *transfer)
1580 unsigned long flags;
1581 unsigned int comm_type;
1582 int nb_words, ret = 0;
1585 spin_lock_irqsave(&spi->lock, flags);
1587 spi->cur_xferlen = transfer->len;
1589 spi->cur_bpw = transfer->bits_per_word;
1590 spi->cfg->set_bpw(spi);
1592 /* Update spi->cur_speed with real clock speed */
1593 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
1594 spi->cfg->baud_rate_div_min,
1595 spi->cfg->baud_rate_div_max);
1601 transfer->speed_hz = spi->cur_speed;
1602 stm32_spi_set_mbr(spi, mbr);
1604 comm_type = stm32_spi_communication_type(spi_dev, transfer);
1605 ret = spi->cfg->set_mode(spi, comm_type);
1609 spi->cur_comm = comm_type;
1611 if (spi->cfg->set_data_idleness)
1612 spi->cfg->set_data_idleness(spi, transfer->len);
1614 if (spi->cur_bpw <= 8)
1615 nb_words = transfer->len;
1616 else if (spi->cur_bpw <= 16)
1617 nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
1619 nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
1621 if (spi->cfg->set_number_of_data) {
1622 ret = spi->cfg->set_number_of_data(spi, nb_words);
1627 dev_dbg(spi->dev, "transfer communication mode set to %d\n",
1630 "data frame of %d-bit, data packet of %d data frames\n",
1631 spi->cur_bpw, spi->cur_fthlv);
1632 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
1633 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
1634 spi->cur_xferlen, nb_words);
1635 dev_dbg(spi->dev, "dma %s\n",
1636 (spi->cur_usedma) ? "enabled" : "disabled");
1639 spin_unlock_irqrestore(&spi->lock, flags);
1645 * stm32_spi_transfer_one - transfer a single spi_transfer
1646 * @master: controller master interface
1647 * @spi_dev: pointer to the spi device
1648 * @transfer: pointer to spi transfer
1650 * It must return 0 if the transfer is finished or 1 if the transfer is still
1653 static int stm32_spi_transfer_one(struct spi_master *master,
1654 struct spi_device *spi_dev,
1655 struct spi_transfer *transfer)
1657 struct stm32_spi *spi = spi_master_get_devdata(master);
1660 /* Don't do anything on 0 bytes transfers */
1661 if (transfer->len == 0)
1664 spi->tx_buf = transfer->tx_buf;
1665 spi->rx_buf = transfer->rx_buf;
1666 spi->tx_len = spi->tx_buf ? transfer->len : 0;
1667 spi->rx_len = spi->rx_buf ? transfer->len : 0;
1669 spi->cur_usedma = (master->can_dma &&
1670 master->can_dma(master, spi_dev, transfer));
1672 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
1674 dev_err(spi->dev, "SPI transfer setup failed\n");
1678 if (spi->cur_usedma)
1679 return stm32_spi_transfer_one_dma(spi, transfer);
1681 return spi->cfg->transfer_one_irq(spi);
1685 * stm32_spi_unprepare_msg - relax the hardware
1686 * @master: controller master interface
1687 * @msg: pointer to the spi message
1689 static int stm32_spi_unprepare_msg(struct spi_master *master,
1690 struct spi_message *msg)
1692 struct stm32_spi *spi = spi_master_get_devdata(master);
1694 spi->cfg->disable(spi);
1700 * stm32f4_spi_config - Configure SPI controller as SPI master
1701 * @spi: pointer to the spi controller data structure
1703 static int stm32f4_spi_config(struct stm32_spi *spi)
1705 unsigned long flags;
1707 spin_lock_irqsave(&spi->lock, flags);
1709 /* Ensure I2SMOD bit is kept cleared */
1710 stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR,
1711 STM32F4_SPI_I2SCFGR_I2SMOD);
1714 * - SS input value high
1715 * - transmitter half duplex direction
1716 * - Set the master mode (default Motorola mode)
1717 * - Consider 1 master/n slaves configuration and
1718 * SS input value is determined by the SSI bit
1720 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI |
1721 STM32F4_SPI_CR1_BIDIOE |
1722 STM32F4_SPI_CR1_MSTR |
1723 STM32F4_SPI_CR1_SSM);
1725 spin_unlock_irqrestore(&spi->lock, flags);
1731 * stm32h7_spi_config - Configure SPI controller as SPI master
1732 * @spi: pointer to the spi controller data structure
1734 static int stm32h7_spi_config(struct stm32_spi *spi)
1736 unsigned long flags;
1738 spin_lock_irqsave(&spi->lock, flags);
1740 /* Ensure I2SMOD bit is kept cleared */
1741 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
1742 STM32H7_SPI_I2SCFGR_I2SMOD);
1745 * - SS input value high
1746 * - transmitter half duplex direction
1747 * - automatic communication suspend when RX-Fifo is full
1749 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI |
1750 STM32H7_SPI_CR1_HDDIR |
1751 STM32H7_SPI_CR1_MASRX);
1754 * - Set the master mode (default Motorola mode)
1755 * - Consider 1 master/n slaves configuration and
1756 * SS input value is determined by the SSI bit
1757 * - keep control of all associated GPIOs
1759 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER |
1760 STM32H7_SPI_CFG2_SSM |
1761 STM32H7_SPI_CFG2_AFCNTR);
1763 spin_unlock_irqrestore(&spi->lock, flags);
1768 static const struct stm32_spi_cfg stm32f4_spi_cfg = {
1769 .regs = &stm32f4_spi_regspec,
1770 .get_bpw_mask = stm32f4_spi_get_bpw_mask,
1771 .disable = stm32f4_spi_disable,
1772 .config = stm32f4_spi_config,
1773 .set_bpw = stm32f4_spi_set_bpw,
1774 .set_mode = stm32f4_spi_set_mode,
1775 .transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start,
1776 .dma_tx_cb = stm32f4_spi_dma_tx_cb,
1777 .dma_rx_cb = stm32f4_spi_dma_rx_cb,
1778 .transfer_one_irq = stm32f4_spi_transfer_one_irq,
1779 .irq_handler_event = stm32f4_spi_irq_event,
1780 .irq_handler_thread = stm32f4_spi_irq_thread,
1781 .baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN,
1782 .baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX,
1786 static const struct stm32_spi_cfg stm32h7_spi_cfg = {
1787 .regs = &stm32h7_spi_regspec,
1788 .get_fifo_size = stm32h7_spi_get_fifo_size,
1789 .get_bpw_mask = stm32h7_spi_get_bpw_mask,
1790 .disable = stm32h7_spi_disable,
1791 .config = stm32h7_spi_config,
1792 .set_bpw = stm32h7_spi_set_bpw,
1793 .set_mode = stm32h7_spi_set_mode,
1794 .set_data_idleness = stm32h7_spi_data_idleness,
1795 .set_number_of_data = stm32h7_spi_number_of_data,
1796 .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
1797 .dma_rx_cb = stm32h7_spi_dma_cb,
1798 .dma_tx_cb = stm32h7_spi_dma_cb,
1799 .transfer_one_irq = stm32h7_spi_transfer_one_irq,
1800 .irq_handler_thread = stm32h7_spi_irq_thread,
1801 .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
1802 .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
1806 static const struct of_device_id stm32_spi_of_match[] = {
1807 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
1808 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
1811 MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
1813 static int stm32_spi_probe(struct platform_device *pdev)
1815 struct spi_master *master;
1816 struct stm32_spi *spi;
1817 struct resource *res;
1820 master = spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
1822 dev_err(&pdev->dev, "spi master allocation failed\n");
1825 platform_set_drvdata(pdev, master);
1827 spi = spi_master_get_devdata(master);
1828 spi->dev = &pdev->dev;
1829 spi->master = master;
1830 spin_lock_init(&spi->lock);
1832 spi->cfg = (const struct stm32_spi_cfg *)
1833 of_match_device(pdev->dev.driver->of_match_table,
1836 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1837 spi->base = devm_ioremap_resource(&pdev->dev, res);
1838 if (IS_ERR(spi->base)) {
1839 ret = PTR_ERR(spi->base);
1840 goto err_master_put;
1843 spi->phys_addr = (dma_addr_t)res->start;
1845 spi->irq = platform_get_irq(pdev, 0);
1846 if (spi->irq <= 0) {
1847 ret = dev_err_probe(&pdev->dev, spi->irq, "failed to get irq\n");
1848 goto err_master_put;
1850 ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
1851 spi->cfg->irq_handler_event,
1852 spi->cfg->irq_handler_thread,
1853 IRQF_ONESHOT, pdev->name, master);
1855 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
1857 goto err_master_put;
1860 spi->clk = devm_clk_get(&pdev->dev, NULL);
1861 if (IS_ERR(spi->clk)) {
1862 ret = PTR_ERR(spi->clk);
1863 dev_err(&pdev->dev, "clk get failed: %d\n", ret);
1864 goto err_master_put;
1867 ret = clk_prepare_enable(spi->clk);
1869 dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
1870 goto err_master_put;
1872 spi->clk_rate = clk_get_rate(spi->clk);
1873 if (!spi->clk_rate) {
1874 dev_err(&pdev->dev, "clk rate = 0\n");
1876 goto err_clk_disable;
1879 spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1880 if (!IS_ERR(spi->rst)) {
1881 reset_control_assert(spi->rst);
1883 reset_control_deassert(spi->rst);
1886 if (spi->cfg->has_fifo)
1887 spi->fifo_size = spi->cfg->get_fifo_size(spi);
1889 ret = spi->cfg->config(spi);
1891 dev_err(&pdev->dev, "controller configuration failed: %d\n",
1893 goto err_clk_disable;
1896 master->dev.of_node = pdev->dev.of_node;
1897 master->auto_runtime_pm = true;
1898 master->bus_num = pdev->id;
1899 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
1901 master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi);
1902 master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
1903 master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
1904 master->use_gpio_descriptors = true;
1905 master->prepare_message = stm32_spi_prepare_msg;
1906 master->transfer_one = stm32_spi_transfer_one;
1907 master->unprepare_message = stm32_spi_unprepare_msg;
1908 master->flags = SPI_MASTER_MUST_TX;
1910 spi->dma_tx = dma_request_chan(spi->dev, "tx");
1911 if (IS_ERR(spi->dma_tx)) {
1912 ret = PTR_ERR(spi->dma_tx);
1914 if (ret == -EPROBE_DEFER)
1915 goto err_clk_disable;
1917 dev_warn(&pdev->dev, "failed to request tx dma channel\n");
1919 master->dma_tx = spi->dma_tx;
1922 spi->dma_rx = dma_request_chan(spi->dev, "rx");
1923 if (IS_ERR(spi->dma_rx)) {
1924 ret = PTR_ERR(spi->dma_rx);
1926 if (ret == -EPROBE_DEFER)
1927 goto err_dma_release;
1929 dev_warn(&pdev->dev, "failed to request rx dma channel\n");
1931 master->dma_rx = spi->dma_rx;
1934 if (spi->dma_tx || spi->dma_rx)
1935 master->can_dma = stm32_spi_can_dma;
1937 pm_runtime_set_active(&pdev->dev);
1938 pm_runtime_enable(&pdev->dev);
1940 ret = devm_spi_register_master(&pdev->dev, master);
1942 dev_err(&pdev->dev, "spi master registration failed: %d\n",
1944 goto err_pm_disable;
1947 dev_info(&pdev->dev, "driver initialized\n");
1952 pm_runtime_disable(&pdev->dev);
1955 dma_release_channel(spi->dma_tx);
1957 dma_release_channel(spi->dma_rx);
1959 clk_disable_unprepare(spi->clk);
1961 spi_master_put(master);
1966 static int stm32_spi_remove(struct platform_device *pdev)
1968 struct spi_master *master = platform_get_drvdata(pdev);
1969 struct stm32_spi *spi = spi_master_get_devdata(master);
1971 spi->cfg->disable(spi);
1974 dma_release_channel(master->dma_tx);
1976 dma_release_channel(master->dma_rx);
1978 clk_disable_unprepare(spi->clk);
1980 pm_runtime_disable(&pdev->dev);
1982 pinctrl_pm_select_sleep_state(&pdev->dev);
1988 static int stm32_spi_runtime_suspend(struct device *dev)
1990 struct spi_master *master = dev_get_drvdata(dev);
1991 struct stm32_spi *spi = spi_master_get_devdata(master);
1993 clk_disable_unprepare(spi->clk);
1995 return pinctrl_pm_select_sleep_state(dev);
1998 static int stm32_spi_runtime_resume(struct device *dev)
2000 struct spi_master *master = dev_get_drvdata(dev);
2001 struct stm32_spi *spi = spi_master_get_devdata(master);
2004 ret = pinctrl_pm_select_default_state(dev);
2008 return clk_prepare_enable(spi->clk);
2012 #ifdef CONFIG_PM_SLEEP
2013 static int stm32_spi_suspend(struct device *dev)
2015 struct spi_master *master = dev_get_drvdata(dev);
2018 ret = spi_master_suspend(master);
2022 return pm_runtime_force_suspend(dev);
2025 static int stm32_spi_resume(struct device *dev)
2027 struct spi_master *master = dev_get_drvdata(dev);
2028 struct stm32_spi *spi = spi_master_get_devdata(master);
2031 ret = pm_runtime_force_resume(dev);
2035 ret = spi_master_resume(master);
2037 clk_disable_unprepare(spi->clk);
2041 ret = pm_runtime_get_sync(dev);
2043 pm_runtime_put_noidle(dev);
2044 dev_err(dev, "Unable to power device:%d\n", ret);
2048 spi->cfg->config(spi);
2050 pm_runtime_mark_last_busy(dev);
2051 pm_runtime_put_autosuspend(dev);
2057 static const struct dev_pm_ops stm32_spi_pm_ops = {
2058 SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
2059 SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend,
2060 stm32_spi_runtime_resume, NULL)
2063 static struct platform_driver stm32_spi_driver = {
2064 .probe = stm32_spi_probe,
2065 .remove = stm32_spi_remove,
2067 .name = DRIVER_NAME,
2068 .pm = &stm32_spi_pm_ops,
2069 .of_match_table = stm32_spi_of_match,
2073 module_platform_driver(stm32_spi_driver);
2075 MODULE_ALIAS("platform:" DRIVER_NAME);
2076 MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
2077 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
2078 MODULE_LICENSE("GPL v2");