1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018 SiFive, Inc.
4 * Copyright 2019 Bhargav Shah <bhargavshah1988@gmail.com>
6 * SiFive SPI controller driver (master mode only)
11 #include <dm/device_compat.h>
16 #include <linux/log2.h>
19 #define SIFIVE_SPI_MAX_CS 32
21 #define SIFIVE_SPI_DEFAULT_DEPTH 8
22 #define SIFIVE_SPI_DEFAULT_BITS 8
24 /* register offsets */
25 #define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */
26 #define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
27 #define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */
28 #define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */
29 #define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */
30 #define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */
31 #define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */
32 #define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */
33 #define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
34 #define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
35 #define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
36 #define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
37 #define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
38 #define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
39 #define SIFIVE_SPI_REG_IE 0x70 /* Interrupt Enable Register */
40 #define SIFIVE_SPI_REG_IP 0x74 /* Interrupt Pendings Register */
43 #define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU
46 #define SIFIVE_SPI_SCKMODE_PHA BIT(0)
47 #define SIFIVE_SPI_SCKMODE_POL BIT(1)
48 #define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \
49 SIFIVE_SPI_SCKMODE_POL)
52 #define SIFIVE_SPI_CSMODE_MODE_AUTO 0U
53 #define SIFIVE_SPI_CSMODE_MODE_HOLD 2U
54 #define SIFIVE_SPI_CSMODE_MODE_OFF 3U
57 #define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x))
58 #define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU
59 #define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16)
60 #define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
63 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x))
64 #define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU
65 #define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16)
66 #define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
69 #define SIFIVE_SPI_FMT_PROTO_SINGLE 0U
70 #define SIFIVE_SPI_FMT_PROTO_DUAL 1U
71 #define SIFIVE_SPI_FMT_PROTO_QUAD 2U
72 #define SIFIVE_SPI_FMT_PROTO_MASK 3U
73 #define SIFIVE_SPI_FMT_ENDIAN BIT(2)
74 #define SIFIVE_SPI_FMT_DIR BIT(3)
75 #define SIFIVE_SPI_FMT_LEN(x) ((u32)(x) << 16)
76 #define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16)
79 #define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU
80 #define SIFIVE_SPI_TXDATA_FULL BIT(31)
83 #define SIFIVE_SPI_RXDATA_DATA_MASK 0xffU
84 #define SIFIVE_SPI_RXDATA_EMPTY BIT(31)
87 #define SIFIVE_SPI_IP_TXWM BIT(0)
88 #define SIFIVE_SPI_IP_RXWM BIT(1)
91 #define SIFIVE_SPI_PROTO_QUAD 4 /* 4 lines I/O protocol transfer */
92 #define SIFIVE_SPI_PROTO_DUAL 2 /* 2 lines I/O protocol transfer */
93 #define SIFIVE_SPI_PROTO_SINGLE 1 /* 1 line I/O protocol transfer */
96 void *regs; /* base address of the registers */
99 u32 cs_inactive; /* Level of the CS pins when inactive*/
105 static void sifive_spi_prep_device(struct sifive_spi *spi,
106 struct dm_spi_slave_platdata *slave_plat)
108 /* Update the chip select polarity */
109 if (slave_plat->mode & SPI_CS_HIGH)
110 spi->cs_inactive &= ~BIT(slave_plat->cs);
112 spi->cs_inactive |= BIT(slave_plat->cs);
113 writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
115 /* Select the correct device */
116 writel(slave_plat->cs, spi->regs + SIFIVE_SPI_REG_CSID);
119 static int sifive_spi_set_cs(struct sifive_spi *spi,
120 struct dm_spi_slave_platdata *slave_plat)
122 u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD;
124 if (slave_plat->mode & SPI_CS_HIGH)
125 cs_mode = SIFIVE_SPI_CSMODE_MODE_AUTO;
127 writel(cs_mode, spi->regs + SIFIVE_SPI_REG_CSMODE);
132 static void sifive_spi_clear_cs(struct sifive_spi *spi)
134 writel(SIFIVE_SPI_CSMODE_MODE_AUTO, spi->regs + SIFIVE_SPI_REG_CSMODE);
137 static void sifive_spi_prep_transfer(struct sifive_spi *spi,
138 struct dm_spi_slave_platdata *slave_plat,
143 /* Modify the SPI protocol mode */
144 cr = readl(spi->regs + SIFIVE_SPI_REG_FMT);
146 /* Bits per word ? */
147 cr &= ~SIFIVE_SPI_FMT_LEN_MASK;
148 cr |= SIFIVE_SPI_FMT_LEN(spi->bits_per_word);
151 cr &= ~SIFIVE_SPI_FMT_ENDIAN;
152 if (slave_plat->mode & SPI_LSB_FIRST)
153 cr |= SIFIVE_SPI_FMT_ENDIAN;
155 /* Number of wires ? */
156 cr &= ~SIFIVE_SPI_FMT_PROTO_MASK;
157 switch (spi->fmt_proto) {
158 case SIFIVE_SPI_PROTO_QUAD:
159 cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
161 case SIFIVE_SPI_PROTO_DUAL:
162 cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
165 cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
169 /* SPI direction in/out ? */
170 cr &= ~SIFIVE_SPI_FMT_DIR;
172 cr |= SIFIVE_SPI_FMT_DIR;
174 writel(cr, spi->regs + SIFIVE_SPI_REG_FMT);
177 static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
182 data = readl(spi->regs + SIFIVE_SPI_REG_RXDATA);
183 } while (data & SIFIVE_SPI_RXDATA_EMPTY);
186 *rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
189 static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
192 u8 tx_data = (tx_ptr) ? *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK :
193 SIFIVE_SPI_TXDATA_DATA_MASK;
196 data = readl(spi->regs + SIFIVE_SPI_REG_TXDATA);
197 } while (data & SIFIVE_SPI_TXDATA_FULL);
199 writel(tx_data, spi->regs + SIFIVE_SPI_REG_TXDATA);
202 static int sifive_spi_wait(struct sifive_spi *spi, u32 bit)
204 return wait_for_bit_le32(spi->regs + SIFIVE_SPI_REG_IP,
205 bit, true, 100, false);
208 static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen,
209 const void *dout, void *din, unsigned long flags)
211 struct udevice *bus = dev->parent;
212 struct sifive_spi *spi = dev_get_priv(bus);
213 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
214 const u8 *tx_ptr = dout;
219 if (flags & SPI_XFER_BEGIN) {
220 sifive_spi_prep_device(spi, slave_plat);
222 ret = sifive_spi_set_cs(spi, slave_plat);
227 sifive_spi_prep_transfer(spi, slave_plat, rx_ptr);
229 remaining_len = bitlen / 8;
231 while (remaining_len) {
232 unsigned int n_words = min(remaining_len, spi->fifo_depth);
233 unsigned int tx_words, rx_words;
235 /* Enqueue n_words for transmission */
236 for (tx_words = 0; tx_words < n_words; tx_words++) {
238 sifive_spi_tx(spi, NULL);
240 sifive_spi_tx(spi, tx_ptr++);
244 /* Wait for transmission + reception to complete */
245 writel(n_words - 1, spi->regs + SIFIVE_SPI_REG_RXMARK);
246 ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_RXWM);
250 /* Read out all the data from the RX FIFO */
251 for (rx_words = 0; rx_words < n_words; rx_words++)
252 sifive_spi_rx(spi, rx_ptr++);
254 /* Wait for transmission to complete */
255 ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_TXWM);
260 remaining_len -= n_words;
263 if (flags & SPI_XFER_END)
264 sifive_spi_clear_cs(spi);
269 static int sifive_spi_exec_op(struct spi_slave *slave,
270 const struct spi_mem_op *op)
272 struct udevice *dev = slave->dev;
273 struct sifive_spi *spi = dev_get_priv(dev->parent);
274 unsigned long flags = SPI_XFER_BEGIN;
275 u8 opcode = op->cmd.opcode;
276 unsigned int pos = 0;
277 const void *tx_buf = NULL;
282 if (!op->addr.nbytes && !op->dummy.nbytes && !op->data.nbytes)
283 flags |= SPI_XFER_END;
285 spi->fmt_proto = op->cmd.buswidth;
287 /* send the opcode */
288 ret = sifive_spi_xfer(dev, 8, (void *)&opcode, NULL, flags);
290 dev_err(dev, "failed to xfer opcode\n");
294 op_len = op->addr.nbytes + op->dummy.nbytes;
297 /* send the addr + dummy */
298 if (op->addr.nbytes) {
300 for (i = 0; i < op->addr.nbytes; i++)
301 op_buf[pos + i] = op->addr.val >>
302 (8 * (op->addr.nbytes - i - 1));
304 pos += op->addr.nbytes;
307 if (op->dummy.nbytes)
308 memset(op_buf + pos, 0xff, op->dummy.nbytes);
310 /* make sure to set end flag, if no data bytes */
311 if (!op->data.nbytes)
312 flags |= SPI_XFER_END;
314 spi->fmt_proto = op->addr.buswidth;
316 ret = sifive_spi_xfer(dev, op_len * 8, op_buf, NULL, flags);
318 dev_err(dev, "failed to xfer addr + dummy\n");
323 /* send/received the data */
324 if (op->data.nbytes) {
325 if (op->data.dir == SPI_MEM_DATA_IN)
326 rx_buf = op->data.buf.in;
328 tx_buf = op->data.buf.out;
330 spi->fmt_proto = op->data.buswidth;
332 ret = sifive_spi_xfer(dev, op->data.nbytes * 8,
333 tx_buf, rx_buf, SPI_XFER_END);
335 dev_err(dev, "failed to xfer data\n");
343 static int sifive_spi_set_speed(struct udevice *bus, uint speed)
345 struct sifive_spi *spi = dev_get_priv(bus);
348 if (speed > spi->freq)
351 /* Cofigure max speed */
352 scale = (DIV_ROUND_UP(spi->freq >> 1, speed) - 1)
353 & SIFIVE_SPI_SCKDIV_DIV_MASK;
354 writel(scale, spi->regs + SIFIVE_SPI_REG_SCKDIV);
359 static int sifive_spi_set_mode(struct udevice *bus, uint mode)
361 struct sifive_spi *spi = dev_get_priv(bus);
364 /* Switch clock mode bits */
365 cr = readl(spi->regs + SIFIVE_SPI_REG_SCKMODE) &
366 ~SIFIVE_SPI_SCKMODE_MODE_MASK;
368 cr |= SIFIVE_SPI_SCKMODE_PHA;
370 cr |= SIFIVE_SPI_SCKMODE_POL;
372 writel(cr, spi->regs + SIFIVE_SPI_REG_SCKMODE);
377 static int sifive_spi_cs_info(struct udevice *bus, uint cs,
378 struct spi_cs_info *info)
380 struct sifive_spi *spi = dev_get_priv(bus);
382 if (cs >= spi->num_cs)
388 static void sifive_spi_init_hw(struct sifive_spi *spi)
392 /* probe the number of CS lines */
393 spi->cs_inactive = readl(spi->regs + SIFIVE_SPI_REG_CSDEF);
394 writel(0xffffffffU, spi->regs + SIFIVE_SPI_REG_CSDEF);
395 cs_bits = readl(spi->regs + SIFIVE_SPI_REG_CSDEF);
396 writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
398 printf("Could not auto probe CS lines\n");
402 spi->num_cs = ilog2(cs_bits) + 1;
403 if (spi->num_cs > SIFIVE_SPI_MAX_CS) {
404 printf("Invalid number of spi slaves\n");
408 /* Watermark interrupts are disabled by default */
409 writel(0, spi->regs + SIFIVE_SPI_REG_IE);
411 /* Default watermark FIFO threshold values */
412 writel(1, spi->regs + SIFIVE_SPI_REG_TXMARK);
413 writel(0, spi->regs + SIFIVE_SPI_REG_RXMARK);
415 /* Set CS/SCK Delays and Inactive Time to defaults */
416 writel(SIFIVE_SPI_DELAY0_CSSCK(1) | SIFIVE_SPI_DELAY0_SCKCS(1),
417 spi->regs + SIFIVE_SPI_REG_DELAY0);
418 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0),
419 spi->regs + SIFIVE_SPI_REG_DELAY1);
421 /* Exit specialized memory-mapped SPI flash mode */
422 writel(0, spi->regs + SIFIVE_SPI_REG_FCTRL);
425 static int sifive_spi_probe(struct udevice *bus)
427 struct sifive_spi *spi = dev_get_priv(bus);
431 spi->regs = (void *)(ulong)dev_remap_addr(bus);
435 spi->fifo_depth = dev_read_u32_default(bus,
437 SIFIVE_SPI_DEFAULT_DEPTH);
439 spi->bits_per_word = dev_read_u32_default(bus,
440 "sifive,max-bits-per-word",
441 SIFIVE_SPI_DEFAULT_BITS);
443 ret = clk_get_by_index(bus, 0, &clkdev);
446 spi->freq = clk_get_rate(&clkdev);
448 /* init the sifive spi hw */
449 sifive_spi_init_hw(spi);
454 static const struct spi_controller_mem_ops sifive_spi_mem_ops = {
455 .exec_op = sifive_spi_exec_op,
458 static const struct dm_spi_ops sifive_spi_ops = {
459 .xfer = sifive_spi_xfer,
460 .set_speed = sifive_spi_set_speed,
461 .set_mode = sifive_spi_set_mode,
462 .cs_info = sifive_spi_cs_info,
463 .mem_ops = &sifive_spi_mem_ops,
466 static const struct udevice_id sifive_spi_ids[] = {
467 { .compatible = "sifive,spi0" },
471 U_BOOT_DRIVER(sifive_spi) = {
472 .name = "sifive_spi",
474 .of_match = sifive_spi_ids,
475 .ops = &sifive_spi_ops,
476 .priv_auto_alloc_size = sizeof(struct sifive_spi),
477 .probe = sifive_spi_probe,