1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2011 Renesas Solutions Corp.
7 * Based on pxa2xx_spi.c:
8 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/sched.h>
14 #include <linux/errno.h>
15 #include <linux/timer.h>
16 #include <linux/delay.h>
17 #include <linux/list.h>
18 #include <linux/workqueue.h>
19 #include <linux/interrupt.h>
20 #include <linux/platform_device.h>
22 #include <linux/spi/spi.h>
24 #define SPI_SH_TBR 0x00
25 #define SPI_SH_RBR 0x00
26 #define SPI_SH_CR1 0x08
27 #define SPI_SH_CR2 0x10
28 #define SPI_SH_CR3 0x18
29 #define SPI_SH_CR4 0x20
30 #define SPI_SH_CR5 0x28
33 #define SPI_SH_TBE 0x80
34 #define SPI_SH_TBF 0x40
35 #define SPI_SH_RBE 0x20
36 #define SPI_SH_RBF 0x10
37 #define SPI_SH_PFONRD 0x08
38 #define SPI_SH_SSDB 0x04
39 #define SPI_SH_SSD 0x02
40 #define SPI_SH_SSA 0x01
43 #define SPI_SH_RSTF 0x80
44 #define SPI_SH_LOOPBK 0x40
45 #define SPI_SH_CPOL 0x20
46 #define SPI_SH_CPHA 0x10
47 #define SPI_SH_L1M0 0x08
50 #define SPI_SH_MAX_BYTE 0xFF
53 #define SPI_SH_TBEI 0x80
54 #define SPI_SH_TBFI 0x40
55 #define SPI_SH_RBEI 0x20
56 #define SPI_SH_RBFI 0x10
57 #define SPI_SH_WPABRT 0x04
58 #define SPI_SH_SSS 0x01
61 #define SPI_SH_P1L0 0x80
62 #define SPI_SH_PP1L0 0x40
63 #define SPI_SH_MUXI 0x20
64 #define SPI_SH_MUXIRQ 0x10
66 #define SPI_SH_FIFO_SIZE 32
67 #define SPI_SH_SEND_TIMEOUT (3 * HZ)
68 #define SPI_SH_RECEIVE_TIMEOUT (HZ >> 3)
75 struct spi_master *master;
76 struct list_head queue;
77 struct work_struct ws;
79 wait_queue_head_t wait;
84 static void spi_sh_write(struct spi_sh_data *ss, unsigned long data,
88 iowrite8(data, ss->addr + (offset >> 2));
89 else if (ss->width == 32)
90 iowrite32(data, ss->addr + offset);
93 static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset)
96 return ioread8(ss->addr + (offset >> 2));
97 else if (ss->width == 32)
98 return ioread32(ss->addr + offset);
103 static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val,
104 unsigned long offset)
108 tmp = spi_sh_read(ss, offset);
110 spi_sh_write(ss, tmp, offset);
113 static void spi_sh_clear_bit(struct spi_sh_data *ss, unsigned long val,
114 unsigned long offset)
118 tmp = spi_sh_read(ss, offset);
120 spi_sh_write(ss, tmp, offset);
123 static void clear_fifo(struct spi_sh_data *ss)
125 spi_sh_set_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
126 spi_sh_clear_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
129 static int spi_sh_wait_receive_buffer(struct spi_sh_data *ss)
131 int timeout = 100000;
133 while (spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
141 static int spi_sh_wait_write_buffer_empty(struct spi_sh_data *ss)
143 int timeout = 100000;
145 while (!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBE)) {
153 static int spi_sh_send(struct spi_sh_data *ss, struct spi_message *mesg,
154 struct spi_transfer *t)
163 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
165 data = (unsigned char *)t->tx_buf;
167 cur_len = min(SPI_SH_FIFO_SIZE, remain);
168 for (i = 0; i < cur_len &&
169 !(spi_sh_read(ss, SPI_SH_CR4) &
171 !(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBF);
173 spi_sh_write(ss, (unsigned long)data[i], SPI_SH_TBR);
175 if (spi_sh_read(ss, SPI_SH_CR4) & SPI_SH_WPABRT) {
176 /* Abort SPI operation */
177 spi_sh_set_bit(ss, SPI_SH_WPABRT, SPI_SH_CR4);
188 ss->cr1 &= ~SPI_SH_TBE;
189 spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
190 ret = wait_event_interruptible_timeout(ss->wait,
191 ss->cr1 & SPI_SH_TBE,
192 SPI_SH_SEND_TIMEOUT);
193 if (ret == 0 && !(ss->cr1 & SPI_SH_TBE)) {
194 printk(KERN_ERR "%s: timeout\n", __func__);
200 if (list_is_last(&t->transfer_list, &mesg->transfers)) {
201 spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
202 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
204 ss->cr1 &= ~SPI_SH_TBE;
205 spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
206 ret = wait_event_interruptible_timeout(ss->wait,
207 ss->cr1 & SPI_SH_TBE,
208 SPI_SH_SEND_TIMEOUT);
209 if (ret == 0 && (ss->cr1 & SPI_SH_TBE)) {
210 printk(KERN_ERR "%s: timeout\n", __func__);
218 static int spi_sh_receive(struct spi_sh_data *ss, struct spi_message *mesg,
219 struct spi_transfer *t)
227 if (t->len > SPI_SH_MAX_BYTE)
228 spi_sh_write(ss, SPI_SH_MAX_BYTE, SPI_SH_CR3);
230 spi_sh_write(ss, t->len, SPI_SH_CR3);
232 spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
233 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
235 spi_sh_wait_write_buffer_empty(ss);
237 data = (unsigned char *)t->rx_buf;
239 if (remain >= SPI_SH_FIFO_SIZE) {
240 ss->cr1 &= ~SPI_SH_RBF;
241 spi_sh_set_bit(ss, SPI_SH_RBF, SPI_SH_CR4);
242 ret = wait_event_interruptible_timeout(ss->wait,
243 ss->cr1 & SPI_SH_RBF,
244 SPI_SH_RECEIVE_TIMEOUT);
246 spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
247 printk(KERN_ERR "%s: timeout\n", __func__);
252 cur_len = min(SPI_SH_FIFO_SIZE, remain);
253 for (i = 0; i < cur_len; i++) {
254 if (spi_sh_wait_receive_buffer(ss))
256 data[i] = (unsigned char)spi_sh_read(ss, SPI_SH_RBR);
263 /* deassert CS when SPI is receiving. */
264 if (t->len > SPI_SH_MAX_BYTE) {
266 spi_sh_write(ss, 1, SPI_SH_CR3);
268 spi_sh_write(ss, 0, SPI_SH_CR3);
274 static void spi_sh_work(struct work_struct *work)
276 struct spi_sh_data *ss = container_of(work, struct spi_sh_data, ws);
277 struct spi_message *mesg;
278 struct spi_transfer *t;
282 pr_debug("%s: enter\n", __func__);
284 spin_lock_irqsave(&ss->lock, flags);
285 while (!list_empty(&ss->queue)) {
286 mesg = list_entry(ss->queue.next, struct spi_message, queue);
287 list_del_init(&mesg->queue);
289 spin_unlock_irqrestore(&ss->lock, flags);
290 list_for_each_entry(t, &mesg->transfers, transfer_list) {
291 pr_debug("tx_buf = %p, rx_buf = %p\n",
292 t->tx_buf, t->rx_buf);
293 pr_debug("len = %d, delay_usecs = %d\n",
294 t->len, t->delay_usecs);
297 ret = spi_sh_send(ss, mesg, t);
302 ret = spi_sh_receive(ss, mesg, t);
306 mesg->actual_length += t->len;
308 spin_lock_irqsave(&ss->lock, flags);
312 mesg->complete(mesg->context);
316 spi_sh_set_bit(ss, SPI_SH_SSD, SPI_SH_CR1);
319 spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
324 spin_unlock_irqrestore(&ss->lock, flags);
331 mesg->complete(mesg->context);
333 spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
339 static int spi_sh_setup(struct spi_device *spi)
341 struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
343 pr_debug("%s: enter\n", __func__);
345 spi_sh_write(ss, 0xfe, SPI_SH_CR1); /* SPI sycle stop */
346 spi_sh_write(ss, 0x00, SPI_SH_CR1); /* CR1 init */
347 spi_sh_write(ss, 0x00, SPI_SH_CR3); /* CR3 init */
352 spi_sh_write(ss, spi_sh_read(ss, SPI_SH_CR2) | 0x07, SPI_SH_CR2);
358 static int spi_sh_transfer(struct spi_device *spi, struct spi_message *mesg)
360 struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
363 pr_debug("%s: enter\n", __func__);
364 pr_debug("\tmode = %02x\n", spi->mode);
366 spin_lock_irqsave(&ss->lock, flags);
368 mesg->actual_length = 0;
369 mesg->status = -EINPROGRESS;
371 spi_sh_clear_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
373 list_add_tail(&mesg->queue, &ss->queue);
374 schedule_work(&ss->ws);
376 spin_unlock_irqrestore(&ss->lock, flags);
381 static void spi_sh_cleanup(struct spi_device *spi)
383 struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
385 pr_debug("%s: enter\n", __func__);
387 spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
391 static irqreturn_t spi_sh_irq(int irq, void *_ss)
393 struct spi_sh_data *ss = (struct spi_sh_data *)_ss;
396 cr1 = spi_sh_read(ss, SPI_SH_CR1);
397 if (cr1 & SPI_SH_TBE)
398 ss->cr1 |= SPI_SH_TBE;
399 if (cr1 & SPI_SH_TBF)
400 ss->cr1 |= SPI_SH_TBF;
401 if (cr1 & SPI_SH_RBE)
402 ss->cr1 |= SPI_SH_RBE;
403 if (cr1 & SPI_SH_RBF)
404 ss->cr1 |= SPI_SH_RBF;
407 spi_sh_clear_bit(ss, ss->cr1, SPI_SH_CR4);
414 static int spi_sh_remove(struct platform_device *pdev)
416 struct spi_sh_data *ss = platform_get_drvdata(pdev);
418 spi_unregister_master(ss->master);
420 free_irq(ss->irq, ss);
425 static int spi_sh_probe(struct platform_device *pdev)
427 struct resource *res;
428 struct spi_master *master;
429 struct spi_sh_data *ss;
433 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
434 if (unlikely(res == NULL)) {
435 dev_err(&pdev->dev, "invalid resource\n");
439 irq = platform_get_irq(pdev, 0);
441 dev_err(&pdev->dev, "platform_get_irq error: %d\n", irq);
445 master = spi_alloc_master(&pdev->dev, sizeof(struct spi_sh_data));
446 if (master == NULL) {
447 dev_err(&pdev->dev, "spi_alloc_master error.\n");
451 ss = spi_master_get_devdata(master);
452 platform_set_drvdata(pdev, ss);
454 switch (res->flags & IORESOURCE_MEM_TYPE_MASK) {
455 case IORESOURCE_MEM_8BIT:
458 case IORESOURCE_MEM_32BIT:
462 dev_err(&pdev->dev, "No support width\n");
468 ss->addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
469 if (ss->addr == NULL) {
470 dev_err(&pdev->dev, "ioremap error.\n");
474 INIT_LIST_HEAD(&ss->queue);
475 spin_lock_init(&ss->lock);
476 INIT_WORK(&ss->ws, spi_sh_work);
477 init_waitqueue_head(&ss->wait);
479 ret = request_irq(irq, spi_sh_irq, 0, "spi_sh", ss);
481 dev_err(&pdev->dev, "request_irq error\n");
485 master->num_chipselect = 2;
486 master->bus_num = pdev->id;
487 master->setup = spi_sh_setup;
488 master->transfer = spi_sh_transfer;
489 master->cleanup = spi_sh_cleanup;
491 ret = spi_register_master(master);
493 printk(KERN_ERR "spi_register_master error.\n");
502 spi_master_put(master);
507 static struct platform_driver spi_sh_driver = {
508 .probe = spi_sh_probe,
509 .remove = spi_sh_remove,
514 module_platform_driver(spi_sh_driver);
516 MODULE_DESCRIPTION("SH SPI bus driver");
517 MODULE_LICENSE("GPL v2");
518 MODULE_AUTHOR("Yoshihiro Shimoda");
519 MODULE_ALIAS("platform:sh_spi");