drivers/spi/spi-s3c64xx.c

   1 /*
   2  * Copyright (C) 2009 Samsung Electronics Ltd.
   3  *      Jaswinder Singh <jassi.brar@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/workqueue.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/clk.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/dmaengine.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/spi/spi.h>
  31 #include <linux/gpio.h>
  32 #include <linux/of.h>
  33 #include <linux/of_gpio.h>
  34
  35 #include <linux/platform_data/spi-s3c64xx.h>
  36
  37 #ifdef CONFIG_S3C_DMA
  38 #include <mach/dma.h>
  39 #endif
  40
  41 #define MAX_SPI_PORTS           3
  42 #define S3C64XX_SPI_QUIRK_POLL          (1 << 0)
  43
  44 /* Registers and bit-fields */
  45
  46 #define S3C64XX_SPI_CH_CFG              0x00
  47 #define S3C64XX_SPI_CLK_CFG             0x04
  48 #define S3C64XX_SPI_MODE_CFG    0x08
  49 #define S3C64XX_SPI_SLAVE_SEL   0x0C
  50 #define S3C64XX_SPI_INT_EN              0x10
  51 #define S3C64XX_SPI_STATUS              0x14
  52 #define S3C64XX_SPI_TX_DATA             0x18
  53 #define S3C64XX_SPI_RX_DATA             0x1C
  54 #define S3C64XX_SPI_PACKET_CNT  0x20
  55 #define S3C64XX_SPI_PENDING_CLR 0x24
  56 #define S3C64XX_SPI_SWAP_CFG    0x28
  57 #define S3C64XX_SPI_FB_CLK              0x2C
  58
  59 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
  60 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
  61 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
  62 #define S3C64XX_SPI_CPOL_L              (1<<3)
  63 #define S3C64XX_SPI_CPHA_B              (1<<2)
  64 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
  65 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
  66
  67 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
  68 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
  69 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
  70 #define S3C64XX_SPI_PSR_MASK            0xff
  71
  72 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
  73 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
  74 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
  75 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
  76 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
  77 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
  78 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
  79 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
  80 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
  81 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
  82 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
  83
  84 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
  85 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
  86
  87 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
  88 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
  89 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
  90 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
  91 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
  92 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
  93 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
  94
  95 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
  96 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
  97 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
  98 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
  99 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
 100 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
 101
 102 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
 103
 104 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
 105 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
 106 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
 107 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
 108 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
 109
 110 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
 111 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
 112 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
 113 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
 114 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
 115 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
 116 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
 117 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
 118
 119 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
 120
 121 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
 122 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
 123                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
 124 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
 125 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
 126                                         FIFO_LVL_MASK(i))
 127
 128 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
 129 #define S3C64XX_SPI_TRAILCNT_OFF        19
 130
 131 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
 132
 133 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 134 #define is_polling(x)   (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
 135
 136 #define RXBUSY    (1<<2)
 137 #define TXBUSY    (1<<3)
 138
 139 struct s3c64xx_spi_dma_data {
 140         struct dma_chan *ch;
 141         enum dma_transfer_direction direction;
 142         unsigned int dmach;
 143 };
 144
 145 /**
 146  * struct s3c64xx_spi_info - SPI Controller hardware info
 147  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
 148  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
 149  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
 150  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
 151  * @clk_from_cmu: True, if the controller does not include a clock mux and
 152  *      prescaler unit.
 153  *
 154  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
 155  * differ in some aspects such as the size of the fifo and spi bus clock
 156  * setup. Such differences are specified to the driver using this structure
 157  * which is provided as driver data to the driver.
 158  */
 159 struct s3c64xx_spi_port_config {
 160         int     fifo_lvl_mask[MAX_SPI_PORTS];
 161         int     rx_lvl_offset;
 162         int     tx_st_done;
 163         int     quirks;
 164         bool    high_speed;
 165         bool    clk_from_cmu;
 166 };
 167
 168 /**
 169  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 170  * @clk: Pointer to the spi clock.
 171  * @src_clk: Pointer to the clock used to generate SPI signals.
 172  * @master: Pointer to the SPI Protocol master.
 173  * @cntrlr_info: Platform specific data for the controller this driver manages.
 174  * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
 175  * @lock: Controller specific lock.
 176  * @state: Set of FLAGS to indicate status.
 177  * @rx_dmach: Controller's DMA channel for Rx.
 178  * @tx_dmach: Controller's DMA channel for Tx.
 179  * @sfr_start: BUS address of SPI controller regs.
 180  * @regs: Pointer to ioremap'ed controller registers.
 181  * @irq: interrupt
 182  * @xfer_completion: To indicate completion of xfer task.
 183  * @cur_mode: Stores the active configuration of the controller.
 184  * @cur_bpw: Stores the active bits per word settings.
 185  * @cur_speed: Stores the active xfer clock speed.
 186  */
 187 struct s3c64xx_spi_driver_data {
 188         void __iomem                    *regs;
 189         struct clk                      *clk;
 190         struct clk                      *src_clk;
 191         struct platform_device          *pdev;
 192         struct spi_master               *master;
 193         struct s3c64xx_spi_info  *cntrlr_info;
 194         struct spi_device               *tgl_spi;
 195         spinlock_t                      lock;
 196         unsigned long                   sfr_start;
 197         struct completion               xfer_completion;
 198         unsigned                        state;
 199         unsigned                        cur_mode, cur_bpw;
 200         unsigned                        cur_speed;
 201         struct s3c64xx_spi_dma_data     rx_dma;
 202         struct s3c64xx_spi_dma_data     tx_dma;
 203 #ifdef CONFIG_S3C_DMA
 204         struct samsung_dma_ops          *ops;
 205 #endif
 206         struct s3c64xx_spi_port_config  *port_conf;
 207         unsigned int                    port_id;
 208         bool                            cs_gpio;
 209 };
 210
 211 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 212 {
 213         void __iomem *regs = sdd->regs;
 214         unsigned long loops;
 215         u32 val;
 216
 217         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 218
 219         val = readl(regs + S3C64XX_SPI_CH_CFG);
 220         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
 221         writel(val, regs + S3C64XX_SPI_CH_CFG);
 222
 223         val = readl(regs + S3C64XX_SPI_CH_CFG);
 224         val |= S3C64XX_SPI_CH_SW_RST;
 225         val &= ~S3C64XX_SPI_CH_HS_EN;
 226         writel(val, regs + S3C64XX_SPI_CH_CFG);
 227
 228         /* Flush TxFIFO*/
 229         loops = msecs_to_loops(1);
 230         do {
 231                 val = readl(regs + S3C64XX_SPI_STATUS);
 232         } while (TX_FIFO_LVL(val, sdd) && loops--);
 233
 234         if (loops == 0)
 235                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
 236
 237         /* Flush RxFIFO*/
 238         loops = msecs_to_loops(1);
 239         do {
 240                 val = readl(regs + S3C64XX_SPI_STATUS);
 241                 if (RX_FIFO_LVL(val, sdd))
 242                         readl(regs + S3C64XX_SPI_RX_DATA);
 243                 else
 244                         break;
 245         } while (loops--);
 246
 247         if (loops == 0)
 248                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
 249
 250         val = readl(regs + S3C64XX_SPI_CH_CFG);
 251         val &= ~S3C64XX_SPI_CH_SW_RST;
 252         writel(val, regs + S3C64XX_SPI_CH_CFG);
 253
 254         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 255         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 256         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 257 }
 258
 259 static void s3c64xx_spi_dmacb(void *data)
 260 {
 261         struct s3c64xx_spi_driver_data *sdd;
 262         struct s3c64xx_spi_dma_data *dma = data;
 263         unsigned long flags;
 264
 265         if (dma->direction == DMA_DEV_TO_MEM)
 266                 sdd = container_of(data,
 267                         struct s3c64xx_spi_driver_data, rx_dma);
 268         else
 269                 sdd = container_of(data,
 270                         struct s3c64xx_spi_driver_data, tx_dma);
 271
 272         spin_lock_irqsave(&sdd->lock, flags);
 273
 274         if (dma->direction == DMA_DEV_TO_MEM) {
 275                 sdd->state &= ~RXBUSY;
 276                 if (!(sdd->state & TXBUSY))
 277                         complete(&sdd->xfer_completion);
 278         } else {
 279                 sdd->state &= ~TXBUSY;
 280                 if (!(sdd->state & RXBUSY))
 281                         complete(&sdd->xfer_completion);
 282         }
 283
 284         spin_unlock_irqrestore(&sdd->lock, flags);
 285 }
 286
 287 #ifdef CONFIG_S3C_DMA
 288 /* FIXME: remove this section once arch/arm/mach-s3c64xx uses dmaengine */
 289
 290 static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
 291         .name = "samsung-spi-dma",
 292 };
 293
 294 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
 295                                         unsigned len, dma_addr_t buf)
 296 {
 297         struct s3c64xx_spi_driver_data *sdd;
 298         struct samsung_dma_prep info;
 299         struct samsung_dma_config config;
 300
 301         if (dma->direction == DMA_DEV_TO_MEM) {
 302                 sdd = container_of((void *)dma,
 303                         struct s3c64xx_spi_driver_data, rx_dma);
 304                 config.direction = sdd->rx_dma.direction;
 305                 config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 306                 config.width = sdd->cur_bpw / 8;
 307                 sdd->ops->config((enum dma_ch)sdd->rx_dma.ch, &config);
 308         } else {
 309                 sdd = container_of((void *)dma,
 310                         struct s3c64xx_spi_driver_data, tx_dma);
 311                 config.direction =  sdd->tx_dma.direction;
 312                 config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 313                 config.width = sdd->cur_bpw / 8;
 314                 sdd->ops->config((enum dma_ch)sdd->tx_dma.ch, &config);
 315         }
 316
 317         info.cap = DMA_SLAVE;
 318         info.len = len;
 319         info.fp = s3c64xx_spi_dmacb;
 320         info.fp_param = dma;
 321         info.direction = dma->direction;
 322         info.buf = buf;
 323
 324         sdd->ops->prepare((enum dma_ch)dma->ch, &info);
 325         sdd->ops->trigger((enum dma_ch)dma->ch);
 326 }
 327
 328 static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
 329 {
 330         struct samsung_dma_req req;
 331         struct device *dev = &sdd->pdev->dev;
 332
 333         sdd->ops = samsung_dma_get_ops();
 334
 335         req.cap = DMA_SLAVE;
 336         req.client = &s3c64xx_spi_dma_client;
 337
 338         sdd->rx_dma.ch = (struct dma_chan *)(unsigned long)sdd->ops->request(
 339                                         sdd->rx_dma.dmach, &req, dev, "rx");
 340         sdd->tx_dma.ch = (struct dma_chan *)(unsigned long)sdd->ops->request(
 341                                         sdd->tx_dma.dmach, &req, dev, "tx");
 342
 343         return 1;
 344 }
 345
 346 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 347 {
 348         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 349
 350         /*
 351          * If DMA resource was not available during
 352          * probe, no need to continue with dma requests
 353          * else Acquire DMA channels
 354          */
 355         while (!is_polling(sdd) && !acquire_dma(sdd))
 356                 usleep_range(10000, 11000);
 357
 358         return 0;
 359 }
 360
 361 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
 362 {
 363         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 364
 365         /* Free DMA channels */
 366         if (!is_polling(sdd)) {
 367                 sdd->ops->release((enum dma_ch)sdd->rx_dma.ch,
 368                                         &s3c64xx_spi_dma_client);
 369                 sdd->ops->release((enum dma_ch)sdd->tx_dma.ch,
 370                                         &s3c64xx_spi_dma_client);
 371         }
 372
 373         return 0;
 374 }
 375
 376 static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
 377                                  struct s3c64xx_spi_dma_data *dma)
 378 {
 379         sdd->ops->stop((enum dma_ch)dma->ch);
 380 }
 381 #else
 382
 383 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
 384                         struct sg_table *sgt)
 385 {
 386         struct s3c64xx_spi_driver_data *sdd;
 387         struct dma_slave_config config;
 388         struct dma_async_tx_descriptor *desc;
 389
 390         memset(&config, 0, sizeof(config));
 391
 392         if (dma->direction == DMA_DEV_TO_MEM) {
 393                 sdd = container_of((void *)dma,
 394                         struct s3c64xx_spi_driver_data, rx_dma);
 395                 config.direction = dma->direction;
 396                 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 397                 config.src_addr_width = sdd->cur_bpw / 8;
 398                 config.src_maxburst = 1;
 399                 dmaengine_slave_config(dma->ch, &config);
 400         } else {
 401                 sdd = container_of((void *)dma,
 402                         struct s3c64xx_spi_driver_data, tx_dma);
 403                 config.direction = dma->direction;
 404                 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 405                 config.dst_addr_width = sdd->cur_bpw / 8;
 406                 config.dst_maxburst = 1;
 407                 dmaengine_slave_config(dma->ch, &config);
 408         }
 409
 410         desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
 411                                        dma->direction, DMA_PREP_INTERRUPT);
 412
 413         desc->callback = s3c64xx_spi_dmacb;
 414         desc->callback_param = dma;
 415
 416         dmaengine_submit(desc);
 417         dma_async_issue_pending(dma->ch);
 418 }
 419
 420 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 421 {
 422         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 423         dma_filter_fn filter = sdd->cntrlr_info->filter;
 424         struct device *dev = &sdd->pdev->dev;
 425         dma_cap_mask_t mask;
 426         int ret;
 427
 428         if (!is_polling(sdd)) {
 429                 dma_cap_zero(mask);
 430                 dma_cap_set(DMA_SLAVE, mask);
 431
 432                 /* Acquire DMA channels */
 433                 sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter,
 434                                    (void *)sdd->rx_dma.dmach, dev, "rx");
 435                 if (!sdd->rx_dma.ch) {
 436                         dev_err(dev, "Failed to get RX DMA channel\n");
 437                         ret = -EBUSY;
 438                         goto out;
 439                 }
 440
 441                 sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
 442                                    (void *)sdd->tx_dma.dmach, dev, "tx");
 443                 if (!sdd->tx_dma.ch) {
 444                         dev_err(dev, "Failed to get TX DMA channel\n");
 445                         ret = -EBUSY;
 446                         goto out_rx;
 447                 }
 448         }
 449
 450         ret = pm_runtime_get_sync(&sdd->pdev->dev);
 451         if (ret < 0) {
 452                 dev_err(dev, "Failed to enable device: %d\n", ret);
 453                 goto out_tx;
 454         }
 455
 456         return 0;
 457
 458 out_tx:
 459         dma_release_channel(sdd->tx_dma.ch);
 460 out_rx:
 461         dma_release_channel(sdd->rx_dma.ch);
 462 out:
 463         return ret;
 464 }
 465
 466 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
 467 {
 468         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 469
 470         /* Free DMA channels */
 471         if (!is_polling(sdd)) {
 472                 dma_release_channel(sdd->rx_dma.ch);
 473                 dma_release_channel(sdd->tx_dma.ch);
 474         }
 475
 476         pm_runtime_put(&sdd->pdev->dev);
 477         return 0;
 478 }
 479
 480 static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
 481                                  struct s3c64xx_spi_dma_data *dma)
 482 {
 483         dmaengine_terminate_all(dma->ch);
 484 }
 485 #endif
 486
 487 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 488                                 struct spi_device *spi,
 489                                 struct spi_transfer *xfer, int dma_mode)
 490 {
 491         void __iomem *regs = sdd->regs;
 492         u32 modecfg, chcfg;
 493
 494         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
 495         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 496
 497         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
 498         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
 499
 500         if (dma_mode) {
 501                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
 502         } else {
 503                 /* Always shift in data in FIFO, even if xfer is Tx only,
 504                  * this helps setting PCKT_CNT value for generating clocks
 505                  * as exactly needed.
 506                  */
 507                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 508                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 509                                         | S3C64XX_SPI_PACKET_CNT_EN,
 510                                         regs + S3C64XX_SPI_PACKET_CNT);
 511         }
 512
 513         if (xfer->tx_buf != NULL) {
 514                 sdd->state |= TXBUSY;
 515                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
 516                 if (dma_mode) {
 517                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
 518 #ifndef CONFIG_S3C_DMA
 519                         prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
 520 #else
 521                         prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
 522 #endif
 523                 } else {
 524                         switch (sdd->cur_bpw) {
 525                         case 32:
 526                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
 527                                         xfer->tx_buf, xfer->len / 4);
 528                                 break;
 529                         case 16:
 530                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
 531                                         xfer->tx_buf, xfer->len / 2);
 532                                 break;
 533                         default:
 534                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
 535                                         xfer->tx_buf, xfer->len);
 536                                 break;
 537                         }
 538                 }
 539         }
 540
 541         if (xfer->rx_buf != NULL) {
 542                 sdd->state |= RXBUSY;
 543
 544                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
 545                                         && !(sdd->cur_mode & SPI_CPHA))
 546                         chcfg |= S3C64XX_SPI_CH_HS_EN;
 547
 548                 if (dma_mode) {
 549                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
 550                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 551                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 552                                         | S3C64XX_SPI_PACKET_CNT_EN,
 553                                         regs + S3C64XX_SPI_PACKET_CNT);
 554 #ifndef CONFIG_S3C_DMA
 555                         prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
 556 #else
 557                         prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
 558 #endif
 559                 }
 560         }
 561
 562         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
 563         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
 564 }
 565
 566 static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
 567                                                 struct spi_device *spi)
 568 {
 569         if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
 570                 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
 571                         /* Deselect the last toggled device */
 572                         if (spi->cs_gpio >= 0)
 573                                 gpio_set_value(spi->cs_gpio,
 574                                         spi->mode & SPI_CS_HIGH ? 0 : 1);
 575                 }
 576                 sdd->tgl_spi = NULL;
 577         }
 578
 579         if (spi->cs_gpio >= 0)
 580                 gpio_set_value(spi->cs_gpio, spi->mode & SPI_CS_HIGH ? 1 : 0);
 581 }
 582
 583 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
 584                                         int timeout_ms)
 585 {
 586         void __iomem *regs = sdd->regs;
 587         unsigned long val = 1;
 588         u32 status;
 589
 590         /* max fifo depth available */
 591         u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
 592
 593         if (timeout_ms)
 594                 val = msecs_to_loops(timeout_ms);
 595
 596         do {
 597                 status = readl(regs + S3C64XX_SPI_STATUS);
 598         } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
 599
 600         /* return the actual received data length */
 601         return RX_FIFO_LVL(status, sdd);
 602 }
 603
 604 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
 605                                 struct spi_transfer *xfer, int dma_mode)
 606 {
 607         void __iomem *regs = sdd->regs;
 608         unsigned long val;
 609         int ms;
 610
 611         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 612         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 613         ms += 10; /* some tolerance */
 614
 615         if (dma_mode) {
 616                 val = msecs_to_jiffies(ms) + 10;
 617                 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
 618         } else {
 619                 u32 status;
 620                 val = msecs_to_loops(ms);
 621                 do {
 622                         status = readl(regs + S3C64XX_SPI_STATUS);
 623                 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
 624         }
 625
 626         if (dma_mode) {
 627                 u32 status;
 628
 629                 /*
 630                  * If the previous xfer was completed within timeout, then
 631                  * proceed further else return -EIO.
 632                  * DmaTx returns after simply writing data in the FIFO,
 633                  * w/o waiting for real transmission on the bus to finish.
 634                  * DmaRx returns only after Dma read data from FIFO which
 635                  * needs bus transmission to finish, so we don't worry if
 636                  * Xfer involved Rx(with or without Tx).
 637                  */
 638                 if (val && !xfer->rx_buf) {
 639                         val = msecs_to_loops(10);
 640                         status = readl(regs + S3C64XX_SPI_STATUS);
 641                         while ((TX_FIFO_LVL(status, sdd)
 642                                 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
 643                                         && --val) {
 644                                 cpu_relax();
 645                                 status = readl(regs + S3C64XX_SPI_STATUS);
 646                         }
 647
 648                 }
 649
 650                 /* If timed out while checking rx/tx status return error */
 651                 if (!val)
 652                         return -EIO;
 653         } else {
 654                 int loops;
 655                 u32 cpy_len;
 656                 u8 *buf;
 657
 658                 /* If it was only Tx */
 659                 if (!xfer->rx_buf) {
 660                         sdd->state &= ~TXBUSY;
 661                         return 0;
 662                 }
 663
 664                 /*
 665                  * If the receive length is bigger than the controller fifo
 666                  * size, calculate the loops and read the fifo as many times.
 667                  * loops = length / max fifo size (calculated by using the
 668                  * fifo mask).
 669                  * For any size less than the fifo size the below code is
 670                  * executed atleast once.
 671                  */
 672                 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
 673                 buf = xfer->rx_buf;
 674                 do {
 675                         /* wait for data to be received in the fifo */
 676                         cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
 677                                                 (loops ? ms : 0));
 678
 679                         switch (sdd->cur_bpw) {
 680                         case 32:
 681                                 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
 682                                         buf, cpy_len / 4);
 683                                 break;
 684                         case 16:
 685                                 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
 686                                         buf, cpy_len / 2);
 687                                 break;
 688                         default:
 689                                 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
 690                                         buf, cpy_len);
 691                                 break;
 692                         }
 693
 694                         buf = buf + cpy_len;
 695                 } while (loops--);
 696                 sdd->state &= ~RXBUSY;
 697         }
 698
 699         return 0;
 700 }
 701
 702 static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
 703                                                 struct spi_device *spi)
 704 {
 705         if (sdd->tgl_spi == spi)
 706                 sdd->tgl_spi = NULL;
 707
 708         if (spi->cs_gpio >= 0)
 709                 gpio_set_value(spi->cs_gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
 710 }
 711
 712 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 713 {
 714         void __iomem *regs = sdd->regs;
 715         u32 val;
 716
 717         /* Disable Clock */
 718         if (sdd->port_conf->clk_from_cmu) {
 719                 clk_disable_unprepare(sdd->src_clk);
 720         } else {
 721                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 722                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 723                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 724         }
 725
 726         /* Set Polarity and Phase */
 727         val = readl(regs + S3C64XX_SPI_CH_CFG);
 728         val &= ~(S3C64XX_SPI_CH_SLAVE |
 729                         S3C64XX_SPI_CPOL_L |
 730                         S3C64XX_SPI_CPHA_B);
 731
 732         if (sdd->cur_mode & SPI_CPOL)
 733                 val |= S3C64XX_SPI_CPOL_L;
 734
 735         if (sdd->cur_mode & SPI_CPHA)
 736                 val |= S3C64XX_SPI_CPHA_B;
 737
 738         writel(val, regs + S3C64XX_SPI_CH_CFG);
 739
 740         /* Set Channel & DMA Mode */
 741         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 742         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
 743                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
 744
 745         switch (sdd->cur_bpw) {
 746         case 32:
 747                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
 748                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
 749                 break;
 750         case 16:
 751                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
 752                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
 753                 break;
 754         default:
 755                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
 756                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
 757                 break;
 758         }
 759
 760         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 761
 762         if (sdd->port_conf->clk_from_cmu) {
 763                 /* Configure Clock */
 764                 /* There is half-multiplier before the SPI */
 765                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
 766                 /* Enable Clock */
 767                 clk_prepare_enable(sdd->src_clk);
 768         } else {
 769                 /* Configure Clock */
 770                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 771                 val &= ~S3C64XX_SPI_PSR_MASK;
 772                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
 773                                 & S3C64XX_SPI_PSR_MASK);
 774                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 775
 776                 /* Enable Clock */
 777                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 778                 val |= S3C64XX_SPI_ENCLK_ENABLE;
 779                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 780         }
 781 }
 782
 783 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
 784
 785 static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
 786                                                 struct spi_message *msg)
 787 {
 788         struct device *dev = &sdd->pdev->dev;
 789         struct spi_transfer *xfer;
 790
 791         if (is_polling(sdd) || msg->is_dma_mapped)
 792                 return 0;
 793
 794         /* First mark all xfer unmapped */
 795         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 796                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 797                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 798         }
 799
 800         /* Map until end or first fail */
 801         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 802
 803                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 804                         continue;
 805
 806                 if (xfer->tx_buf != NULL) {
 807                         xfer->tx_dma = dma_map_single(dev,
 808                                         (void *)xfer->tx_buf, xfer->len,
 809                                         DMA_TO_DEVICE);
 810                         if (dma_mapping_error(dev, xfer->tx_dma)) {
 811                                 dev_err(dev, "dma_map_single Tx failed\n");
 812                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 813                                 return -ENOMEM;
 814                         }
 815                 }
 816
 817                 if (xfer->rx_buf != NULL) {
 818                         xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
 819                                                 xfer->len, DMA_FROM_DEVICE);
 820                         if (dma_mapping_error(dev, xfer->rx_dma)) {
 821                                 dev_err(dev, "dma_map_single Rx failed\n");
 822                                 dma_unmap_single(dev, xfer->tx_dma,
 823                                                 xfer->len, DMA_TO_DEVICE);
 824                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 825                                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 826                                 return -ENOMEM;
 827                         }
 828                 }
 829         }
 830
 831         return 0;
 832 }
 833
 834 static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
 835                                                 struct spi_message *msg)
 836 {
 837         struct device *dev = &sdd->pdev->dev;
 838         struct spi_transfer *xfer;
 839
 840         if (is_polling(sdd) || msg->is_dma_mapped)
 841                 return;
 842
 843         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 844
 845                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 846                         continue;
 847
 848                 if (xfer->rx_buf != NULL
 849                                 && xfer->rx_dma != XFER_DMAADDR_INVALID)
 850                         dma_unmap_single(dev, xfer->rx_dma,
 851                                                 xfer->len, DMA_FROM_DEVICE);
 852
 853                 if (xfer->tx_buf != NULL
 854                                 && xfer->tx_dma != XFER_DMAADDR_INVALID)
 855                         dma_unmap_single(dev, xfer->tx_dma,
 856                                                 xfer->len, DMA_TO_DEVICE);
 857         }
 858 }
 859
 860 static int s3c64xx_spi_prepare_message(struct spi_master *master,
 861                                        struct spi_message *msg)
 862 {
 863         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 864         struct spi_device *spi = msg->spi;
 865         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 866
 867         /* If Master's(controller) state differs from that needed by Slave */
 868         if (sdd->cur_speed != spi->max_speed_hz
 869                         || sdd->cur_mode != spi->mode
 870                         || sdd->cur_bpw != spi->bits_per_word) {
 871                 sdd->cur_bpw = spi->bits_per_word;
 872                 sdd->cur_speed = spi->max_speed_hz;
 873                 sdd->cur_mode = spi->mode;
 874                 s3c64xx_spi_config(sdd);
 875         }
 876
 877         /* Map all the transfers if needed */
 878         if (s3c64xx_spi_map_mssg(sdd, msg)) {
 879                 dev_err(&spi->dev,
 880                         "Xfer: Unable to map message buffers!\n");
 881                 return -ENOMEM;
 882         }
 883
 884         /* Configure feedback delay */
 885         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
 886
 887         return 0;
 888 }
 889
 890 static int s3c64xx_spi_transfer_one(struct spi_master *master,
 891                                     struct spi_device *spi,
 892                                     struct spi_transfer *xfer)
 893 {
 894         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 895         int status;
 896         u32 speed;
 897         u8 bpw;
 898         unsigned long flags;
 899         int use_dma;
 900
 901         reinit_completion(&sdd->xfer_completion);
 902
 903         /* Only BPW and Speed may change across transfers */
 904         bpw = xfer->bits_per_word;
 905         speed = xfer->speed_hz ? : spi->max_speed_hz;
 906
 907         if (xfer->len % (bpw / 8)) {
 908                 dev_err(&spi->dev,
 909                         "Xfer length(%u) not a multiple of word size(%u)\n",
 910                         xfer->len, bpw / 8);
 911                 return -EIO;
 912         }
 913
 914         if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
 915                 sdd->cur_bpw = bpw;
 916                 sdd->cur_speed = speed;
 917                 s3c64xx_spi_config(sdd);
 918         }
 919
 920         /* Polling method for xfers not bigger than FIFO capacity */
 921         use_dma = 0;
 922         if (!is_polling(sdd) &&
 923             (sdd->rx_dma.ch && sdd->tx_dma.ch &&
 924              (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
 925                 use_dma = 1;
 926
 927         spin_lock_irqsave(&sdd->lock, flags);
 928
 929         /* Pending only which is to be done */
 930         sdd->state &= ~RXBUSY;
 931         sdd->state &= ~TXBUSY;
 932
 933         enable_datapath(sdd, spi, xfer, use_dma);
 934
 935         /* Start the signals */
 936         writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 937
 938         spin_unlock_irqrestore(&sdd->lock, flags);
 939
 940         status = wait_for_xfer(sdd, xfer, use_dma);
 941
 942         if (status) {
 943                 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
 944                         xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
 945                         (sdd->state & RXBUSY) ? 'f' : 'p',
 946                         (sdd->state & TXBUSY) ? 'f' : 'p',
 947                         xfer->len);
 948
 949                 if (use_dma) {
 950                         if (xfer->tx_buf != NULL
 951                             && (sdd->state & TXBUSY))
 952                                 s3c64xx_spi_dma_stop(sdd, &sdd->tx_dma);
 953                         if (xfer->rx_buf != NULL
 954                             && (sdd->state & RXBUSY))
 955                                 s3c64xx_spi_dma_stop(sdd, &sdd->rx_dma);
 956                 }
 957         } else {
 958                 flush_fifo(sdd);
 959         }
 960
 961         return status;
 962 }
 963
 964 static int s3c64xx_spi_unprepare_message(struct spi_master *master,
 965                                             struct spi_message *msg)
 966 {
 967         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 968
 969         s3c64xx_spi_unmap_mssg(sdd, msg);
 970
 971         return 0;
 972 }
 973
 974 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
 975                                 struct spi_device *spi)
 976 {
 977         struct s3c64xx_spi_csinfo *cs;
 978         struct device_node *slave_np, *data_np = NULL;
 979         struct s3c64xx_spi_driver_data *sdd;
 980         u32 fb_delay = 0;
 981
 982         sdd = spi_master_get_devdata(spi->master);
 983         slave_np = spi->dev.of_node;
 984         if (!slave_np) {
 985                 dev_err(&spi->dev, "device node not found\n");
 986                 return ERR_PTR(-EINVAL);
 987         }
 988
 989         data_np = of_get_child_by_name(slave_np, "controller-data");
 990         if (!data_np) {
 991                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
 992                 return ERR_PTR(-EINVAL);
 993         }
 994
 995         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 996         if (!cs) {
 997                 dev_err(&spi->dev, "could not allocate memory for controller data\n");
 998                 of_node_put(data_np);
 999                 return ERR_PTR(-ENOMEM);
1000         }
1001
1002         /* The CS line is asserted/deasserted by the gpio pin */
1003         if (sdd->cs_gpio)
1004                 cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
1005
1006         if (!gpio_is_valid(cs->line)) {
1007                 dev_err(&spi->dev, "chip select gpio is not specified or invalid\n");
1008                 kfree(cs);
1009                 of_node_put(data_np);
1010                 return ERR_PTR(-EINVAL);
1011         }
1012
1013         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
1014         cs->fb_delay = fb_delay;
1015         of_node_put(data_np);
1016         return cs;
1017 }
1018
1019 /*
1020  * Here we only check the validity of requested configuration
1021  * and save the configuration in a local data-structure.
1022  * The controller is actually configured only just before we
1023  * get a message to transfer.
1024  */
1025 static int s3c64xx_spi_setup(struct spi_device *spi)
1026 {
1027         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
1028         struct s3c64xx_spi_driver_data *sdd;
1029         struct s3c64xx_spi_info *sci;
1030         int err;
1031
1032         sdd = spi_master_get_devdata(spi->master);
1033         if (!cs && spi->dev.of_node) {
1034                 cs = s3c64xx_get_slave_ctrldata(spi);
1035                 spi->controller_data = cs;
1036         }
1037
1038         if (IS_ERR_OR_NULL(cs)) {
1039                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
1040                 return -ENODEV;
1041         }
1042
1043         if (!spi_get_ctldata(spi)) {
1044                 /* Request gpio only if cs line is asserted by gpio pins */
1045                 if (sdd->cs_gpio) {
1046                         err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH,
1047                                         dev_name(&spi->dev));
1048                         if (err) {
1049                                 dev_err(&spi->dev,
1050                                         "Failed to get /CS gpio [%d]: %d\n",
1051                                         cs->line, err);
1052                                 goto err_gpio_req;
1053                         }
1054
1055                         spi->cs_gpio = cs->line;
1056                 }
1057
1058                 spi_set_ctldata(spi, cs);
1059         }
1060
1061         sci = sdd->cntrlr_info;
1062
1063         pm_runtime_get_sync(&sdd->pdev->dev);
1064
1065         /* Check if we can provide the requested rate */
1066         if (!sdd->port_conf->clk_from_cmu) {
1067                 u32 psr, speed;
1068
1069                 /* Max possible */
1070                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
1071
1072                 if (spi->max_speed_hz > speed)
1073                         spi->max_speed_hz = speed;
1074
1075                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
1076                 psr &= S3C64XX_SPI_PSR_MASK;
1077                 if (psr == S3C64XX_SPI_PSR_MASK)
1078                         psr--;
1079
1080                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
1081                 if (spi->max_speed_hz < speed) {
1082                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
1083                                 psr++;
1084                         } else {
1085                                 err = -EINVAL;
1086                                 goto setup_exit;
1087                         }
1088                 }
1089
1090                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
1091                 if (spi->max_speed_hz >= speed) {
1092                         spi->max_speed_hz = speed;
1093                 } else {
1094                         dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
1095                                 spi->max_speed_hz);
1096                         err = -EINVAL;
1097                         goto setup_exit;
1098                 }
1099         }
1100
1101         pm_runtime_put(&sdd->pdev->dev);
1102         writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
1103         disable_cs(sdd, spi);
1104         return 0;
1105
1106 setup_exit:
1107         pm_runtime_put(&sdd->pdev->dev);
1108         /* setup() returns with device de-selected */
1109         writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
1110         disable_cs(sdd, spi);
1111
1112         gpio_free(cs->line);
1113         spi_set_ctldata(spi, NULL);
1114
1115 err_gpio_req:
1116         if (spi->dev.of_node)
1117                 kfree(cs);
1118
1119         return err;
1120 }
1121
1122 static void s3c64xx_spi_cleanup(struct spi_device *spi)
1123 {
1124         struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
1125         struct s3c64xx_spi_driver_data *sdd;
1126
1127         sdd = spi_master_get_devdata(spi->master);
1128         if (spi->cs_gpio) {
1129                 gpio_free(spi->cs_gpio);
1130                 if (spi->dev.of_node)
1131                         kfree(cs);
1132         }
1133         spi_set_ctldata(spi, NULL);
1134 }
1135
1136 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
1137 {
1138         struct s3c64xx_spi_driver_data *sdd = data;
1139         struct spi_master *spi = sdd->master;
1140         unsigned int val, clr = 0;
1141
1142         val = readl(sdd->regs + S3C64XX_SPI_STATUS);
1143
1144         if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
1145                 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
1146                 dev_err(&spi->dev, "RX overrun\n");
1147         }
1148         if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
1149                 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
1150                 dev_err(&spi->dev, "RX underrun\n");
1151         }
1152         if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
1153                 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
1154                 dev_err(&spi->dev, "TX overrun\n");
1155         }
1156         if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
1157                 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1158                 dev_err(&spi->dev, "TX underrun\n");
1159         }
1160
1161         /* Clear the pending irq by setting and then clearing it */
1162         writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1163         writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1164
1165         return IRQ_HANDLED;
1166 }
1167
1168 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
1169 {
1170         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1171         void __iomem *regs = sdd->regs;
1172         unsigned int val;
1173
1174         sdd->cur_speed = 0;
1175
1176         writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
1177
1178         /* Disable Interrupts - we use Polling if not DMA mode */
1179         writel(0, regs + S3C64XX_SPI_INT_EN);
1180
1181         if (!sdd->port_conf->clk_from_cmu)
1182                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
1183                                 regs + S3C64XX_SPI_CLK_CFG);
1184         writel(0, regs + S3C64XX_SPI_MODE_CFG);
1185         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1186
1187         /* Clear any irq pending bits, should set and clear the bits */
1188         val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1189                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1190                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1191                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1192         writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1193         writel(0, regs + S3C64XX_SPI_PENDING_CLR);
1194
1195         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1196
1197         val = readl(regs + S3C64XX_SPI_MODE_CFG);
1198         val &= ~S3C64XX_SPI_MODE_4BURST;
1199         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1200         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1201         writel(val, regs + S3C64XX_SPI_MODE_CFG);
1202
1203         flush_fifo(sdd);
1204 }
1205
1206 #ifdef CONFIG_OF
1207 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1208 {
1209         struct s3c64xx_spi_info *sci;
1210         u32 temp;
1211
1212         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1213         if (!sci) {
1214                 dev_err(dev, "memory allocation for spi_info failed\n");
1215                 return ERR_PTR(-ENOMEM);
1216         }
1217
1218         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1219                 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1220                 sci->src_clk_nr = 0;
1221         } else {
1222                 sci->src_clk_nr = temp;
1223         }
1224
1225         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1226                 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1227                 sci->num_cs = 1;
1228         } else {
1229                 sci->num_cs = temp;
1230         }
1231
1232         return sci;
1233 }
1234 #else
1235 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1236 {
1237         return dev_get_platdata(dev);
1238 }
1239 #endif
1240
1241 static const struct of_device_id s3c64xx_spi_dt_match[];
1242
1243 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1244                                                 struct platform_device *pdev)
1245 {
1246 #ifdef CONFIG_OF
1247         if (pdev->dev.of_node) {
1248                 const struct of_device_id *match;
1249                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1250                 return (struct s3c64xx_spi_port_config *)match->data;
1251         }
1252 #endif
1253         return (struct s3c64xx_spi_port_config *)
1254                          platform_get_device_id(pdev)->driver_data;
1255 }
1256
1257 static int s3c64xx_spi_probe(struct platform_device *pdev)
1258 {
1259         struct resource *mem_res;
1260         struct resource *res;
1261         struct s3c64xx_spi_driver_data *sdd;
1262         struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1263         struct spi_master *master;
1264         int ret, irq;
1265         char clk_name[16];
1266
1267         if (!sci && pdev->dev.of_node) {
1268                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1269                 if (IS_ERR(sci))
1270                         return PTR_ERR(sci);
1271         }
1272
1273         if (!sci) {
1274                 dev_err(&pdev->dev, "platform_data missing!\n");
1275                 return -ENODEV;
1276         }
1277
1278         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1279         if (mem_res == NULL) {
1280                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1281                 return -ENXIO;
1282         }
1283
1284         irq = platform_get_irq(pdev, 0);
1285         if (irq < 0) {
1286                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1287                 return irq;
1288         }
1289
1290         master = spi_alloc_master(&pdev->dev,
1291                                 sizeof(struct s3c64xx_spi_driver_data));
1292         if (master == NULL) {
1293                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1294                 return -ENOMEM;
1295         }
1296
1297         platform_set_drvdata(pdev, master);
1298
1299         sdd = spi_master_get_devdata(master);
1300         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1301         sdd->master = master;
1302         sdd->cntrlr_info = sci;
1303         sdd->pdev = pdev;
1304         sdd->sfr_start = mem_res->start;
1305         sdd->cs_gpio = true;
1306         if (pdev->dev.of_node) {
1307                 if (!of_find_property(pdev->dev.of_node, "cs-gpio", NULL))
1308                         sdd->cs_gpio = false;
1309
1310                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1311                 if (ret < 0) {
1312                         dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1313                                 ret);
1314                         goto err0;
1315                 }
1316                 sdd->port_id = ret;
1317         } else {
1318                 sdd->port_id = pdev->id;
1319         }
1320
1321         sdd->cur_bpw = 8;
1322
1323         if (!sdd->pdev->dev.of_node) {
1324                 res = platform_get_resource(pdev, IORESOURCE_DMA,  0);
1325                 if (!res) {
1326                         dev_warn(&pdev->dev, "Unable to get SPI tx dma resource. Switching to poll mode\n");
1327                         sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1328                 } else
1329                         sdd->tx_dma.dmach = res->start;
1330
1331                 res = platform_get_resource(pdev, IORESOURCE_DMA,  1);
1332                 if (!res) {
1333                         dev_warn(&pdev->dev, "Unable to get SPI rx dma resource. Switching to poll mode\n");
1334                         sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1335                 } else
1336                         sdd->rx_dma.dmach = res->start;
1337         }
1338
1339         sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1340         sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1341
1342         master->dev.of_node = pdev->dev.of_node;
1343         master->bus_num = sdd->port_id;
1344         master->setup = s3c64xx_spi_setup;
1345         master->cleanup = s3c64xx_spi_cleanup;
1346         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1347         master->prepare_message = s3c64xx_spi_prepare_message;
1348         master->transfer_one = s3c64xx_spi_transfer_one;
1349         master->unprepare_message = s3c64xx_spi_unprepare_message;
1350         master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1351         master->num_chipselect = sci->num_cs;
1352         master->dma_alignment = 8;
1353         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1354                                         SPI_BPW_MASK(8);
1355         /* the spi->mode bits understood by this driver: */
1356         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1357         master->auto_runtime_pm = true;
1358
1359         sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1360         if (IS_ERR(sdd->regs)) {
1361                 ret = PTR_ERR(sdd->regs);
1362                 goto err0;
1363         }
1364
1365         if (sci->cfg_gpio && sci->cfg_gpio()) {
1366                 dev_err(&pdev->dev, "Unable to config gpio\n");
1367                 ret = -EBUSY;
1368                 goto err0;
1369         }
1370
1371         /* Setup clocks */
1372         sdd->clk = devm_clk_get(&pdev->dev, "spi");
1373         if (IS_ERR(sdd->clk)) {
1374                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1375                 ret = PTR_ERR(sdd->clk);
1376                 goto err0;
1377         }
1378
1379         if (clk_prepare_enable(sdd->clk)) {
1380                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1381                 ret = -EBUSY;
1382                 goto err0;
1383         }
1384
1385         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1386         sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1387         if (IS_ERR(sdd->src_clk)) {
1388                 dev_err(&pdev->dev,
1389                         "Unable to acquire clock '%s'\n", clk_name);
1390                 ret = PTR_ERR(sdd->src_clk);
1391                 goto err2;
1392         }
1393
1394         if (clk_prepare_enable(sdd->src_clk)) {
1395                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1396                 ret = -EBUSY;
1397                 goto err2;
1398         }
1399
1400         /* Setup Deufult Mode */
1401         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1402
1403         spin_lock_init(&sdd->lock);
1404         init_completion(&sdd->xfer_completion);
1405
1406         ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1407                                 "spi-s3c64xx", sdd);
1408         if (ret != 0) {
1409                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1410                         irq, ret);
1411                 goto err3;
1412         }
1413
1414         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1415                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1416                sdd->regs + S3C64XX_SPI_INT_EN);
1417
1418         pm_runtime_set_active(&pdev->dev);
1419         pm_runtime_enable(&pdev->dev);
1420
1421         ret = devm_spi_register_master(&pdev->dev, master);
1422         if (ret != 0) {
1423                 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1424                 goto err3;
1425         }
1426
1427         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1428                                         sdd->port_id, master->num_chipselect);
1429         dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tDMA=[Rx-%d, Tx-%d]\n",
1430                                         mem_res,
1431                                         sdd->rx_dma.dmach, sdd->tx_dma.dmach);
1432
1433         return 0;
1434
1435 err3:
1436         clk_disable_unprepare(sdd->src_clk);
1437 err2:
1438         clk_disable_unprepare(sdd->clk);
1439 err0:
1440         spi_master_put(master);
1441
1442         return ret;
1443 }
1444
1445 static int s3c64xx_spi_remove(struct platform_device *pdev)
1446 {
1447         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1448         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1449
1450         pm_runtime_disable(&pdev->dev);
1451
1452         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1453
1454         clk_disable_unprepare(sdd->src_clk);
1455
1456         clk_disable_unprepare(sdd->clk);
1457
1458         return 0;
1459 }
1460
1461 #ifdef CONFIG_PM_SLEEP
1462 static int s3c64xx_spi_suspend(struct device *dev)
1463 {
1464         struct spi_master *master = dev_get_drvdata(dev);
1465         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1466
1467         int ret = spi_master_suspend(master);
1468         if (ret)
1469                 return ret;
1470
1471         if (!pm_runtime_suspended(dev)) {
1472                 clk_disable_unprepare(sdd->clk);
1473                 clk_disable_unprepare(sdd->src_clk);
1474         }
1475
1476         sdd->cur_speed = 0; /* Output Clock is stopped */
1477
1478         return 0;
1479 }
1480
1481 static int s3c64xx_spi_resume(struct device *dev)
1482 {
1483         struct spi_master *master = dev_get_drvdata(dev);
1484         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1485         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1486
1487         if (sci->cfg_gpio)
1488                 sci->cfg_gpio();
1489
1490         if (!pm_runtime_suspended(dev)) {
1491                 clk_prepare_enable(sdd->src_clk);
1492                 clk_prepare_enable(sdd->clk);
1493         }
1494
1495         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1496
1497         return spi_master_resume(master);
1498 }
1499 #endif /* CONFIG_PM_SLEEP */
1500
1501 #ifdef CONFIG_PM_RUNTIME
1502 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1503 {
1504         struct spi_master *master = dev_get_drvdata(dev);
1505         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1506
1507         clk_disable_unprepare(sdd->clk);
1508         clk_disable_unprepare(sdd->src_clk);
1509
1510         return 0;
1511 }
1512
1513 static int s3c64xx_spi_runtime_resume(struct device *dev)
1514 {
1515         struct spi_master *master = dev_get_drvdata(dev);
1516         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1517         int ret;
1518
1519         ret = clk_prepare_enable(sdd->src_clk);
1520         if (ret != 0)
1521                 return ret;
1522
1523         ret = clk_prepare_enable(sdd->clk);
1524         if (ret != 0) {
1525                 clk_disable_unprepare(sdd->src_clk);
1526                 return ret;
1527         }
1528
1529         return 0;
1530 }
1531 #endif /* CONFIG_PM_RUNTIME */
1532
1533 static const struct dev_pm_ops s3c64xx_spi_pm = {
1534         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1535         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1536                            s3c64xx_spi_runtime_resume, NULL)
1537 };
1538
1539 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1540         .fifo_lvl_mask  = { 0x7f },
1541         .rx_lvl_offset  = 13,
1542         .tx_st_done     = 21,
1543         .high_speed     = true,
1544 };
1545
1546 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1547         .fifo_lvl_mask  = { 0x7f, 0x7F },
1548         .rx_lvl_offset  = 13,
1549         .tx_st_done     = 21,
1550 };
1551
1552 static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
1553         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1554         .rx_lvl_offset  = 15,
1555         .tx_st_done     = 25,
1556 };
1557
1558 static struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
1559         .fifo_lvl_mask  = { 0x7f, 0x7F },
1560         .rx_lvl_offset  = 13,
1561         .tx_st_done     = 21,
1562         .high_speed     = true,
1563 };
1564
1565 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1566         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1567         .rx_lvl_offset  = 15,
1568         .tx_st_done     = 25,
1569         .high_speed     = true,
1570 };
1571
1572 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1573         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1574         .rx_lvl_offset  = 15,
1575         .tx_st_done     = 25,
1576         .high_speed     = true,
1577         .clk_from_cmu   = true,
1578 };
1579
1580 static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1581         .fifo_lvl_mask  = { 0x1ff },
1582         .rx_lvl_offset  = 15,
1583         .tx_st_done     = 25,
1584         .high_speed     = true,
1585         .clk_from_cmu   = true,
1586         .quirks         = S3C64XX_SPI_QUIRK_POLL,
1587 };
1588
1589 static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1590         {
1591                 .name           = "s3c2443-spi",
1592                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1593         }, {
1594                 .name           = "s3c6410-spi",
1595                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1596         }, {
1597                 .name           = "s5p64x0-spi",
1598                 .driver_data    = (kernel_ulong_t)&s5p64x0_spi_port_config,
1599         }, {
1600                 .name           = "s5pc100-spi",
1601                 .driver_data    = (kernel_ulong_t)&s5pc100_spi_port_config,
1602         }, {
1603                 .name           = "s5pv210-spi",
1604                 .driver_data    = (kernel_ulong_t)&s5pv210_spi_port_config,
1605         }, {
1606                 .name           = "exynos4210-spi",
1607                 .driver_data    = (kernel_ulong_t)&exynos4_spi_port_config,
1608         },
1609         { },
1610 };
1611
1612 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1613         { .compatible = "samsung,s3c2443-spi",
1614                         .data = (void *)&s3c2443_spi_port_config,
1615         },
1616         { .compatible = "samsung,s3c6410-spi",
1617                         .data = (void *)&s3c6410_spi_port_config,
1618         },
1619         { .compatible = "samsung,s5pc100-spi",
1620                         .data = (void *)&s5pc100_spi_port_config,
1621         },
1622         { .compatible = "samsung,s5pv210-spi",
1623                         .data = (void *)&s5pv210_spi_port_config,
1624         },
1625         { .compatible = "samsung,exynos4210-spi",
1626                         .data = (void *)&exynos4_spi_port_config,
1627         },
1628         { .compatible = "samsung,exynos5440-spi",
1629                         .data = (void *)&exynos5440_spi_port_config,
1630         },
1631         { },
1632 };
1633 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1634
1635 static struct platform_driver s3c64xx_spi_driver = {
1636         .driver = {
1637                 .name   = "s3c64xx-spi",
1638                 .owner = THIS_MODULE,
1639                 .pm = &s3c64xx_spi_pm,
1640                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1641         },
1642         .probe = s3c64xx_spi_probe,
1643         .remove = s3c64xx_spi_remove,
1644         .id_table = s3c64xx_spi_driver_ids,
1645 };
1646 MODULE_ALIAS("platform:s3c64xx-spi");
1647
1648 module_platform_driver(s3c64xx_spi_driver);
1649
1650 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1651 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1652 MODULE_LICENSE("GPL");