1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 // Jaswinder Singh <jassi.brar@samsung.com>
6 #include <linux/init.h>
7 #include <linux/module.h>
8 #include <linux/interrupt.h>
9 #include <linux/delay.h>
10 #include <linux/clk.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/dmaengine.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/spi/spi.h>
16 #include <linux/gpio.h>
18 #include <linux/of_device.h>
19 #include <linux/of_gpio.h>
21 #include <linux/platform_data/spi-s3c64xx.h>
23 #define MAX_SPI_PORTS 6
24 #define S3C64XX_SPI_QUIRK_POLL (1 << 0)
25 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
26 #define AUTOSUSPEND_TIMEOUT 2000
28 /* Registers and bit-fields */
30 #define S3C64XX_SPI_CH_CFG 0x00
31 #define S3C64XX_SPI_CLK_CFG 0x04
32 #define S3C64XX_SPI_MODE_CFG 0x08
33 #define S3C64XX_SPI_CS_REG 0x0C
34 #define S3C64XX_SPI_INT_EN 0x10
35 #define S3C64XX_SPI_STATUS 0x14
36 #define S3C64XX_SPI_TX_DATA 0x18
37 #define S3C64XX_SPI_RX_DATA 0x1C
38 #define S3C64XX_SPI_PACKET_CNT 0x20
39 #define S3C64XX_SPI_PENDING_CLR 0x24
40 #define S3C64XX_SPI_SWAP_CFG 0x28
41 #define S3C64XX_SPI_FB_CLK 0x2C
43 #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
44 #define S3C64XX_SPI_CH_SW_RST (1<<5)
45 #define S3C64XX_SPI_CH_SLAVE (1<<4)
46 #define S3C64XX_SPI_CPOL_L (1<<3)
47 #define S3C64XX_SPI_CPHA_B (1<<2)
48 #define S3C64XX_SPI_CH_RXCH_ON (1<<1)
49 #define S3C64XX_SPI_CH_TXCH_ON (1<<0)
51 #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
52 #define S3C64XX_SPI_CLKSEL_SRCSHFT 9
53 #define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
54 #define S3C64XX_SPI_PSR_MASK 0xff
56 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
57 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
58 #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
59 #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
60 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
61 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
62 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
63 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
64 #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
65 #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
66 #define S3C64XX_SPI_MODE_4BURST (1<<0)
68 #define S3C64XX_SPI_CS_NSC_CNT_2 (2<<4)
69 #define S3C64XX_SPI_CS_AUTO (1<<1)
70 #define S3C64XX_SPI_CS_SIG_INACT (1<<0)
72 #define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
73 #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
74 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
75 #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
76 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
77 #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
78 #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
80 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
81 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
82 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
83 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
84 #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
85 #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
87 #define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
88 #define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0)
90 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
91 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
92 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
93 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
94 #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
96 #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
97 #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
98 #define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
99 #define S3C64XX_SPI_SWAP_RX_EN (1<<4)
100 #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
101 #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
102 #define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
103 #define S3C64XX_SPI_SWAP_TX_EN (1<<0)
105 #define S3C64XX_SPI_FBCLK_MSK (3<<0)
107 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
108 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
109 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
110 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
111 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
114 #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
115 #define S3C64XX_SPI_TRAILCNT_OFF 19
117 #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
119 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
120 #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
122 #define RXBUSY (1<<2)
123 #define TXBUSY (1<<3)
125 struct s3c64xx_spi_dma_data {
128 enum dma_transfer_direction direction;
132 * struct s3c64xx_spi_port_config - SPI Controller hardware info
133 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
134 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
135 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
136 * @quirks: Bitmask of known quirks
137 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
138 * @clk_from_cmu: True, if the controller does not include a clock mux and
140 * @clk_ioclk: True if clock is present on this device
142 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
143 * differ in some aspects such as the size of the fifo and spi bus clock
144 * setup. Such differences are specified to the driver using this structure
145 * which is provided as driver data to the driver.
147 struct s3c64xx_spi_port_config {
148 int fifo_lvl_mask[MAX_SPI_PORTS];
158 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
159 * @clk: Pointer to the spi clock.
160 * @src_clk: Pointer to the clock used to generate SPI signals.
161 * @ioclk: Pointer to the i/o clock between master and slave
162 * @pdev: Pointer to device's platform device data
163 * @master: Pointer to the SPI Protocol master.
164 * @cntrlr_info: Platform specific data for the controller this driver manages.
165 * @lock: Controller specific lock.
166 * @state: Set of FLAGS to indicate status.
167 * @sfr_start: BUS address of SPI controller regs.
168 * @regs: Pointer to ioremap'ed controller registers.
169 * @xfer_completion: To indicate completion of xfer task.
170 * @cur_mode: Stores the active configuration of the controller.
171 * @cur_bpw: Stores the active bits per word settings.
172 * @cur_speed: Current clock speed
173 * @rx_dma: Local receive DMA data (e.g. chan and direction)
174 * @tx_dma: Local transmit DMA data (e.g. chan and direction)
175 * @port_conf: Local SPI port configuartion data
176 * @port_id: Port identification number
178 struct s3c64xx_spi_driver_data {
183 struct platform_device *pdev;
184 struct spi_master *master;
185 struct s3c64xx_spi_info *cntrlr_info;
187 unsigned long sfr_start;
188 struct completion xfer_completion;
190 unsigned cur_mode, cur_bpw;
192 struct s3c64xx_spi_dma_data rx_dma;
193 struct s3c64xx_spi_dma_data tx_dma;
194 const struct s3c64xx_spi_port_config *port_conf;
195 unsigned int port_id;
198 static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd)
200 void __iomem *regs = sdd->regs;
204 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
206 val = readl(regs + S3C64XX_SPI_CH_CFG);
207 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
208 writel(val, regs + S3C64XX_SPI_CH_CFG);
210 val = readl(regs + S3C64XX_SPI_CH_CFG);
211 val |= S3C64XX_SPI_CH_SW_RST;
212 val &= ~S3C64XX_SPI_CH_HS_EN;
213 writel(val, regs + S3C64XX_SPI_CH_CFG);
216 loops = msecs_to_loops(1);
218 val = readl(regs + S3C64XX_SPI_STATUS);
219 } while (TX_FIFO_LVL(val, sdd) && loops--);
222 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
225 loops = msecs_to_loops(1);
227 val = readl(regs + S3C64XX_SPI_STATUS);
228 if (RX_FIFO_LVL(val, sdd))
229 readl(regs + S3C64XX_SPI_RX_DATA);
235 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
237 val = readl(regs + S3C64XX_SPI_CH_CFG);
238 val &= ~S3C64XX_SPI_CH_SW_RST;
239 writel(val, regs + S3C64XX_SPI_CH_CFG);
241 val = readl(regs + S3C64XX_SPI_MODE_CFG);
242 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
243 writel(val, regs + S3C64XX_SPI_MODE_CFG);
246 static void s3c64xx_spi_dmacb(void *data)
248 struct s3c64xx_spi_driver_data *sdd;
249 struct s3c64xx_spi_dma_data *dma = data;
252 if (dma->direction == DMA_DEV_TO_MEM)
253 sdd = container_of(data,
254 struct s3c64xx_spi_driver_data, rx_dma);
256 sdd = container_of(data,
257 struct s3c64xx_spi_driver_data, tx_dma);
259 spin_lock_irqsave(&sdd->lock, flags);
261 if (dma->direction == DMA_DEV_TO_MEM) {
262 sdd->state &= ~RXBUSY;
263 if (!(sdd->state & TXBUSY))
264 complete(&sdd->xfer_completion);
266 sdd->state &= ~TXBUSY;
267 if (!(sdd->state & RXBUSY))
268 complete(&sdd->xfer_completion);
271 spin_unlock_irqrestore(&sdd->lock, flags);
274 static int prepare_dma(struct s3c64xx_spi_dma_data *dma,
275 struct sg_table *sgt)
277 struct s3c64xx_spi_driver_data *sdd;
278 struct dma_slave_config config;
279 struct dma_async_tx_descriptor *desc;
282 memset(&config, 0, sizeof(config));
284 if (dma->direction == DMA_DEV_TO_MEM) {
285 sdd = container_of((void *)dma,
286 struct s3c64xx_spi_driver_data, rx_dma);
287 config.direction = dma->direction;
288 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
289 config.src_addr_width = sdd->cur_bpw / 8;
290 config.src_maxburst = 1;
291 dmaengine_slave_config(dma->ch, &config);
293 sdd = container_of((void *)dma,
294 struct s3c64xx_spi_driver_data, tx_dma);
295 config.direction = dma->direction;
296 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
297 config.dst_addr_width = sdd->cur_bpw / 8;
298 config.dst_maxburst = 1;
299 dmaengine_slave_config(dma->ch, &config);
302 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
303 dma->direction, DMA_PREP_INTERRUPT);
305 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist",
306 dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx");
310 desc->callback = s3c64xx_spi_dmacb;
311 desc->callback_param = dma;
313 dma->cookie = dmaengine_submit(desc);
314 ret = dma_submit_error(dma->cookie);
316 dev_err(&sdd->pdev->dev, "DMA submission failed");
320 dma_async_issue_pending(dma->ch);
324 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
326 struct s3c64xx_spi_driver_data *sdd =
327 spi_master_get_devdata(spi->master);
329 if (sdd->cntrlr_info->no_cs)
333 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
334 writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
336 u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG);
338 ssel |= (S3C64XX_SPI_CS_AUTO |
339 S3C64XX_SPI_CS_NSC_CNT_2);
340 writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG);
343 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
344 writel(S3C64XX_SPI_CS_SIG_INACT,
345 sdd->regs + S3C64XX_SPI_CS_REG);
349 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
351 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
356 spi->dma_rx = sdd->rx_dma.ch;
357 spi->dma_tx = sdd->tx_dma.ch;
362 static bool s3c64xx_spi_can_dma(struct spi_master *master,
363 struct spi_device *spi,
364 struct spi_transfer *xfer)
366 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
368 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
371 static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
372 struct spi_transfer *xfer, int dma_mode)
374 void __iomem *regs = sdd->regs;
378 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
379 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
381 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
382 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
385 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
387 /* Always shift in data in FIFO, even if xfer is Tx only,
388 * this helps setting PCKT_CNT value for generating clocks
391 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
392 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
393 | S3C64XX_SPI_PACKET_CNT_EN,
394 regs + S3C64XX_SPI_PACKET_CNT);
397 if (xfer->tx_buf != NULL) {
398 sdd->state |= TXBUSY;
399 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
401 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
402 ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
404 switch (sdd->cur_bpw) {
406 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
407 xfer->tx_buf, xfer->len / 4);
410 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
411 xfer->tx_buf, xfer->len / 2);
414 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
415 xfer->tx_buf, xfer->len);
421 if (xfer->rx_buf != NULL) {
422 sdd->state |= RXBUSY;
424 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
425 && !(sdd->cur_mode & SPI_CPHA))
426 chcfg |= S3C64XX_SPI_CH_HS_EN;
429 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
430 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
431 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
432 | S3C64XX_SPI_PACKET_CNT_EN,
433 regs + S3C64XX_SPI_PACKET_CNT);
434 ret = prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
441 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
442 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
447 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
450 void __iomem *regs = sdd->regs;
451 unsigned long val = 1;
454 /* max fifo depth available */
455 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
458 val = msecs_to_loops(timeout_ms);
461 status = readl(regs + S3C64XX_SPI_STATUS);
462 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
464 /* return the actual received data length */
465 return RX_FIFO_LVL(status, sdd);
468 static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
469 struct spi_transfer *xfer)
471 void __iomem *regs = sdd->regs;
476 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
477 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
478 ms += 30; /* some tolerance */
479 ms = max(ms, 100); /* minimum timeout */
481 val = msecs_to_jiffies(ms) + 10;
482 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
485 * If the previous xfer was completed within timeout, then
486 * proceed further else return -EIO.
487 * DmaTx returns after simply writing data in the FIFO,
488 * w/o waiting for real transmission on the bus to finish.
489 * DmaRx returns only after Dma read data from FIFO which
490 * needs bus transmission to finish, so we don't worry if
491 * Xfer involved Rx(with or without Tx).
493 if (val && !xfer->rx_buf) {
494 val = msecs_to_loops(10);
495 status = readl(regs + S3C64XX_SPI_STATUS);
496 while ((TX_FIFO_LVL(status, sdd)
497 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
500 status = readl(regs + S3C64XX_SPI_STATUS);
505 /* If timed out while checking rx/tx status return error */
512 static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
513 struct spi_transfer *xfer)
515 void __iomem *regs = sdd->regs;
523 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
524 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
525 ms += 10; /* some tolerance */
527 val = msecs_to_loops(ms);
529 status = readl(regs + S3C64XX_SPI_STATUS);
530 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
535 /* If it was only Tx */
537 sdd->state &= ~TXBUSY;
542 * If the receive length is bigger than the controller fifo
543 * size, calculate the loops and read the fifo as many times.
544 * loops = length / max fifo size (calculated by using the
546 * For any size less than the fifo size the below code is
547 * executed atleast once.
549 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
552 /* wait for data to be received in the fifo */
553 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
556 switch (sdd->cur_bpw) {
558 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
562 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
566 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
573 sdd->state &= ~RXBUSY;
578 static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
580 void __iomem *regs = sdd->regs;
585 if (!sdd->port_conf->clk_from_cmu) {
586 val = readl(regs + S3C64XX_SPI_CLK_CFG);
587 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
588 writel(val, regs + S3C64XX_SPI_CLK_CFG);
591 /* Set Polarity and Phase */
592 val = readl(regs + S3C64XX_SPI_CH_CFG);
593 val &= ~(S3C64XX_SPI_CH_SLAVE |
597 if (sdd->cur_mode & SPI_CPOL)
598 val |= S3C64XX_SPI_CPOL_L;
600 if (sdd->cur_mode & SPI_CPHA)
601 val |= S3C64XX_SPI_CPHA_B;
603 writel(val, regs + S3C64XX_SPI_CH_CFG);
605 /* Set Channel & DMA Mode */
606 val = readl(regs + S3C64XX_SPI_MODE_CFG);
607 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
608 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
610 switch (sdd->cur_bpw) {
612 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
613 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
616 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
617 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
620 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
621 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
625 writel(val, regs + S3C64XX_SPI_MODE_CFG);
627 if (sdd->port_conf->clk_from_cmu) {
628 /* The src_clk clock is divided internally by 2 */
629 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
632 sdd->cur_speed = clk_get_rate(sdd->src_clk) / 2;
634 /* Configure Clock */
635 val = readl(regs + S3C64XX_SPI_CLK_CFG);
636 val &= ~S3C64XX_SPI_PSR_MASK;
637 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
638 & S3C64XX_SPI_PSR_MASK);
639 writel(val, regs + S3C64XX_SPI_CLK_CFG);
642 val = readl(regs + S3C64XX_SPI_CLK_CFG);
643 val |= S3C64XX_SPI_ENCLK_ENABLE;
644 writel(val, regs + S3C64XX_SPI_CLK_CFG);
650 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
652 static int s3c64xx_spi_prepare_message(struct spi_master *master,
653 struct spi_message *msg)
655 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
656 struct spi_device *spi = msg->spi;
657 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
659 /* Configure feedback delay */
660 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
665 static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi)
667 struct spi_controller *ctlr = spi->controller;
669 return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX;
672 static int s3c64xx_spi_transfer_one(struct spi_master *master,
673 struct spi_device *spi,
674 struct spi_transfer *xfer)
676 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
677 const unsigned int fifo_len = (FIFO_LVL_MASK(sdd) >> 1) + 1;
678 const void *tx_buf = NULL;
680 int target_len = 0, origin_len = 0;
687 reinit_completion(&sdd->xfer_completion);
689 /* Only BPW and Speed may change across transfers */
690 bpw = xfer->bits_per_word;
691 speed = xfer->speed_hz;
693 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
695 sdd->cur_speed = speed;
696 sdd->cur_mode = spi->mode;
697 status = s3c64xx_spi_config(sdd);
702 if (!is_polling(sdd) && (xfer->len > fifo_len) &&
703 sdd->rx_dma.ch && sdd->tx_dma.ch) {
706 } else if (is_polling(sdd) && xfer->len > fifo_len) {
707 tx_buf = xfer->tx_buf;
708 rx_buf = xfer->rx_buf;
709 origin_len = xfer->len;
711 target_len = xfer->len;
712 if (xfer->len > fifo_len)
713 xfer->len = fifo_len;
717 spin_lock_irqsave(&sdd->lock, flags);
719 /* Pending only which is to be done */
720 sdd->state &= ~RXBUSY;
721 sdd->state &= ~TXBUSY;
723 /* Start the signals */
724 s3c64xx_spi_set_cs(spi, true);
726 status = s3c64xx_enable_datapath(sdd, xfer, use_dma);
728 spin_unlock_irqrestore(&sdd->lock, flags);
731 dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status);
736 status = s3c64xx_wait_for_dma(sdd, xfer);
738 status = s3c64xx_wait_for_pio(sdd, xfer);
742 "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n",
743 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
744 (sdd->state & RXBUSY) ? 'f' : 'p',
745 (sdd->state & TXBUSY) ? 'f' : 'p',
746 xfer->len, use_dma ? 1 : 0, status);
749 struct dma_tx_state s;
751 if (xfer->tx_buf && (sdd->state & TXBUSY)) {
752 dmaengine_pause(sdd->tx_dma.ch);
753 dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s);
754 dmaengine_terminate_all(sdd->tx_dma.ch);
755 dev_err(&spi->dev, "TX residue: %d\n", s.residue);
758 if (xfer->rx_buf && (sdd->state & RXBUSY)) {
759 dmaengine_pause(sdd->rx_dma.ch);
760 dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s);
761 dmaengine_terminate_all(sdd->rx_dma.ch);
762 dev_err(&spi->dev, "RX residue: %d\n", s.residue);
766 s3c64xx_flush_fifo(sdd);
768 if (target_len > 0) {
769 target_len -= xfer->len;
772 xfer->tx_buf += xfer->len;
775 xfer->rx_buf += xfer->len;
777 if (target_len > fifo_len)
778 xfer->len = fifo_len;
780 xfer->len = target_len;
782 } while (target_len > 0);
785 /* Restore original xfer buffers and length */
786 xfer->tx_buf = tx_buf;
787 xfer->rx_buf = rx_buf;
788 xfer->len = origin_len;
794 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
795 struct spi_device *spi)
797 struct s3c64xx_spi_csinfo *cs;
798 struct device_node *slave_np, *data_np = NULL;
801 slave_np = spi->dev.of_node;
803 dev_err(&spi->dev, "device node not found\n");
804 return ERR_PTR(-EINVAL);
807 data_np = of_get_child_by_name(slave_np, "controller-data");
809 dev_err(&spi->dev, "child node 'controller-data' not found\n");
810 return ERR_PTR(-EINVAL);
813 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
815 of_node_put(data_np);
816 return ERR_PTR(-ENOMEM);
819 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
820 cs->fb_delay = fb_delay;
821 of_node_put(data_np);
826 * Here we only check the validity of requested configuration
827 * and save the configuration in a local data-structure.
828 * The controller is actually configured only just before we
829 * get a message to transfer.
831 static int s3c64xx_spi_setup(struct spi_device *spi)
833 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
834 struct s3c64xx_spi_driver_data *sdd;
837 sdd = spi_master_get_devdata(spi->master);
838 if (spi->dev.of_node) {
839 cs = s3c64xx_get_slave_ctrldata(spi);
840 spi->controller_data = cs;
842 /* On non-DT platforms the SPI core will set spi->cs_gpio
843 * to -ENOENT. The GPIO pin used to drive the chip select
844 * is defined by using platform data so spi->cs_gpio value
845 * has to be override to have the proper GPIO pin number.
847 spi->cs_gpio = cs->line;
850 if (IS_ERR_OR_NULL(cs)) {
851 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
855 if (!spi_get_ctldata(spi)) {
856 if (gpio_is_valid(spi->cs_gpio)) {
857 err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
858 dev_name(&spi->dev));
861 "Failed to get /CS gpio [%d]: %d\n",
867 spi_set_ctldata(spi, cs);
870 pm_runtime_get_sync(&sdd->pdev->dev);
872 /* Check if we can provide the requested rate */
873 if (!sdd->port_conf->clk_from_cmu) {
877 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
879 if (spi->max_speed_hz > speed)
880 spi->max_speed_hz = speed;
882 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
883 psr &= S3C64XX_SPI_PSR_MASK;
884 if (psr == S3C64XX_SPI_PSR_MASK)
887 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
888 if (spi->max_speed_hz < speed) {
889 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
897 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
898 if (spi->max_speed_hz >= speed) {
899 spi->max_speed_hz = speed;
901 dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
908 pm_runtime_mark_last_busy(&sdd->pdev->dev);
909 pm_runtime_put_autosuspend(&sdd->pdev->dev);
910 s3c64xx_spi_set_cs(spi, false);
915 pm_runtime_mark_last_busy(&sdd->pdev->dev);
916 pm_runtime_put_autosuspend(&sdd->pdev->dev);
917 /* setup() returns with device de-selected */
918 s3c64xx_spi_set_cs(spi, false);
920 if (gpio_is_valid(spi->cs_gpio))
921 gpio_free(spi->cs_gpio);
922 spi_set_ctldata(spi, NULL);
925 if (spi->dev.of_node)
931 static void s3c64xx_spi_cleanup(struct spi_device *spi)
933 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
935 if (gpio_is_valid(spi->cs_gpio)) {
936 gpio_free(spi->cs_gpio);
937 if (spi->dev.of_node)
940 /* On non-DT platforms, the SPI core sets
941 * spi->cs_gpio to -ENOENT and .setup()
942 * overrides it with the GPIO pin value
943 * passed using platform data.
945 spi->cs_gpio = -ENOENT;
949 spi_set_ctldata(spi, NULL);
952 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
954 struct s3c64xx_spi_driver_data *sdd = data;
955 struct spi_master *spi = sdd->master;
956 unsigned int val, clr = 0;
958 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
960 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
961 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
962 dev_err(&spi->dev, "RX overrun\n");
964 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
965 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
966 dev_err(&spi->dev, "RX underrun\n");
968 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
969 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
970 dev_err(&spi->dev, "TX overrun\n");
972 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
973 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
974 dev_err(&spi->dev, "TX underrun\n");
977 /* Clear the pending irq by setting and then clearing it */
978 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
979 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
984 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd)
986 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
987 void __iomem *regs = sdd->regs;
993 writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
994 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
995 writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG);
997 /* Disable Interrupts - we use Polling if not DMA mode */
998 writel(0, regs + S3C64XX_SPI_INT_EN);
1000 if (!sdd->port_conf->clk_from_cmu)
1001 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
1002 regs + S3C64XX_SPI_CLK_CFG);
1003 writel(0, regs + S3C64XX_SPI_MODE_CFG);
1004 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1006 /* Clear any irq pending bits, should set and clear the bits */
1007 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1008 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1009 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1010 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1011 writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1012 writel(0, regs + S3C64XX_SPI_PENDING_CLR);
1014 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1016 val = readl(regs + S3C64XX_SPI_MODE_CFG);
1017 val &= ~S3C64XX_SPI_MODE_4BURST;
1018 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1019 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1020 writel(val, regs + S3C64XX_SPI_MODE_CFG);
1022 s3c64xx_flush_fifo(sdd);
1026 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1028 struct s3c64xx_spi_info *sci;
1031 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1033 return ERR_PTR(-ENOMEM);
1035 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1036 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1037 sci->src_clk_nr = 0;
1039 sci->src_clk_nr = temp;
1042 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1043 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1049 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
1054 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1056 return dev_get_platdata(dev);
1060 static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1061 struct platform_device *pdev)
1064 if (pdev->dev.of_node)
1065 return of_device_get_match_data(&pdev->dev);
1067 return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data;
1070 static int s3c64xx_spi_probe(struct platform_device *pdev)
1072 struct resource *mem_res;
1073 struct s3c64xx_spi_driver_data *sdd;
1074 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1075 struct spi_master *master;
1079 if (!sci && pdev->dev.of_node) {
1080 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1082 return PTR_ERR(sci);
1086 dev_err(&pdev->dev, "platform_data missing!\n");
1090 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1091 if (mem_res == NULL) {
1092 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1096 irq = platform_get_irq(pdev, 0);
1098 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1102 master = spi_alloc_master(&pdev->dev,
1103 sizeof(struct s3c64xx_spi_driver_data));
1104 if (master == NULL) {
1105 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1109 platform_set_drvdata(pdev, master);
1111 sdd = spi_master_get_devdata(master);
1112 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1113 sdd->master = master;
1114 sdd->cntrlr_info = sci;
1116 sdd->sfr_start = mem_res->start;
1117 if (pdev->dev.of_node) {
1118 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1120 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1122 goto err_deref_master;
1126 sdd->port_id = pdev->id;
1131 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1132 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1134 master->dev.of_node = pdev->dev.of_node;
1135 master->bus_num = sdd->port_id;
1136 master->setup = s3c64xx_spi_setup;
1137 master->cleanup = s3c64xx_spi_cleanup;
1138 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1139 master->prepare_message = s3c64xx_spi_prepare_message;
1140 master->transfer_one = s3c64xx_spi_transfer_one;
1141 master->max_transfer_size = s3c64xx_spi_max_transfer_size;
1142 master->num_chipselect = sci->num_cs;
1143 master->dma_alignment = 8;
1144 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1146 /* the spi->mode bits understood by this driver: */
1147 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1148 master->auto_runtime_pm = true;
1149 if (!is_polling(sdd))
1150 master->can_dma = s3c64xx_spi_can_dma;
1152 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1153 if (IS_ERR(sdd->regs)) {
1154 ret = PTR_ERR(sdd->regs);
1155 goto err_deref_master;
1158 if (sci->cfg_gpio && sci->cfg_gpio()) {
1159 dev_err(&pdev->dev, "Unable to config gpio\n");
1161 goto err_deref_master;
1165 sdd->clk = devm_clk_get(&pdev->dev, "spi");
1166 if (IS_ERR(sdd->clk)) {
1167 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1168 ret = PTR_ERR(sdd->clk);
1169 goto err_deref_master;
1172 ret = clk_prepare_enable(sdd->clk);
1174 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1175 goto err_deref_master;
1178 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1179 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1180 if (IS_ERR(sdd->src_clk)) {
1182 "Unable to acquire clock '%s'\n", clk_name);
1183 ret = PTR_ERR(sdd->src_clk);
1184 goto err_disable_clk;
1187 ret = clk_prepare_enable(sdd->src_clk);
1189 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1190 goto err_disable_clk;
1193 if (sdd->port_conf->clk_ioclk) {
1194 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk");
1195 if (IS_ERR(sdd->ioclk)) {
1196 dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n");
1197 ret = PTR_ERR(sdd->ioclk);
1198 goto err_disable_src_clk;
1201 ret = clk_prepare_enable(sdd->ioclk);
1203 dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n");
1204 goto err_disable_src_clk;
1208 if (!is_polling(sdd)) {
1209 /* Acquire DMA channels */
1210 sdd->rx_dma.ch = dma_request_chan(&pdev->dev, "rx");
1211 if (IS_ERR(sdd->rx_dma.ch)) {
1212 dev_err(&pdev->dev, "Failed to get RX DMA channel\n");
1213 ret = PTR_ERR(sdd->rx_dma.ch);
1214 goto err_disable_io_clk;
1216 sdd->tx_dma.ch = dma_request_chan(&pdev->dev, "tx");
1217 if (IS_ERR(sdd->tx_dma.ch)) {
1218 dev_err(&pdev->dev, "Failed to get TX DMA channel\n");
1219 ret = PTR_ERR(sdd->tx_dma.ch);
1220 goto err_release_rx_dma;
1224 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1225 pm_runtime_use_autosuspend(&pdev->dev);
1226 pm_runtime_set_active(&pdev->dev);
1227 pm_runtime_enable(&pdev->dev);
1228 pm_runtime_get_sync(&pdev->dev);
1230 /* Setup Deufult Mode */
1231 s3c64xx_spi_hwinit(sdd);
1233 spin_lock_init(&sdd->lock);
1234 init_completion(&sdd->xfer_completion);
1236 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1237 "spi-s3c64xx", sdd);
1239 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1244 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1245 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1246 sdd->regs + S3C64XX_SPI_INT_EN);
1248 ret = devm_spi_register_master(&pdev->dev, master);
1250 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1254 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1255 sdd->port_id, master->num_chipselect);
1256 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1257 mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1);
1259 pm_runtime_mark_last_busy(&pdev->dev);
1260 pm_runtime_put_autosuspend(&pdev->dev);
1265 pm_runtime_put_noidle(&pdev->dev);
1266 pm_runtime_disable(&pdev->dev);
1267 pm_runtime_set_suspended(&pdev->dev);
1269 if (!is_polling(sdd))
1270 dma_release_channel(sdd->tx_dma.ch);
1272 if (!is_polling(sdd))
1273 dma_release_channel(sdd->rx_dma.ch);
1275 clk_disable_unprepare(sdd->ioclk);
1276 err_disable_src_clk:
1277 clk_disable_unprepare(sdd->src_clk);
1279 clk_disable_unprepare(sdd->clk);
1281 spi_master_put(master);
1286 static int s3c64xx_spi_remove(struct platform_device *pdev)
1288 struct spi_master *master = platform_get_drvdata(pdev);
1289 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1291 pm_runtime_get_sync(&pdev->dev);
1293 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1295 if (!is_polling(sdd)) {
1296 dma_release_channel(sdd->rx_dma.ch);
1297 dma_release_channel(sdd->tx_dma.ch);
1300 clk_disable_unprepare(sdd->ioclk);
1302 clk_disable_unprepare(sdd->src_clk);
1304 clk_disable_unprepare(sdd->clk);
1306 pm_runtime_put_noidle(&pdev->dev);
1307 pm_runtime_disable(&pdev->dev);
1308 pm_runtime_set_suspended(&pdev->dev);
1313 #ifdef CONFIG_PM_SLEEP
1314 static int s3c64xx_spi_suspend(struct device *dev)
1316 struct spi_master *master = dev_get_drvdata(dev);
1317 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1319 int ret = spi_master_suspend(master);
1323 ret = pm_runtime_force_suspend(dev);
1327 sdd->cur_speed = 0; /* Output Clock is stopped */
1332 static int s3c64xx_spi_resume(struct device *dev)
1334 struct spi_master *master = dev_get_drvdata(dev);
1335 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1336 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1342 ret = pm_runtime_force_resume(dev);
1346 return spi_master_resume(master);
1348 #endif /* CONFIG_PM_SLEEP */
1351 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1353 struct spi_master *master = dev_get_drvdata(dev);
1354 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1356 clk_disable_unprepare(sdd->clk);
1357 clk_disable_unprepare(sdd->src_clk);
1358 clk_disable_unprepare(sdd->ioclk);
1363 static int s3c64xx_spi_runtime_resume(struct device *dev)
1365 struct spi_master *master = dev_get_drvdata(dev);
1366 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1369 if (sdd->port_conf->clk_ioclk) {
1370 ret = clk_prepare_enable(sdd->ioclk);
1375 ret = clk_prepare_enable(sdd->src_clk);
1377 goto err_disable_ioclk;
1379 ret = clk_prepare_enable(sdd->clk);
1381 goto err_disable_src_clk;
1383 s3c64xx_spi_hwinit(sdd);
1385 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1386 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1387 sdd->regs + S3C64XX_SPI_INT_EN);
1391 err_disable_src_clk:
1392 clk_disable_unprepare(sdd->src_clk);
1394 clk_disable_unprepare(sdd->ioclk);
1398 #endif /* CONFIG_PM */
1400 static const struct dev_pm_ops s3c64xx_spi_pm = {
1401 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1402 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1403 s3c64xx_spi_runtime_resume, NULL)
1406 static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1407 .fifo_lvl_mask = { 0x7f },
1408 .rx_lvl_offset = 13,
1413 static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1414 .fifo_lvl_mask = { 0x7f, 0x7F },
1415 .rx_lvl_offset = 13,
1419 static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1420 .fifo_lvl_mask = { 0x1ff, 0x7F },
1421 .rx_lvl_offset = 15,
1426 static const struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1427 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1428 .rx_lvl_offset = 15,
1431 .clk_from_cmu = true,
1432 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1435 static const struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1436 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1437 .rx_lvl_offset = 15,
1440 .clk_from_cmu = true,
1441 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1444 static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
1445 .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1446 .rx_lvl_offset = 15,
1449 .clk_from_cmu = true,
1451 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1454 static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1456 .name = "s3c2443-spi",
1457 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
1459 .name = "s3c6410-spi",
1460 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1465 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1466 { .compatible = "samsung,s3c2443-spi",
1467 .data = (void *)&s3c2443_spi_port_config,
1469 { .compatible = "samsung,s3c6410-spi",
1470 .data = (void *)&s3c6410_spi_port_config,
1472 { .compatible = "samsung,s5pv210-spi",
1473 .data = (void *)&s5pv210_spi_port_config,
1475 { .compatible = "samsung,exynos4210-spi",
1476 .data = (void *)&exynos4_spi_port_config,
1478 { .compatible = "samsung,exynos7-spi",
1479 .data = (void *)&exynos7_spi_port_config,
1481 { .compatible = "samsung,exynos5433-spi",
1482 .data = (void *)&exynos5433_spi_port_config,
1486 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1488 static struct platform_driver s3c64xx_spi_driver = {
1490 .name = "s3c64xx-spi",
1491 .pm = &s3c64xx_spi_pm,
1492 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1494 .probe = s3c64xx_spi_probe,
1495 .remove = s3c64xx_spi_remove,
1496 .id_table = s3c64xx_spi_driver_ids,
1498 MODULE_ALIAS("platform:s3c64xx-spi");
1500 module_platform_driver(s3c64xx_spi_driver);
1502 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1503 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1504 MODULE_LICENSE("GPL");