drivers/spi/spi-s3c64xx.c

   1 /*
   2  * Copyright (C) 2009 Samsung Electronics Ltd.
   3  *      Jaswinder Singh <jassi.brar@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/delay.h>
  20 #include <linux/clk.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/spi/spi.h>
  26 #include <linux/gpio.h>
  27 #include <linux/of.h>
  28 #include <linux/of_gpio.h>
  29
  30 #include <linux/platform_data/spi-s3c64xx.h>
  31
  32 #define MAX_SPI_PORTS           6
  33 #define S3C64XX_SPI_QUIRK_POLL          (1 << 0)
  34 #define S3C64XX_SPI_QUIRK_CS_AUTO       (1 << 1)
  35 #define AUTOSUSPEND_TIMEOUT     2000
  36
  37 /* Registers and bit-fields */
  38
  39 #define S3C64XX_SPI_CH_CFG              0x00
  40 #define S3C64XX_SPI_CLK_CFG             0x04
  41 #define S3C64XX_SPI_MODE_CFG    0x08
  42 #define S3C64XX_SPI_SLAVE_SEL   0x0C
  43 #define S3C64XX_SPI_INT_EN              0x10
  44 #define S3C64XX_SPI_STATUS              0x14
  45 #define S3C64XX_SPI_TX_DATA             0x18
  46 #define S3C64XX_SPI_RX_DATA             0x1C
  47 #define S3C64XX_SPI_PACKET_CNT  0x20
  48 #define S3C64XX_SPI_PENDING_CLR 0x24
  49 #define S3C64XX_SPI_SWAP_CFG    0x28
  50 #define S3C64XX_SPI_FB_CLK              0x2C
  51
  52 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
  53 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
  54 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
  55 #define S3C64XX_SPI_CPOL_L              (1<<3)
  56 #define S3C64XX_SPI_CPHA_B              (1<<2)
  57 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
  58 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
  59
  60 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
  61 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
  62 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
  63 #define S3C64XX_SPI_PSR_MASK            0xff
  64
  65 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
  66 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
  67 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
  68 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
  69 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
  70 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
  71 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
  72 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
  73 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
  74 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
  75 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
  76
  77 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
  78 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
  79 #define S3C64XX_SPI_SLAVE_NSC_CNT_2             (2<<4)
  80
  81 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
  82 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
  83 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
  84 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
  85 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
  86 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
  87 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
  88
  89 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
  90 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
  91 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
  92 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
  93 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
  94 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
  95
  96 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
  97
  98 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
  99 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
 100 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
 101 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
 102 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
 103
 104 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
 105 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
 106 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
 107 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
 108 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
 109 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
 110 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
 111 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
 112
 113 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
 114
 115 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
 116 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
 117                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
 118 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
 119 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
 120                                         FIFO_LVL_MASK(i))
 121
 122 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
 123 #define S3C64XX_SPI_TRAILCNT_OFF        19
 124
 125 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
 126
 127 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 128 #define is_polling(x)   (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
 129
 130 #define RXBUSY    (1<<2)
 131 #define TXBUSY    (1<<3)
 132
 133 struct s3c64xx_spi_dma_data {
 134         struct dma_chan *ch;
 135         enum dma_transfer_direction direction;
 136 };
 137
 138 /**
 139  * struct s3c64xx_spi_info - SPI Controller hardware info
 140  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
 141  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
 142  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
 143  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
 144  * @clk_from_cmu: True, if the controller does not include a clock mux and
 145  *      prescaler unit.
 146  *
 147  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
 148  * differ in some aspects such as the size of the fifo and spi bus clock
 149  * setup. Such differences are specified to the driver using this structure
 150  * which is provided as driver data to the driver.
 151  */
 152 struct s3c64xx_spi_port_config {
 153         int     fifo_lvl_mask[MAX_SPI_PORTS];
 154         int     rx_lvl_offset;
 155         int     tx_st_done;
 156         int     quirks;
 157         bool    high_speed;
 158         bool    clk_from_cmu;
 159         bool    clk_ioclk;
 160 };
 161
 162 /**
 163  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 164  * @clk: Pointer to the spi clock.
 165  * @src_clk: Pointer to the clock used to generate SPI signals.
 166  * @ioclk: Pointer to the i/o clock between master and slave
 167  * @master: Pointer to the SPI Protocol master.
 168  * @cntrlr_info: Platform specific data for the controller this driver manages.
 169  * @lock: Controller specific lock.
 170  * @state: Set of FLAGS to indicate status.
 171  * @rx_dmach: Controller's DMA channel for Rx.
 172  * @tx_dmach: Controller's DMA channel for Tx.
 173  * @sfr_start: BUS address of SPI controller regs.
 174  * @regs: Pointer to ioremap'ed controller registers.
 175  * @irq: interrupt
 176  * @xfer_completion: To indicate completion of xfer task.
 177  * @cur_mode: Stores the active configuration of the controller.
 178  * @cur_bpw: Stores the active bits per word settings.
 179  * @cur_speed: Stores the active xfer clock speed.
 180  */
 181 struct s3c64xx_spi_driver_data {
 182         void __iomem                    *regs;
 183         struct clk                      *clk;
 184         struct clk                      *src_clk;
 185         struct clk                      *ioclk;
 186         struct platform_device          *pdev;
 187         struct spi_master               *master;
 188         struct s3c64xx_spi_info  *cntrlr_info;
 189         spinlock_t                      lock;
 190         unsigned long                   sfr_start;
 191         struct completion               xfer_completion;
 192         unsigned                        state;
 193         unsigned                        cur_mode, cur_bpw;
 194         unsigned                        cur_speed;
 195         struct s3c64xx_spi_dma_data     rx_dma;
 196         struct s3c64xx_spi_dma_data     tx_dma;
 197         struct s3c64xx_spi_port_config  *port_conf;
 198         unsigned int                    port_id;
 199 };
 200
 201 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 202 {
 203         void __iomem *regs = sdd->regs;
 204         unsigned long loops;
 205         u32 val;
 206
 207         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 208
 209         val = readl(regs + S3C64XX_SPI_CH_CFG);
 210         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
 211         writel(val, regs + S3C64XX_SPI_CH_CFG);
 212
 213         val = readl(regs + S3C64XX_SPI_CH_CFG);
 214         val |= S3C64XX_SPI_CH_SW_RST;
 215         val &= ~S3C64XX_SPI_CH_HS_EN;
 216         writel(val, regs + S3C64XX_SPI_CH_CFG);
 217
 218         /* Flush TxFIFO*/
 219         loops = msecs_to_loops(1);
 220         do {
 221                 val = readl(regs + S3C64XX_SPI_STATUS);
 222         } while (TX_FIFO_LVL(val, sdd) && loops--);
 223
 224         if (loops == 0)
 225                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
 226
 227         /* Flush RxFIFO*/
 228         loops = msecs_to_loops(1);
 229         do {
 230                 val = readl(regs + S3C64XX_SPI_STATUS);
 231                 if (RX_FIFO_LVL(val, sdd))
 232                         readl(regs + S3C64XX_SPI_RX_DATA);
 233                 else
 234                         break;
 235         } while (loops--);
 236
 237         if (loops == 0)
 238                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
 239
 240         val = readl(regs + S3C64XX_SPI_CH_CFG);
 241         val &= ~S3C64XX_SPI_CH_SW_RST;
 242         writel(val, regs + S3C64XX_SPI_CH_CFG);
 243
 244         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 245         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 246         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 247 }
 248
 249 static void s3c64xx_spi_dmacb(void *data)
 250 {
 251         struct s3c64xx_spi_driver_data *sdd;
 252         struct s3c64xx_spi_dma_data *dma = data;
 253         unsigned long flags;
 254
 255         if (dma->direction == DMA_DEV_TO_MEM)
 256                 sdd = container_of(data,
 257                         struct s3c64xx_spi_driver_data, rx_dma);
 258         else
 259                 sdd = container_of(data,
 260                         struct s3c64xx_spi_driver_data, tx_dma);
 261
 262         spin_lock_irqsave(&sdd->lock, flags);
 263
 264         if (dma->direction == DMA_DEV_TO_MEM) {
 265                 sdd->state &= ~RXBUSY;
 266                 if (!(sdd->state & TXBUSY))
 267                         complete(&sdd->xfer_completion);
 268         } else {
 269                 sdd->state &= ~TXBUSY;
 270                 if (!(sdd->state & RXBUSY))
 271                         complete(&sdd->xfer_completion);
 272         }
 273
 274         spin_unlock_irqrestore(&sdd->lock, flags);
 275 }
 276
 277 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
 278                         struct sg_table *sgt)
 279 {
 280         struct s3c64xx_spi_driver_data *sdd;
 281         struct dma_slave_config config;
 282         struct dma_async_tx_descriptor *desc;
 283
 284         memset(&config, 0, sizeof(config));
 285
 286         if (dma->direction == DMA_DEV_TO_MEM) {
 287                 sdd = container_of((void *)dma,
 288                         struct s3c64xx_spi_driver_data, rx_dma);
 289                 config.direction = dma->direction;
 290                 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 291                 config.src_addr_width = sdd->cur_bpw / 8;
 292                 config.src_maxburst = 1;
 293                 dmaengine_slave_config(dma->ch, &config);
 294         } else {
 295                 sdd = container_of((void *)dma,
 296                         struct s3c64xx_spi_driver_data, tx_dma);
 297                 config.direction = dma->direction;
 298                 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 299                 config.dst_addr_width = sdd->cur_bpw / 8;
 300                 config.dst_maxburst = 1;
 301                 dmaengine_slave_config(dma->ch, &config);
 302         }
 303
 304         desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
 305                                        dma->direction, DMA_PREP_INTERRUPT);
 306
 307         desc->callback = s3c64xx_spi_dmacb;
 308         desc->callback_param = dma;
 309
 310         dmaengine_submit(desc);
 311         dma_async_issue_pending(dma->ch);
 312 }
 313
 314 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
 315 {
 316         struct s3c64xx_spi_driver_data *sdd =
 317                                         spi_master_get_devdata(spi->master);
 318
 319         if (sdd->cntrlr_info->no_cs)
 320                 return;
 321
 322         if (enable) {
 323                 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
 324                         writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 325                 } else {
 326                         u32 ssel = readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 327
 328                         ssel |= (S3C64XX_SPI_SLAVE_AUTO |
 329                                                 S3C64XX_SPI_SLAVE_NSC_CNT_2);
 330                         writel(ssel, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 331                 }
 332         } else {
 333                 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
 334                         writel(S3C64XX_SPI_SLAVE_SIG_INACT,
 335                                sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 336         }
 337 }
 338
 339 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 340 {
 341         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 342
 343         if (is_polling(sdd))
 344                 return 0;
 345
 346         spi->dma_rx = sdd->rx_dma.ch;
 347         spi->dma_tx = sdd->tx_dma.ch;
 348
 349         return 0;
 350 }
 351
 352 static bool s3c64xx_spi_can_dma(struct spi_master *master,
 353                                 struct spi_device *spi,
 354                                 struct spi_transfer *xfer)
 355 {
 356         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 357
 358         return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
 359 }
 360
 361 static void s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 362                                     struct spi_transfer *xfer, int dma_mode)
 363 {
 364         void __iomem *regs = sdd->regs;
 365         u32 modecfg, chcfg;
 366
 367         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
 368         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 369
 370         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
 371         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
 372
 373         if (dma_mode) {
 374                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
 375         } else {
 376                 /* Always shift in data in FIFO, even if xfer is Tx only,
 377                  * this helps setting PCKT_CNT value for generating clocks
 378                  * as exactly needed.
 379                  */
 380                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 381                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 382                                         | S3C64XX_SPI_PACKET_CNT_EN,
 383                                         regs + S3C64XX_SPI_PACKET_CNT);
 384         }
 385
 386         if (xfer->tx_buf != NULL) {
 387                 sdd->state |= TXBUSY;
 388                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
 389                 if (dma_mode) {
 390                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
 391                         prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
 392                 } else {
 393                         switch (sdd->cur_bpw) {
 394                         case 32:
 395                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
 396                                         xfer->tx_buf, xfer->len / 4);
 397                                 break;
 398                         case 16:
 399                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
 400                                         xfer->tx_buf, xfer->len / 2);
 401                                 break;
 402                         default:
 403                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
 404                                         xfer->tx_buf, xfer->len);
 405                                 break;
 406                         }
 407                 }
 408         }
 409
 410         if (xfer->rx_buf != NULL) {
 411                 sdd->state |= RXBUSY;
 412
 413                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
 414                                         && !(sdd->cur_mode & SPI_CPHA))
 415                         chcfg |= S3C64XX_SPI_CH_HS_EN;
 416
 417                 if (dma_mode) {
 418                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
 419                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 420                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 421                                         | S3C64XX_SPI_PACKET_CNT_EN,
 422                                         regs + S3C64XX_SPI_PACKET_CNT);
 423                         prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
 424                 }
 425         }
 426
 427         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
 428         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
 429 }
 430
 431 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
 432                                         int timeout_ms)
 433 {
 434         void __iomem *regs = sdd->regs;
 435         unsigned long val = 1;
 436         u32 status;
 437
 438         /* max fifo depth available */
 439         u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
 440
 441         if (timeout_ms)
 442                 val = msecs_to_loops(timeout_ms);
 443
 444         do {
 445                 status = readl(regs + S3C64XX_SPI_STATUS);
 446         } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
 447
 448         /* return the actual received data length */
 449         return RX_FIFO_LVL(status, sdd);
 450 }
 451
 452 static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
 453                         struct spi_transfer *xfer)
 454 {
 455         void __iomem *regs = sdd->regs;
 456         unsigned long val;
 457         u32 status;
 458         int ms;
 459
 460         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 461         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 462         ms += 10; /* some tolerance */
 463
 464         val = msecs_to_jiffies(ms) + 10;
 465         val = wait_for_completion_timeout(&sdd->xfer_completion, val);
 466
 467         /*
 468          * If the previous xfer was completed within timeout, then
 469          * proceed further else return -EIO.
 470          * DmaTx returns after simply writing data in the FIFO,
 471          * w/o waiting for real transmission on the bus to finish.
 472          * DmaRx returns only after Dma read data from FIFO which
 473          * needs bus transmission to finish, so we don't worry if
 474          * Xfer involved Rx(with or without Tx).
 475          */
 476         if (val && !xfer->rx_buf) {
 477                 val = msecs_to_loops(10);
 478                 status = readl(regs + S3C64XX_SPI_STATUS);
 479                 while ((TX_FIFO_LVL(status, sdd)
 480                         || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
 481                        && --val) {
 482                         cpu_relax();
 483                         status = readl(regs + S3C64XX_SPI_STATUS);
 484                 }
 485
 486         }
 487
 488         /* If timed out while checking rx/tx status return error */
 489         if (!val)
 490                 return -EIO;
 491
 492         return 0;
 493 }
 494
 495 static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
 496                         struct spi_transfer *xfer)
 497 {
 498         void __iomem *regs = sdd->regs;
 499         unsigned long val;
 500         u32 status;
 501         int loops;
 502         u32 cpy_len;
 503         u8 *buf;
 504         int ms;
 505
 506         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 507         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 508         ms += 10; /* some tolerance */
 509
 510         val = msecs_to_loops(ms);
 511         do {
 512                 status = readl(regs + S3C64XX_SPI_STATUS);
 513         } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
 514
 515         if (!val)
 516                 return -EIO;
 517
 518         /* If it was only Tx */
 519         if (!xfer->rx_buf) {
 520                 sdd->state &= ~TXBUSY;
 521                 return 0;
 522         }
 523
 524         /*
 525          * If the receive length is bigger than the controller fifo
 526          * size, calculate the loops and read the fifo as many times.
 527          * loops = length / max fifo size (calculated by using the
 528          * fifo mask).
 529          * For any size less than the fifo size the below code is
 530          * executed atleast once.
 531          */
 532         loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
 533         buf = xfer->rx_buf;
 534         do {
 535                 /* wait for data to be received in the fifo */
 536                 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
 537                                                        (loops ? ms : 0));
 538
 539                 switch (sdd->cur_bpw) {
 540                 case 32:
 541                         ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
 542                                      buf, cpy_len / 4);
 543                         break;
 544                 case 16:
 545                         ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
 546                                      buf, cpy_len / 2);
 547                         break;
 548                 default:
 549                         ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
 550                                     buf, cpy_len);
 551                         break;
 552                 }
 553
 554                 buf = buf + cpy_len;
 555         } while (loops--);
 556         sdd->state &= ~RXBUSY;
 557
 558         return 0;
 559 }
 560
 561 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 562 {
 563         void __iomem *regs = sdd->regs;
 564         u32 val;
 565
 566         /* Disable Clock */
 567         if (!sdd->port_conf->clk_from_cmu) {
 568                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 569                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 570                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 571         }
 572
 573         /* Set Polarity and Phase */
 574         val = readl(regs + S3C64XX_SPI_CH_CFG);
 575         val &= ~(S3C64XX_SPI_CH_SLAVE |
 576                         S3C64XX_SPI_CPOL_L |
 577                         S3C64XX_SPI_CPHA_B);
 578
 579         if (sdd->cur_mode & SPI_CPOL)
 580                 val |= S3C64XX_SPI_CPOL_L;
 581
 582         if (sdd->cur_mode & SPI_CPHA)
 583                 val |= S3C64XX_SPI_CPHA_B;
 584
 585         writel(val, regs + S3C64XX_SPI_CH_CFG);
 586
 587         /* Set Channel & DMA Mode */
 588         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 589         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
 590                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
 591
 592         switch (sdd->cur_bpw) {
 593         case 32:
 594                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
 595                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
 596                 break;
 597         case 16:
 598                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
 599                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
 600                 break;
 601         default:
 602                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
 603                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
 604                 break;
 605         }
 606
 607         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 608
 609         if (sdd->port_conf->clk_from_cmu) {
 610                 /* The src_clk clock is divided internally by 2 */
 611                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
 612         } else {
 613                 /* Configure Clock */
 614                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 615                 val &= ~S3C64XX_SPI_PSR_MASK;
 616                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
 617                                 & S3C64XX_SPI_PSR_MASK);
 618                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 619
 620                 /* Enable Clock */
 621                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 622                 val |= S3C64XX_SPI_ENCLK_ENABLE;
 623                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 624         }
 625 }
 626
 627 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
 628
 629 static int s3c64xx_spi_prepare_message(struct spi_master *master,
 630                                        struct spi_message *msg)
 631 {
 632         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 633         struct spi_device *spi = msg->spi;
 634         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 635
 636         /* Configure feedback delay */
 637         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
 638
 639         return 0;
 640 }
 641
 642 static int s3c64xx_spi_transfer_one(struct spi_master *master,
 643                                     struct spi_device *spi,
 644                                     struct spi_transfer *xfer)
 645 {
 646         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 647         int status;
 648         u32 speed;
 649         u8 bpw;
 650         unsigned long flags;
 651         int use_dma;
 652
 653         reinit_completion(&sdd->xfer_completion);
 654
 655         /* Only BPW and Speed may change across transfers */
 656         bpw = xfer->bits_per_word;
 657         speed = xfer->speed_hz;
 658
 659         if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
 660                 sdd->cur_bpw = bpw;
 661                 sdd->cur_speed = speed;
 662                 sdd->cur_mode = spi->mode;
 663                 s3c64xx_spi_config(sdd);
 664         }
 665
 666         /* Polling method for xfers not bigger than FIFO capacity */
 667         use_dma = 0;
 668         if (!is_polling(sdd) &&
 669             (sdd->rx_dma.ch && sdd->tx_dma.ch &&
 670              (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
 671                 use_dma = 1;
 672
 673         spin_lock_irqsave(&sdd->lock, flags);
 674
 675         /* Pending only which is to be done */
 676         sdd->state &= ~RXBUSY;
 677         sdd->state &= ~TXBUSY;
 678
 679         s3c64xx_enable_datapath(sdd, xfer, use_dma);
 680
 681         /* Start the signals */
 682         s3c64xx_spi_set_cs(spi, true);
 683
 684         spin_unlock_irqrestore(&sdd->lock, flags);
 685
 686         if (use_dma)
 687                 status = wait_for_dma(sdd, xfer);
 688         else
 689                 status = wait_for_pio(sdd, xfer);
 690
 691         if (status) {
 692                 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
 693                         xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
 694                         (sdd->state & RXBUSY) ? 'f' : 'p',
 695                         (sdd->state & TXBUSY) ? 'f' : 'p',
 696                         xfer->len);
 697
 698                 if (use_dma) {
 699                         if (xfer->tx_buf != NULL
 700                             && (sdd->state & TXBUSY))
 701                                 dmaengine_terminate_all(sdd->tx_dma.ch);
 702                         if (xfer->rx_buf != NULL
 703                             && (sdd->state & RXBUSY))
 704                                 dmaengine_terminate_all(sdd->rx_dma.ch);
 705                 }
 706         } else {
 707                 flush_fifo(sdd);
 708         }
 709
 710         return status;
 711 }
 712
 713 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
 714                                 struct spi_device *spi)
 715 {
 716         struct s3c64xx_spi_csinfo *cs;
 717         struct device_node *slave_np, *data_np = NULL;
 718         u32 fb_delay = 0;
 719
 720         slave_np = spi->dev.of_node;
 721         if (!slave_np) {
 722                 dev_err(&spi->dev, "device node not found\n");
 723                 return ERR_PTR(-EINVAL);
 724         }
 725
 726         data_np = of_get_child_by_name(slave_np, "controller-data");
 727         if (!data_np) {
 728                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
 729                 return ERR_PTR(-EINVAL);
 730         }
 731
 732         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 733         if (!cs) {
 734                 of_node_put(data_np);
 735                 return ERR_PTR(-ENOMEM);
 736         }
 737
 738         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
 739         cs->fb_delay = fb_delay;
 740         of_node_put(data_np);
 741         return cs;
 742 }
 743
 744 /*
 745  * Here we only check the validity of requested configuration
 746  * and save the configuration in a local data-structure.
 747  * The controller is actually configured only just before we
 748  * get a message to transfer.
 749  */
 750 static int s3c64xx_spi_setup(struct spi_device *spi)
 751 {
 752         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 753         struct s3c64xx_spi_driver_data *sdd;
 754         struct s3c64xx_spi_info *sci;
 755         int err;
 756
 757         sdd = spi_master_get_devdata(spi->master);
 758         if (spi->dev.of_node) {
 759                 cs = s3c64xx_get_slave_ctrldata(spi);
 760                 spi->controller_data = cs;
 761         } else if (cs) {
 762                 /* On non-DT platforms the SPI core will set spi->cs_gpio
 763                  * to -ENOENT. The GPIO pin used to drive the chip select
 764                  * is defined by using platform data so spi->cs_gpio value
 765                  * has to be override to have the proper GPIO pin number.
 766                  */
 767                 spi->cs_gpio = cs->line;
 768         }
 769
 770         if (IS_ERR_OR_NULL(cs)) {
 771                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
 772                 return -ENODEV;
 773         }
 774
 775         if (!spi_get_ctldata(spi)) {
 776                 if (gpio_is_valid(spi->cs_gpio)) {
 777                         err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
 778                                                dev_name(&spi->dev));
 779                         if (err) {
 780                                 dev_err(&spi->dev,
 781                                         "Failed to get /CS gpio [%d]: %d\n",
 782                                         spi->cs_gpio, err);
 783                                 goto err_gpio_req;
 784                         }
 785                 }
 786
 787                 spi_set_ctldata(spi, cs);
 788         }
 789
 790         sci = sdd->cntrlr_info;
 791
 792         pm_runtime_get_sync(&sdd->pdev->dev);
 793
 794         /* Check if we can provide the requested rate */
 795         if (!sdd->port_conf->clk_from_cmu) {
 796                 u32 psr, speed;
 797
 798                 /* Max possible */
 799                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
 800
 801                 if (spi->max_speed_hz > speed)
 802                         spi->max_speed_hz = speed;
 803
 804                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
 805                 psr &= S3C64XX_SPI_PSR_MASK;
 806                 if (psr == S3C64XX_SPI_PSR_MASK)
 807                         psr--;
 808
 809                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 810                 if (spi->max_speed_hz < speed) {
 811                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
 812                                 psr++;
 813                         } else {
 814                                 err = -EINVAL;
 815                                 goto setup_exit;
 816                         }
 817                 }
 818
 819                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 820                 if (spi->max_speed_hz >= speed) {
 821                         spi->max_speed_hz = speed;
 822                 } else {
 823                         dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
 824                                 spi->max_speed_hz);
 825                         err = -EINVAL;
 826                         goto setup_exit;
 827                 }
 828         }
 829
 830         pm_runtime_mark_last_busy(&sdd->pdev->dev);
 831         pm_runtime_put_autosuspend(&sdd->pdev->dev);
 832         s3c64xx_spi_set_cs(spi, false);
 833
 834         return 0;
 835
 836 setup_exit:
 837         pm_runtime_mark_last_busy(&sdd->pdev->dev);
 838         pm_runtime_put_autosuspend(&sdd->pdev->dev);
 839         /* setup() returns with device de-selected */
 840         s3c64xx_spi_set_cs(spi, false);
 841
 842         if (gpio_is_valid(spi->cs_gpio))
 843                 gpio_free(spi->cs_gpio);
 844         spi_set_ctldata(spi, NULL);
 845
 846 err_gpio_req:
 847         if (spi->dev.of_node)
 848                 kfree(cs);
 849
 850         return err;
 851 }
 852
 853 static void s3c64xx_spi_cleanup(struct spi_device *spi)
 854 {
 855         struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
 856
 857         if (gpio_is_valid(spi->cs_gpio)) {
 858                 gpio_free(spi->cs_gpio);
 859                 if (spi->dev.of_node)
 860                         kfree(cs);
 861                 else {
 862                         /* On non-DT platforms, the SPI core sets
 863                          * spi->cs_gpio to -ENOENT and .setup()
 864                          * overrides it with the GPIO pin value
 865                          * passed using platform data.
 866                          */
 867                         spi->cs_gpio = -ENOENT;
 868                 }
 869         }
 870
 871         spi_set_ctldata(spi, NULL);
 872 }
 873
 874 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
 875 {
 876         struct s3c64xx_spi_driver_data *sdd = data;
 877         struct spi_master *spi = sdd->master;
 878         unsigned int val, clr = 0;
 879
 880         val = readl(sdd->regs + S3C64XX_SPI_STATUS);
 881
 882         if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
 883                 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
 884                 dev_err(&spi->dev, "RX overrun\n");
 885         }
 886         if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
 887                 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
 888                 dev_err(&spi->dev, "RX underrun\n");
 889         }
 890         if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
 891                 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
 892                 dev_err(&spi->dev, "TX overrun\n");
 893         }
 894         if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
 895                 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
 896                 dev_err(&spi->dev, "TX underrun\n");
 897         }
 898
 899         /* Clear the pending irq by setting and then clearing it */
 900         writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
 901         writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
 902
 903         return IRQ_HANDLED;
 904 }
 905
 906 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd)
 907 {
 908         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 909         void __iomem *regs = sdd->regs;
 910         unsigned int val;
 911
 912         sdd->cur_speed = 0;
 913
 914         if (sci->no_cs)
 915                 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 916         else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
 917                 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 918
 919         /* Disable Interrupts - we use Polling if not DMA mode */
 920         writel(0, regs + S3C64XX_SPI_INT_EN);
 921
 922         if (!sdd->port_conf->clk_from_cmu)
 923                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
 924                                 regs + S3C64XX_SPI_CLK_CFG);
 925         writel(0, regs + S3C64XX_SPI_MODE_CFG);
 926         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 927
 928         /* Clear any irq pending bits, should set and clear the bits */
 929         val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
 930                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
 931                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
 932                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
 933         writel(val, regs + S3C64XX_SPI_PENDING_CLR);
 934         writel(0, regs + S3C64XX_SPI_PENDING_CLR);
 935
 936         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
 937
 938         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 939         val &= ~S3C64XX_SPI_MODE_4BURST;
 940         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
 941         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
 942         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 943
 944         flush_fifo(sdd);
 945 }
 946
 947 #ifdef CONFIG_OF
 948 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
 949 {
 950         struct s3c64xx_spi_info *sci;
 951         u32 temp;
 952
 953         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
 954         if (!sci)
 955                 return ERR_PTR(-ENOMEM);
 956
 957         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
 958                 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
 959                 sci->src_clk_nr = 0;
 960         } else {
 961                 sci->src_clk_nr = temp;
 962         }
 963
 964         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
 965                 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
 966                 sci->num_cs = 1;
 967         } else {
 968                 sci->num_cs = temp;
 969         }
 970
 971         sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
 972
 973         return sci;
 974 }
 975 #else
 976 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
 977 {
 978         return dev_get_platdata(dev);
 979 }
 980 #endif
 981
 982 static const struct of_device_id s3c64xx_spi_dt_match[];
 983
 984 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
 985                                                 struct platform_device *pdev)
 986 {
 987 #ifdef CONFIG_OF
 988         if (pdev->dev.of_node) {
 989                 const struct of_device_id *match;
 990                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
 991                 return (struct s3c64xx_spi_port_config *)match->data;
 992         }
 993 #endif
 994         return (struct s3c64xx_spi_port_config *)
 995                          platform_get_device_id(pdev)->driver_data;
 996 }
 997
 998 static int s3c64xx_spi_probe(struct platform_device *pdev)
 999 {
1000         struct resource *mem_res;
1001         struct s3c64xx_spi_driver_data *sdd;
1002         struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1003         struct spi_master *master;
1004         int ret, irq;
1005         char clk_name[16];
1006
1007         if (!sci && pdev->dev.of_node) {
1008                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1009                 if (IS_ERR(sci))
1010                         return PTR_ERR(sci);
1011         }
1012
1013         if (!sci) {
1014                 dev_err(&pdev->dev, "platform_data missing!\n");
1015                 return -ENODEV;
1016         }
1017
1018         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1019         if (mem_res == NULL) {
1020                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1021                 return -ENXIO;
1022         }
1023
1024         irq = platform_get_irq(pdev, 0);
1025         if (irq < 0) {
1026                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1027                 return irq;
1028         }
1029
1030         master = spi_alloc_master(&pdev->dev,
1031                                 sizeof(struct s3c64xx_spi_driver_data));
1032         if (master == NULL) {
1033                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1034                 return -ENOMEM;
1035         }
1036
1037         platform_set_drvdata(pdev, master);
1038
1039         sdd = spi_master_get_devdata(master);
1040         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1041         sdd->master = master;
1042         sdd->cntrlr_info = sci;
1043         sdd->pdev = pdev;
1044         sdd->sfr_start = mem_res->start;
1045         if (pdev->dev.of_node) {
1046                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1047                 if (ret < 0) {
1048                         dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1049                                 ret);
1050                         goto err_deref_master;
1051                 }
1052                 sdd->port_id = ret;
1053         } else {
1054                 sdd->port_id = pdev->id;
1055         }
1056
1057         sdd->cur_bpw = 8;
1058
1059         sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1060         sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1061
1062         master->dev.of_node = pdev->dev.of_node;
1063         master->bus_num = sdd->port_id;
1064         master->setup = s3c64xx_spi_setup;
1065         master->cleanup = s3c64xx_spi_cleanup;
1066         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1067         master->prepare_message = s3c64xx_spi_prepare_message;
1068         master->transfer_one = s3c64xx_spi_transfer_one;
1069         master->num_chipselect = sci->num_cs;
1070         master->dma_alignment = 8;
1071         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1072                                         SPI_BPW_MASK(8);
1073         /* the spi->mode bits understood by this driver: */
1074         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1075         master->auto_runtime_pm = true;
1076         if (!is_polling(sdd))
1077                 master->can_dma = s3c64xx_spi_can_dma;
1078
1079         sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1080         if (IS_ERR(sdd->regs)) {
1081                 ret = PTR_ERR(sdd->regs);
1082                 goto err_deref_master;
1083         }
1084
1085         if (sci->cfg_gpio && sci->cfg_gpio()) {
1086                 dev_err(&pdev->dev, "Unable to config gpio\n");
1087                 ret = -EBUSY;
1088                 goto err_deref_master;
1089         }
1090
1091         /* Setup clocks */
1092         sdd->clk = devm_clk_get(&pdev->dev, "spi");
1093         if (IS_ERR(sdd->clk)) {
1094                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1095                 ret = PTR_ERR(sdd->clk);
1096                 goto err_deref_master;
1097         }
1098
1099         ret = clk_prepare_enable(sdd->clk);
1100         if (ret) {
1101                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1102                 goto err_deref_master;
1103         }
1104
1105         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1106         sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1107         if (IS_ERR(sdd->src_clk)) {
1108                 dev_err(&pdev->dev,
1109                         "Unable to acquire clock '%s'\n", clk_name);
1110                 ret = PTR_ERR(sdd->src_clk);
1111                 goto err_disable_clk;
1112         }
1113
1114         ret = clk_prepare_enable(sdd->src_clk);
1115         if (ret) {
1116                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1117                 goto err_disable_clk;
1118         }
1119
1120         if (sdd->port_conf->clk_ioclk) {
1121                 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk");
1122                 if (IS_ERR(sdd->ioclk)) {
1123                         dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n");
1124                         ret = PTR_ERR(sdd->ioclk);
1125                         goto err_disable_src_clk;
1126                 }
1127
1128                 ret = clk_prepare_enable(sdd->ioclk);
1129                 if (ret) {
1130                         dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n");
1131                         goto err_disable_src_clk;
1132                 }
1133         }
1134
1135         if (!is_polling(sdd)) {
1136                 /* Acquire DMA channels */
1137                 sdd->rx_dma.ch = dma_request_slave_channel_reason(&pdev->dev,
1138                                                                   "rx");
1139                 if (IS_ERR(sdd->rx_dma.ch)) {
1140                         dev_err(&pdev->dev, "Failed to get RX DMA channel\n");
1141                         ret = PTR_ERR(sdd->rx_dma.ch);
1142                         goto err_disable_io_clk;
1143                 }
1144                 sdd->tx_dma.ch = dma_request_slave_channel_reason(&pdev->dev,
1145                                                                   "tx");
1146                 if (IS_ERR(sdd->tx_dma.ch)) {
1147                         dev_err(&pdev->dev, "Failed to get TX DMA channel\n");
1148                         ret = PTR_ERR(sdd->tx_dma.ch);
1149                         goto err_release_rx_dma;
1150                 }
1151         }
1152
1153         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1154         pm_runtime_use_autosuspend(&pdev->dev);
1155         pm_runtime_set_active(&pdev->dev);
1156         pm_runtime_enable(&pdev->dev);
1157         pm_runtime_get_sync(&pdev->dev);
1158
1159         /* Setup Deufult Mode */
1160         s3c64xx_spi_hwinit(sdd);
1161
1162         spin_lock_init(&sdd->lock);
1163         init_completion(&sdd->xfer_completion);
1164
1165         ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1166                                 "spi-s3c64xx", sdd);
1167         if (ret != 0) {
1168                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1169                         irq, ret);
1170                 goto err_pm_put;
1171         }
1172
1173         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1174                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1175                sdd->regs + S3C64XX_SPI_INT_EN);
1176
1177         ret = devm_spi_register_master(&pdev->dev, master);
1178         if (ret != 0) {
1179                 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1180                 goto err_pm_put;
1181         }
1182
1183         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1184                                         sdd->port_id, master->num_chipselect);
1185         dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1186                                         mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1);
1187
1188         pm_runtime_mark_last_busy(&pdev->dev);
1189         pm_runtime_put_autosuspend(&pdev->dev);
1190
1191         return 0;
1192
1193 err_pm_put:
1194         pm_runtime_put_noidle(&pdev->dev);
1195         pm_runtime_disable(&pdev->dev);
1196         pm_runtime_set_suspended(&pdev->dev);
1197
1198         if (!is_polling(sdd))
1199                 dma_release_channel(sdd->tx_dma.ch);
1200 err_release_rx_dma:
1201         if (!is_polling(sdd))
1202                 dma_release_channel(sdd->rx_dma.ch);
1203 err_disable_io_clk:
1204         clk_disable_unprepare(sdd->ioclk);
1205 err_disable_src_clk:
1206         clk_disable_unprepare(sdd->src_clk);
1207 err_disable_clk:
1208         clk_disable_unprepare(sdd->clk);
1209 err_deref_master:
1210         spi_master_put(master);
1211
1212         return ret;
1213 }
1214
1215 static int s3c64xx_spi_remove(struct platform_device *pdev)
1216 {
1217         struct spi_master *master = platform_get_drvdata(pdev);
1218         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1219
1220         pm_runtime_get_sync(&pdev->dev);
1221
1222         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1223
1224         if (!is_polling(sdd)) {
1225                 dma_release_channel(sdd->rx_dma.ch);
1226                 dma_release_channel(sdd->tx_dma.ch);
1227         }
1228
1229         clk_disable_unprepare(sdd->ioclk);
1230
1231         clk_disable_unprepare(sdd->src_clk);
1232
1233         clk_disable_unprepare(sdd->clk);
1234
1235         pm_runtime_put_noidle(&pdev->dev);
1236         pm_runtime_disable(&pdev->dev);
1237         pm_runtime_set_suspended(&pdev->dev);
1238
1239         return 0;
1240 }
1241
1242 #ifdef CONFIG_PM_SLEEP
1243 static int s3c64xx_spi_suspend(struct device *dev)
1244 {
1245         struct spi_master *master = dev_get_drvdata(dev);
1246         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1247
1248         int ret = spi_master_suspend(master);
1249         if (ret)
1250                 return ret;
1251
1252         ret = pm_runtime_force_suspend(dev);
1253         if (ret < 0)
1254                 return ret;
1255
1256         sdd->cur_speed = 0; /* Output Clock is stopped */
1257
1258         return 0;
1259 }
1260
1261 static int s3c64xx_spi_resume(struct device *dev)
1262 {
1263         struct spi_master *master = dev_get_drvdata(dev);
1264         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1265         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1266         int ret;
1267
1268         if (sci->cfg_gpio)
1269                 sci->cfg_gpio();
1270
1271         ret = pm_runtime_force_resume(dev);
1272         if (ret < 0)
1273                 return ret;
1274
1275         s3c64xx_spi_hwinit(sdd);
1276
1277         return spi_master_resume(master);
1278 }
1279 #endif /* CONFIG_PM_SLEEP */
1280
1281 #ifdef CONFIG_PM
1282 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1283 {
1284         struct spi_master *master = dev_get_drvdata(dev);
1285         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1286
1287         clk_disable_unprepare(sdd->clk);
1288         clk_disable_unprepare(sdd->src_clk);
1289         clk_disable_unprepare(sdd->ioclk);
1290
1291         return 0;
1292 }
1293
1294 static int s3c64xx_spi_runtime_resume(struct device *dev)
1295 {
1296         struct spi_master *master = dev_get_drvdata(dev);
1297         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1298         int ret;
1299
1300         if (sdd->port_conf->clk_ioclk) {
1301                 ret = clk_prepare_enable(sdd->ioclk);
1302                 if (ret != 0)
1303                         return ret;
1304         }
1305
1306         ret = clk_prepare_enable(sdd->src_clk);
1307         if (ret != 0)
1308                 goto err_disable_ioclk;
1309
1310         ret = clk_prepare_enable(sdd->clk);
1311         if (ret != 0)
1312                 goto err_disable_src_clk;
1313
1314         s3c64xx_spi_hwinit(sdd);
1315
1316         return 0;
1317
1318 err_disable_src_clk:
1319         clk_disable_unprepare(sdd->src_clk);
1320 err_disable_ioclk:
1321         clk_disable_unprepare(sdd->ioclk);
1322
1323         return ret;
1324 }
1325 #endif /* CONFIG_PM */
1326
1327 static const struct dev_pm_ops s3c64xx_spi_pm = {
1328         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1329         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1330                            s3c64xx_spi_runtime_resume, NULL)
1331 };
1332
1333 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1334         .fifo_lvl_mask  = { 0x7f },
1335         .rx_lvl_offset  = 13,
1336         .tx_st_done     = 21,
1337         .high_speed     = true,
1338 };
1339
1340 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1341         .fifo_lvl_mask  = { 0x7f, 0x7F },
1342         .rx_lvl_offset  = 13,
1343         .tx_st_done     = 21,
1344 };
1345
1346 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1347         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1348         .rx_lvl_offset  = 15,
1349         .tx_st_done     = 25,
1350         .high_speed     = true,
1351 };
1352
1353 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1354         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1355         .rx_lvl_offset  = 15,
1356         .tx_st_done     = 25,
1357         .high_speed     = true,
1358         .clk_from_cmu   = true,
1359 };
1360
1361 static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1362         .fifo_lvl_mask  = { 0x1ff },
1363         .rx_lvl_offset  = 15,
1364         .tx_st_done     = 25,
1365         .high_speed     = true,
1366         .clk_from_cmu   = true,
1367         .quirks         = S3C64XX_SPI_QUIRK_POLL,
1368 };
1369
1370 static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1371         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1372         .rx_lvl_offset  = 15,
1373         .tx_st_done     = 25,
1374         .high_speed     = true,
1375         .clk_from_cmu   = true,
1376         .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1377 };
1378
1379 static struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
1380         .fifo_lvl_mask  = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1381         .rx_lvl_offset  = 15,
1382         .tx_st_done     = 25,
1383         .high_speed     = true,
1384         .clk_from_cmu   = true,
1385         .clk_ioclk      = true,
1386         .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1387 };
1388
1389 static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1390         {
1391                 .name           = "s3c2443-spi",
1392                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1393         }, {
1394                 .name           = "s3c6410-spi",
1395                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1396         },
1397         { },
1398 };
1399
1400 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1401         { .compatible = "samsung,s3c2443-spi",
1402                         .data = (void *)&s3c2443_spi_port_config,
1403         },
1404         { .compatible = "samsung,s3c6410-spi",
1405                         .data = (void *)&s3c6410_spi_port_config,
1406         },
1407         { .compatible = "samsung,s5pv210-spi",
1408                         .data = (void *)&s5pv210_spi_port_config,
1409         },
1410         { .compatible = "samsung,exynos4210-spi",
1411                         .data = (void *)&exynos4_spi_port_config,
1412         },
1413         { .compatible = "samsung,exynos5440-spi",
1414                         .data = (void *)&exynos5440_spi_port_config,
1415         },
1416         { .compatible = "samsung,exynos7-spi",
1417                         .data = (void *)&exynos7_spi_port_config,
1418         },
1419         { .compatible = "samsung,exynos5433-spi",
1420                         .data = (void *)&exynos5433_spi_port_config,
1421         },
1422         { },
1423 };
1424 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1425
1426 static struct platform_driver s3c64xx_spi_driver = {
1427         .driver = {
1428                 .name   = "s3c64xx-spi",
1429                 .pm = &s3c64xx_spi_pm,
1430                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1431         },
1432         .probe = s3c64xx_spi_probe,
1433         .remove = s3c64xx_spi_remove,
1434         .id_table = s3c64xx_spi_driver_ids,
1435 };
1436 MODULE_ALIAS("platform:s3c64xx-spi");
1437
1438 module_platform_driver(s3c64xx_spi_driver);
1439
1440 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1441 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1442 MODULE_LICENSE("GPL");