drivers/spi/spi-s3c64xx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright (c) 2009 Samsung Electronics Co., Ltd.
   4 //      Jaswinder Singh <jassi.brar@samsung.com>
   5
   6 #include <linux/init.h>
   7 #include <linux/module.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/delay.h>
  10 #include <linux/clk.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/spi/spi.h>
  16 #include <linux/gpio.h>
  17 #include <linux/of.h>
  18 #include <linux/of_gpio.h>
  19
  20 #include <linux/platform_data/spi-s3c64xx.h>
  21
  22 #define MAX_SPI_PORTS           6
  23 #define S3C64XX_SPI_QUIRK_POLL          (1 << 0)
  24 #define S3C64XX_SPI_QUIRK_CS_AUTO       (1 << 1)
  25 #define AUTOSUSPEND_TIMEOUT     2000
  26
  27 /* Registers and bit-fields */
  28
  29 #define S3C64XX_SPI_CH_CFG              0x00
  30 #define S3C64XX_SPI_CLK_CFG             0x04
  31 #define S3C64XX_SPI_MODE_CFG            0x08
  32 #define S3C64XX_SPI_CS_REG              0x0C
  33 #define S3C64XX_SPI_INT_EN              0x10
  34 #define S3C64XX_SPI_STATUS              0x14
  35 #define S3C64XX_SPI_TX_DATA             0x18
  36 #define S3C64XX_SPI_RX_DATA             0x1C
  37 #define S3C64XX_SPI_PACKET_CNT          0x20
  38 #define S3C64XX_SPI_PENDING_CLR         0x24
  39 #define S3C64XX_SPI_SWAP_CFG            0x28
  40 #define S3C64XX_SPI_FB_CLK              0x2C
  41
  42 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
  43 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
  44 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
  45 #define S3C64XX_SPI_CPOL_L              (1<<3)
  46 #define S3C64XX_SPI_CPHA_B              (1<<2)
  47 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
  48 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
  49
  50 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
  51 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
  52 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
  53 #define S3C64XX_SPI_PSR_MASK            0xff
  54
  55 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
  56 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
  57 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
  58 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
  59 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
  60 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
  61 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
  62 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
  63 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
  64 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
  65 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
  66
  67 #define S3C64XX_SPI_CS_NSC_CNT_2                (2<<4)
  68 #define S3C64XX_SPI_CS_AUTO                     (1<<1)
  69 #define S3C64XX_SPI_CS_SIG_INACT                (1<<0)
  70
  71 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
  72 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
  73 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
  74 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
  75 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
  76 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
  77 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
  78
  79 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
  80 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR          (1<<4)
  81 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
  82 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR          (1<<2)
  83 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
  84 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
  85
  86 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
  87
  88 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
  89 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
  90 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
  91 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
  92 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
  93
  94 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
  95 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
  96 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
  97 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
  98 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
  99 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
 100 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
 101 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
 102
 103 #define S3C64XX_SPI_FBCLK_MSK                   (3<<0)
 104
 105 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
 106 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
 107                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
 108 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
 109 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
 110                                         FIFO_LVL_MASK(i))
 111
 112 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
 113 #define S3C64XX_SPI_TRAILCNT_OFF        19
 114
 115 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
 116
 117 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 118 #define is_polling(x)   (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
 119
 120 #define RXBUSY    (1<<2)
 121 #define TXBUSY    (1<<3)
 122
 123 struct s3c64xx_spi_dma_data {
 124         struct dma_chan *ch;
 125         dma_cookie_t cookie;
 126         enum dma_transfer_direction direction;
 127 };
 128
 129 /**
 130  * struct s3c64xx_spi_info - SPI Controller hardware info
 131  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
 132  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
 133  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
 134  * @quirks: Bitmask of known quirks
 135  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
 136  * @clk_from_cmu: True, if the controller does not include a clock mux and
 137  *      prescaler unit.
 138  * @clk_ioclk: True if clock is present on this device
 139  *
 140  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
 141  * differ in some aspects such as the size of the fifo and spi bus clock
 142  * setup. Such differences are specified to the driver using this structure
 143  * which is provided as driver data to the driver.
 144  */
 145 struct s3c64xx_spi_port_config {
 146         int     fifo_lvl_mask[MAX_SPI_PORTS];
 147         int     rx_lvl_offset;
 148         int     tx_st_done;
 149         int     quirks;
 150         bool    high_speed;
 151         bool    clk_from_cmu;
 152         bool    clk_ioclk;
 153 };
 154
 155 /**
 156  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 157  * @clk: Pointer to the spi clock.
 158  * @src_clk: Pointer to the clock used to generate SPI signals.
 159  * @ioclk: Pointer to the i/o clock between master and slave
 160  * @pdev: Pointer to device's platform device data
 161  * @master: Pointer to the SPI Protocol master.
 162  * @cntrlr_info: Platform specific data for the controller this driver manages.
 163  * @lock: Controller specific lock.
 164  * @state: Set of FLAGS to indicate status.
 165  * @rx_dmach: Controller's DMA channel for Rx.
 166  * @tx_dmach: Controller's DMA channel for Tx.
 167  * @sfr_start: BUS address of SPI controller regs.
 168  * @regs: Pointer to ioremap'ed controller registers.
 169  * @irq: interrupt
 170  * @xfer_completion: To indicate completion of xfer task.
 171  * @cur_mode: Stores the active configuration of the controller.
 172  * @cur_bpw: Stores the active bits per word settings.
 173  * @cur_speed: Current clock speed
 174  * @rx_dma: Local receive DMA data (e.g. chan and direction)
 175  * @tx_dma: Local transmit DMA data (e.g. chan and direction)
 176  * @port_conf: Local SPI port configuartion data
 177  * @port_id: Port identification number
 178  */
 179 struct s3c64xx_spi_driver_data {
 180         void __iomem                    *regs;
 181         struct clk                      *clk;
 182         struct clk                      *src_clk;
 183         struct clk                      *ioclk;
 184         struct platform_device          *pdev;
 185         struct spi_master               *master;
 186         struct s3c64xx_spi_info  *cntrlr_info;
 187         spinlock_t                      lock;
 188         unsigned long                   sfr_start;
 189         struct completion               xfer_completion;
 190         unsigned                        state;
 191         unsigned                        cur_mode, cur_bpw;
 192         unsigned                        cur_speed;
 193         struct s3c64xx_spi_dma_data     rx_dma;
 194         struct s3c64xx_spi_dma_data     tx_dma;
 195         struct s3c64xx_spi_port_config  *port_conf;
 196         unsigned int                    port_id;
 197 };
 198
 199 static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 200 {
 201         void __iomem *regs = sdd->regs;
 202         unsigned long loops;
 203         u32 val;
 204
 205         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 206
 207         val = readl(regs + S3C64XX_SPI_CH_CFG);
 208         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
 209         writel(val, regs + S3C64XX_SPI_CH_CFG);
 210
 211         val = readl(regs + S3C64XX_SPI_CH_CFG);
 212         val |= S3C64XX_SPI_CH_SW_RST;
 213         val &= ~S3C64XX_SPI_CH_HS_EN;
 214         writel(val, regs + S3C64XX_SPI_CH_CFG);
 215
 216         /* Flush TxFIFO*/
 217         loops = msecs_to_loops(1);
 218         do {
 219                 val = readl(regs + S3C64XX_SPI_STATUS);
 220         } while (TX_FIFO_LVL(val, sdd) && loops--);
 221
 222         if (loops == 0)
 223                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
 224
 225         /* Flush RxFIFO*/
 226         loops = msecs_to_loops(1);
 227         do {
 228                 val = readl(regs + S3C64XX_SPI_STATUS);
 229                 if (RX_FIFO_LVL(val, sdd))
 230                         readl(regs + S3C64XX_SPI_RX_DATA);
 231                 else
 232                         break;
 233         } while (loops--);
 234
 235         if (loops == 0)
 236                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
 237
 238         val = readl(regs + S3C64XX_SPI_CH_CFG);
 239         val &= ~S3C64XX_SPI_CH_SW_RST;
 240         writel(val, regs + S3C64XX_SPI_CH_CFG);
 241
 242         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 243         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 244         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 245 }
 246
 247 static void s3c64xx_spi_dmacb(void *data)
 248 {
 249         struct s3c64xx_spi_driver_data *sdd;
 250         struct s3c64xx_spi_dma_data *dma = data;
 251         unsigned long flags;
 252
 253         if (dma->direction == DMA_DEV_TO_MEM)
 254                 sdd = container_of(data,
 255                         struct s3c64xx_spi_driver_data, rx_dma);
 256         else
 257                 sdd = container_of(data,
 258                         struct s3c64xx_spi_driver_data, tx_dma);
 259
 260         spin_lock_irqsave(&sdd->lock, flags);
 261
 262         if (dma->direction == DMA_DEV_TO_MEM) {
 263                 sdd->state &= ~RXBUSY;
 264                 if (!(sdd->state & TXBUSY))
 265                         complete(&sdd->xfer_completion);
 266         } else {
 267                 sdd->state &= ~TXBUSY;
 268                 if (!(sdd->state & RXBUSY))
 269                         complete(&sdd->xfer_completion);
 270         }
 271
 272         spin_unlock_irqrestore(&sdd->lock, flags);
 273 }
 274
 275 static int prepare_dma(struct s3c64xx_spi_dma_data *dma,
 276                         struct sg_table *sgt)
 277 {
 278         struct s3c64xx_spi_driver_data *sdd;
 279         struct dma_slave_config config;
 280         struct dma_async_tx_descriptor *desc;
 281         int ret;
 282
 283         memset(&config, 0, sizeof(config));
 284
 285         if (dma->direction == DMA_DEV_TO_MEM) {
 286                 sdd = container_of((void *)dma,
 287                         struct s3c64xx_spi_driver_data, rx_dma);
 288                 config.direction = dma->direction;
 289                 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 290                 config.src_addr_width = sdd->cur_bpw / 8;
 291                 config.src_maxburst = 1;
 292                 dmaengine_slave_config(dma->ch, &config);
 293         } else {
 294                 sdd = container_of((void *)dma,
 295                         struct s3c64xx_spi_driver_data, tx_dma);
 296                 config.direction = dma->direction;
 297                 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 298                 config.dst_addr_width = sdd->cur_bpw / 8;
 299                 config.dst_maxburst = 1;
 300                 dmaengine_slave_config(dma->ch, &config);
 301         }
 302
 303         desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
 304                                        dma->direction, DMA_PREP_INTERRUPT);
 305         if (!desc) {
 306                 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist",
 307                         dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx");
 308                 return -ENOMEM;
 309         }
 310
 311         desc->callback = s3c64xx_spi_dmacb;
 312         desc->callback_param = dma;
 313
 314         dma->cookie = dmaengine_submit(desc);
 315         ret = dma_submit_error(dma->cookie);
 316         if (ret) {
 317                 dev_err(&sdd->pdev->dev, "DMA submission failed");
 318                 return -EIO;
 319         }
 320
 321         dma_async_issue_pending(dma->ch);
 322         return 0;
 323 }
 324
 325 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
 326 {
 327         struct s3c64xx_spi_driver_data *sdd =
 328                                         spi_master_get_devdata(spi->master);
 329
 330         if (sdd->cntrlr_info->no_cs)
 331                 return;
 332
 333         if (enable) {
 334                 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
 335                         writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
 336                 } else {
 337                         u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG);
 338
 339                         ssel |= (S3C64XX_SPI_CS_AUTO |
 340                                                 S3C64XX_SPI_CS_NSC_CNT_2);
 341                         writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG);
 342                 }
 343         } else {
 344                 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
 345                         writel(S3C64XX_SPI_CS_SIG_INACT,
 346                                sdd->regs + S3C64XX_SPI_CS_REG);
 347         }
 348 }
 349
 350 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 351 {
 352         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 353
 354         if (is_polling(sdd))
 355                 return 0;
 356
 357         spi->dma_rx = sdd->rx_dma.ch;
 358         spi->dma_tx = sdd->tx_dma.ch;
 359
 360         return 0;
 361 }
 362
 363 static bool s3c64xx_spi_can_dma(struct spi_master *master,
 364                                 struct spi_device *spi,
 365                                 struct spi_transfer *xfer)
 366 {
 367         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 368
 369         return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
 370 }
 371
 372 static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 373                                     struct spi_transfer *xfer, int dma_mode)
 374 {
 375         void __iomem *regs = sdd->regs;
 376         u32 modecfg, chcfg;
 377         int ret = 0;
 378
 379         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
 380         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 381
 382         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
 383         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
 384
 385         if (dma_mode) {
 386                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
 387         } else {
 388                 /* Always shift in data in FIFO, even if xfer is Tx only,
 389                  * this helps setting PCKT_CNT value for generating clocks
 390                  * as exactly needed.
 391                  */
 392                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 393                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 394                                         | S3C64XX_SPI_PACKET_CNT_EN,
 395                                         regs + S3C64XX_SPI_PACKET_CNT);
 396         }
 397
 398         if (xfer->tx_buf != NULL) {
 399                 sdd->state |= TXBUSY;
 400                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
 401                 if (dma_mode) {
 402                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
 403                         ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
 404                 } else {
 405                         switch (sdd->cur_bpw) {
 406                         case 32:
 407                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
 408                                         xfer->tx_buf, xfer->len / 4);
 409                                 break;
 410                         case 16:
 411                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
 412                                         xfer->tx_buf, xfer->len / 2);
 413                                 break;
 414                         default:
 415                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
 416                                         xfer->tx_buf, xfer->len);
 417                                 break;
 418                         }
 419                 }
 420         }
 421
 422         if (xfer->rx_buf != NULL) {
 423                 sdd->state |= RXBUSY;
 424
 425                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
 426                                         && !(sdd->cur_mode & SPI_CPHA))
 427                         chcfg |= S3C64XX_SPI_CH_HS_EN;
 428
 429                 if (dma_mode) {
 430                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
 431                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 432                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 433                                         | S3C64XX_SPI_PACKET_CNT_EN,
 434                                         regs + S3C64XX_SPI_PACKET_CNT);
 435                         ret = prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
 436                 }
 437         }
 438
 439         if (ret)
 440                 return ret;
 441
 442         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
 443         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
 444
 445         return 0;
 446 }
 447
 448 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
 449                                         int timeout_ms)
 450 {
 451         void __iomem *regs = sdd->regs;
 452         unsigned long val = 1;
 453         u32 status;
 454
 455         /* max fifo depth available */
 456         u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
 457
 458         if (timeout_ms)
 459                 val = msecs_to_loops(timeout_ms);
 460
 461         do {
 462                 status = readl(regs + S3C64XX_SPI_STATUS);
 463         } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
 464
 465         /* return the actual received data length */
 466         return RX_FIFO_LVL(status, sdd);
 467 }
 468
 469 static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
 470                                 struct spi_transfer *xfer)
 471 {
 472         void __iomem *regs = sdd->regs;
 473         unsigned long val;
 474         u32 status;
 475         int ms;
 476
 477         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 478         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 479         ms += 10; /* some tolerance */
 480
 481         val = msecs_to_jiffies(ms) + 10;
 482         val = wait_for_completion_timeout(&sdd->xfer_completion, val);
 483
 484         /*
 485          * If the previous xfer was completed within timeout, then
 486          * proceed further else return -EIO.
 487          * DmaTx returns after simply writing data in the FIFO,
 488          * w/o waiting for real transmission on the bus to finish.
 489          * DmaRx returns only after Dma read data from FIFO which
 490          * needs bus transmission to finish, so we don't worry if
 491          * Xfer involved Rx(with or without Tx).
 492          */
 493         if (val && !xfer->rx_buf) {
 494                 val = msecs_to_loops(10);
 495                 status = readl(regs + S3C64XX_SPI_STATUS);
 496                 while ((TX_FIFO_LVL(status, sdd)
 497                         || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
 498                        && --val) {
 499                         cpu_relax();
 500                         status = readl(regs + S3C64XX_SPI_STATUS);
 501                 }
 502
 503         }
 504
 505         /* If timed out while checking rx/tx status return error */
 506         if (!val)
 507                 return -EIO;
 508
 509         return 0;
 510 }
 511
 512 static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
 513                                 struct spi_transfer *xfer)
 514 {
 515         void __iomem *regs = sdd->regs;
 516         unsigned long val;
 517         u32 status;
 518         int loops;
 519         u32 cpy_len;
 520         u8 *buf;
 521         int ms;
 522
 523         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 524         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 525         ms += 10; /* some tolerance */
 526
 527         val = msecs_to_loops(ms);
 528         do {
 529                 status = readl(regs + S3C64XX_SPI_STATUS);
 530         } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
 531
 532         if (!val)
 533                 return -EIO;
 534
 535         /* If it was only Tx */
 536         if (!xfer->rx_buf) {
 537                 sdd->state &= ~TXBUSY;
 538                 return 0;
 539         }
 540
 541         /*
 542          * If the receive length is bigger than the controller fifo
 543          * size, calculate the loops and read the fifo as many times.
 544          * loops = length / max fifo size (calculated by using the
 545          * fifo mask).
 546          * For any size less than the fifo size the below code is
 547          * executed atleast once.
 548          */
 549         loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
 550         buf = xfer->rx_buf;
 551         do {
 552                 /* wait for data to be received in the fifo */
 553                 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
 554                                                        (loops ? ms : 0));
 555
 556                 switch (sdd->cur_bpw) {
 557                 case 32:
 558                         ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
 559                                      buf, cpy_len / 4);
 560                         break;
 561                 case 16:
 562                         ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
 563                                      buf, cpy_len / 2);
 564                         break;
 565                 default:
 566                         ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
 567                                     buf, cpy_len);
 568                         break;
 569                 }
 570
 571                 buf = buf + cpy_len;
 572         } while (loops--);
 573         sdd->state &= ~RXBUSY;
 574
 575         return 0;
 576 }
 577
 578 static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 579 {
 580         void __iomem *regs = sdd->regs;
 581         int ret;
 582         u32 val;
 583
 584         /* Disable Clock */
 585         if (!sdd->port_conf->clk_from_cmu) {
 586                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 587                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 588                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 589         }
 590
 591         /* Set Polarity and Phase */
 592         val = readl(regs + S3C64XX_SPI_CH_CFG);
 593         val &= ~(S3C64XX_SPI_CH_SLAVE |
 594                         S3C64XX_SPI_CPOL_L |
 595                         S3C64XX_SPI_CPHA_B);
 596
 597         if (sdd->cur_mode & SPI_CPOL)
 598                 val |= S3C64XX_SPI_CPOL_L;
 599
 600         if (sdd->cur_mode & SPI_CPHA)
 601                 val |= S3C64XX_SPI_CPHA_B;
 602
 603         writel(val, regs + S3C64XX_SPI_CH_CFG);
 604
 605         /* Set Channel & DMA Mode */
 606         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 607         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
 608                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
 609
 610         switch (sdd->cur_bpw) {
 611         case 32:
 612                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
 613                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
 614                 break;
 615         case 16:
 616                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
 617                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
 618                 break;
 619         default:
 620                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
 621                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
 622                 break;
 623         }
 624
 625         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 626
 627         if (sdd->port_conf->clk_from_cmu) {
 628                 /* The src_clk clock is divided internally by 2 */
 629                 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
 630                 if (ret)
 631                         return ret;
 632         } else {
 633                 /* Configure Clock */
 634                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 635                 val &= ~S3C64XX_SPI_PSR_MASK;
 636                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
 637                                 & S3C64XX_SPI_PSR_MASK);
 638                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 639
 640                 /* Enable Clock */
 641                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 642                 val |= S3C64XX_SPI_ENCLK_ENABLE;
 643                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 644         }
 645
 646         return 0;
 647 }
 648
 649 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
 650
 651 static int s3c64xx_spi_prepare_message(struct spi_master *master,
 652                                        struct spi_message *msg)
 653 {
 654         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 655         struct spi_device *spi = msg->spi;
 656         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 657
 658         /* Configure feedback delay */
 659         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
 660
 661         return 0;
 662 }
 663
 664 static int s3c64xx_spi_transfer_one(struct spi_master *master,
 665                                     struct spi_device *spi,
 666                                     struct spi_transfer *xfer)
 667 {
 668         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 669         const unsigned int fifo_len = (FIFO_LVL_MASK(sdd) >> 1) + 1;
 670         const void *tx_buf = NULL;
 671         void *rx_buf = NULL;
 672         int target_len = 0, origin_len = 0;
 673         int use_dma = 0;
 674         int status;
 675         u32 speed;
 676         u8 bpw;
 677         unsigned long flags;
 678
 679         reinit_completion(&sdd->xfer_completion);
 680
 681         /* Only BPW and Speed may change across transfers */
 682         bpw = xfer->bits_per_word;
 683         speed = xfer->speed_hz;
 684
 685         if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
 686                 sdd->cur_bpw = bpw;
 687                 sdd->cur_speed = speed;
 688                 sdd->cur_mode = spi->mode;
 689                 status = s3c64xx_spi_config(sdd);
 690                 if (status)
 691                         return status;
 692         }
 693
 694         if (!is_polling(sdd) && (xfer->len > fifo_len) &&
 695             sdd->rx_dma.ch && sdd->tx_dma.ch) {
 696                 use_dma = 1;
 697
 698         } else if (is_polling(sdd) && xfer->len > fifo_len) {
 699                 tx_buf = xfer->tx_buf;
 700                 rx_buf = xfer->rx_buf;
 701                 origin_len = xfer->len;
 702
 703                 target_len = xfer->len;
 704                 if (xfer->len > fifo_len)
 705                         xfer->len = fifo_len;
 706         }
 707
 708         do {
 709                 spin_lock_irqsave(&sdd->lock, flags);
 710
 711                 /* Pending only which is to be done */
 712                 sdd->state &= ~RXBUSY;
 713                 sdd->state &= ~TXBUSY;
 714
 715                 /* Start the signals */
 716                 s3c64xx_spi_set_cs(spi, true);
 717
 718                 status = s3c64xx_enable_datapath(sdd, xfer, use_dma);
 719
 720                 spin_unlock_irqrestore(&sdd->lock, flags);
 721
 722                 if (status) {
 723                         dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status);
 724                         break;
 725                 }
 726
 727                 if (use_dma)
 728                         status = s3c64xx_wait_for_dma(sdd, xfer);
 729                 else
 730                         status = s3c64xx_wait_for_pio(sdd, xfer);
 731
 732                 if (status) {
 733                         dev_err(&spi->dev,
 734                                 "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n",
 735                                 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
 736                                 (sdd->state & RXBUSY) ? 'f' : 'p',
 737                                 (sdd->state & TXBUSY) ? 'f' : 'p',
 738                                 xfer->len, use_dma ? 1 : 0, status);
 739
 740                         if (use_dma) {
 741                                 struct dma_tx_state s;
 742
 743                                 if (xfer->tx_buf && (sdd->state & TXBUSY)) {
 744                                         dmaengine_pause(sdd->tx_dma.ch);
 745                                         dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s);
 746                                         dmaengine_terminate_all(sdd->tx_dma.ch);
 747                                         dev_err(&spi->dev, "TX residue: %d\n", s.residue);
 748
 749                                 }
 750                                 if (xfer->rx_buf && (sdd->state & RXBUSY)) {
 751                                         dmaengine_pause(sdd->rx_dma.ch);
 752                                         dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s);
 753                                         dmaengine_terminate_all(sdd->rx_dma.ch);
 754                                         dev_err(&spi->dev, "RX residue: %d\n", s.residue);
 755                                 }
 756                         }
 757                 } else {
 758                         s3c64xx_flush_fifo(sdd);
 759                 }
 760                 if (target_len > 0) {
 761                         target_len -= xfer->len;
 762
 763                         if (xfer->tx_buf)
 764                                 xfer->tx_buf += xfer->len;
 765
 766                         if (xfer->rx_buf)
 767                                 xfer->rx_buf += xfer->len;
 768
 769                         if (target_len > fifo_len)
 770                                 xfer->len = fifo_len;
 771                         else
 772                                 xfer->len = target_len;
 773                 }
 774         } while (target_len > 0);
 775
 776         if (origin_len) {
 777                 /* Restore original xfer buffers and length */
 778                 xfer->tx_buf = tx_buf;
 779                 xfer->rx_buf = rx_buf;
 780                 xfer->len = origin_len;
 781         }
 782
 783         return status;
 784 }
 785
 786 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
 787                                 struct spi_device *spi)
 788 {
 789         struct s3c64xx_spi_csinfo *cs;
 790         struct device_node *slave_np, *data_np = NULL;
 791         u32 fb_delay = 0;
 792
 793         slave_np = spi->dev.of_node;
 794         if (!slave_np) {
 795                 dev_err(&spi->dev, "device node not found\n");
 796                 return ERR_PTR(-EINVAL);
 797         }
 798
 799         data_np = of_get_child_by_name(slave_np, "controller-data");
 800         if (!data_np) {
 801                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
 802                 return ERR_PTR(-EINVAL);
 803         }
 804
 805         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 806         if (!cs) {
 807                 of_node_put(data_np);
 808                 return ERR_PTR(-ENOMEM);
 809         }
 810
 811         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
 812         cs->fb_delay = fb_delay;
 813         of_node_put(data_np);
 814         return cs;
 815 }
 816
 817 /*
 818  * Here we only check the validity of requested configuration
 819  * and save the configuration in a local data-structure.
 820  * The controller is actually configured only just before we
 821  * get a message to transfer.
 822  */
 823 static int s3c64xx_spi_setup(struct spi_device *spi)
 824 {
 825         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 826         struct s3c64xx_spi_driver_data *sdd;
 827         int err;
 828
 829         sdd = spi_master_get_devdata(spi->master);
 830         if (spi->dev.of_node) {
 831                 cs = s3c64xx_get_slave_ctrldata(spi);
 832                 spi->controller_data = cs;
 833         } else if (cs) {
 834                 /* On non-DT platforms the SPI core will set spi->cs_gpio
 835                  * to -ENOENT. The GPIO pin used to drive the chip select
 836                  * is defined by using platform data so spi->cs_gpio value
 837                  * has to be override to have the proper GPIO pin number.
 838                  */
 839                 spi->cs_gpio = cs->line;
 840         }
 841
 842         if (IS_ERR_OR_NULL(cs)) {
 843                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
 844                 return -ENODEV;
 845         }
 846
 847         if (!spi_get_ctldata(spi)) {
 848                 if (gpio_is_valid(spi->cs_gpio)) {
 849                         err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
 850                                                dev_name(&spi->dev));
 851                         if (err) {
 852                                 dev_err(&spi->dev,
 853                                         "Failed to get /CS gpio [%d]: %d\n",
 854                                         spi->cs_gpio, err);
 855                                 goto err_gpio_req;
 856                         }
 857                 }
 858
 859                 spi_set_ctldata(spi, cs);
 860         }
 861
 862         pm_runtime_get_sync(&sdd->pdev->dev);
 863
 864         /* Check if we can provide the requested rate */
 865         if (!sdd->port_conf->clk_from_cmu) {
 866                 u32 psr, speed;
 867
 868                 /* Max possible */
 869                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
 870
 871                 if (spi->max_speed_hz > speed)
 872                         spi->max_speed_hz = speed;
 873
 874                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
 875                 psr &= S3C64XX_SPI_PSR_MASK;
 876                 if (psr == S3C64XX_SPI_PSR_MASK)
 877                         psr--;
 878
 879                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 880                 if (spi->max_speed_hz < speed) {
 881                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
 882                                 psr++;
 883                         } else {
 884                                 err = -EINVAL;
 885                                 goto setup_exit;
 886                         }
 887                 }
 888
 889                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 890                 if (spi->max_speed_hz >= speed) {
 891                         spi->max_speed_hz = speed;
 892                 } else {
 893                         dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
 894                                 spi->max_speed_hz);
 895                         err = -EINVAL;
 896                         goto setup_exit;
 897                 }
 898         }
 899
 900         pm_runtime_mark_last_busy(&sdd->pdev->dev);
 901         pm_runtime_put_autosuspend(&sdd->pdev->dev);
 902         s3c64xx_spi_set_cs(spi, false);
 903
 904         return 0;
 905
 906 setup_exit:
 907         pm_runtime_mark_last_busy(&sdd->pdev->dev);
 908         pm_runtime_put_autosuspend(&sdd->pdev->dev);
 909         /* setup() returns with device de-selected */
 910         s3c64xx_spi_set_cs(spi, false);
 911
 912         if (gpio_is_valid(spi->cs_gpio))
 913                 gpio_free(spi->cs_gpio);
 914         spi_set_ctldata(spi, NULL);
 915
 916 err_gpio_req:
 917         if (spi->dev.of_node)
 918                 kfree(cs);
 919
 920         return err;
 921 }
 922
 923 static void s3c64xx_spi_cleanup(struct spi_device *spi)
 924 {
 925         struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
 926
 927         if (gpio_is_valid(spi->cs_gpio)) {
 928                 gpio_free(spi->cs_gpio);
 929                 if (spi->dev.of_node)
 930                         kfree(cs);
 931                 else {
 932                         /* On non-DT platforms, the SPI core sets
 933                          * spi->cs_gpio to -ENOENT and .setup()
 934                          * overrides it with the GPIO pin value
 935                          * passed using platform data.
 936                          */
 937                         spi->cs_gpio = -ENOENT;
 938                 }
 939         }
 940
 941         spi_set_ctldata(spi, NULL);
 942 }
 943
 944 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
 945 {
 946         struct s3c64xx_spi_driver_data *sdd = data;
 947         struct spi_master *spi = sdd->master;
 948         unsigned int val, clr = 0;
 949
 950         val = readl(sdd->regs + S3C64XX_SPI_STATUS);
 951
 952         if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
 953                 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
 954                 dev_err(&spi->dev, "RX overrun\n");
 955         }
 956         if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
 957                 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
 958                 dev_err(&spi->dev, "RX underrun\n");
 959         }
 960         if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
 961                 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
 962                 dev_err(&spi->dev, "TX overrun\n");
 963         }
 964         if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
 965                 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
 966                 dev_err(&spi->dev, "TX underrun\n");
 967         }
 968
 969         /* Clear the pending irq by setting and then clearing it */
 970         writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
 971         writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
 972
 973         return IRQ_HANDLED;
 974 }
 975
 976 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd)
 977 {
 978         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 979         void __iomem *regs = sdd->regs;
 980         unsigned int val;
 981
 982         sdd->cur_speed = 0;
 983
 984         if (sci->no_cs)
 985                 writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
 986         else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
 987                 writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG);
 988
 989         /* Disable Interrupts - we use Polling if not DMA mode */
 990         writel(0, regs + S3C64XX_SPI_INT_EN);
 991
 992         if (!sdd->port_conf->clk_from_cmu)
 993                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
 994                                 regs + S3C64XX_SPI_CLK_CFG);
 995         writel(0, regs + S3C64XX_SPI_MODE_CFG);
 996         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 997
 998         /* Clear any irq pending bits, should set and clear the bits */
 999         val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1000                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1001                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1002                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1003         writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1004         writel(0, regs + S3C64XX_SPI_PENDING_CLR);
1005
1006         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1007
1008         val = readl(regs + S3C64XX_SPI_MODE_CFG);
1009         val &= ~S3C64XX_SPI_MODE_4BURST;
1010         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1011         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1012         writel(val, regs + S3C64XX_SPI_MODE_CFG);
1013
1014         s3c64xx_flush_fifo(sdd);
1015 }
1016
1017 #ifdef CONFIG_OF
1018 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1019 {
1020         struct s3c64xx_spi_info *sci;
1021         u32 temp;
1022
1023         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1024         if (!sci)
1025                 return ERR_PTR(-ENOMEM);
1026
1027         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1028                 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1029                 sci->src_clk_nr = 0;
1030         } else {
1031                 sci->src_clk_nr = temp;
1032         }
1033
1034         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1035                 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1036                 sci->num_cs = 1;
1037         } else {
1038                 sci->num_cs = temp;
1039         }
1040
1041         sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
1042
1043         return sci;
1044 }
1045 #else
1046 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1047 {
1048         return dev_get_platdata(dev);
1049 }
1050 #endif
1051
1052 static const struct of_device_id s3c64xx_spi_dt_match[];
1053
1054 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1055                                                 struct platform_device *pdev)
1056 {
1057 #ifdef CONFIG_OF
1058         if (pdev->dev.of_node) {
1059                 const struct of_device_id *match;
1060                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1061                 return (struct s3c64xx_spi_port_config *)match->data;
1062         }
1063 #endif
1064         return (struct s3c64xx_spi_port_config *)
1065                          platform_get_device_id(pdev)->driver_data;
1066 }
1067
1068 static int s3c64xx_spi_probe(struct platform_device *pdev)
1069 {
1070         struct resource *mem_res;
1071         struct s3c64xx_spi_driver_data *sdd;
1072         struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1073         struct spi_master *master;
1074         int ret, irq;
1075         char clk_name[16];
1076
1077         if (!sci && pdev->dev.of_node) {
1078                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1079                 if (IS_ERR(sci))
1080                         return PTR_ERR(sci);
1081         }
1082
1083         if (!sci) {
1084                 dev_err(&pdev->dev, "platform_data missing!\n");
1085                 return -ENODEV;
1086         }
1087
1088         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1089         if (mem_res == NULL) {
1090                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1091                 return -ENXIO;
1092         }
1093
1094         irq = platform_get_irq(pdev, 0);
1095         if (irq < 0) {
1096                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1097                 return irq;
1098         }
1099
1100         master = spi_alloc_master(&pdev->dev,
1101                                 sizeof(struct s3c64xx_spi_driver_data));
1102         if (master == NULL) {
1103                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1104                 return -ENOMEM;
1105         }
1106
1107         platform_set_drvdata(pdev, master);
1108
1109         sdd = spi_master_get_devdata(master);
1110         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1111         sdd->master = master;
1112         sdd->cntrlr_info = sci;
1113         sdd->pdev = pdev;
1114         sdd->sfr_start = mem_res->start;
1115         if (pdev->dev.of_node) {
1116                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1117                 if (ret < 0) {
1118                         dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1119                                 ret);
1120                         goto err_deref_master;
1121                 }
1122                 sdd->port_id = ret;
1123         } else {
1124                 sdd->port_id = pdev->id;
1125         }
1126
1127         sdd->cur_bpw = 8;
1128
1129         sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1130         sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1131
1132         master->dev.of_node = pdev->dev.of_node;
1133         master->bus_num = sdd->port_id;
1134         master->setup = s3c64xx_spi_setup;
1135         master->cleanup = s3c64xx_spi_cleanup;
1136         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1137         master->prepare_message = s3c64xx_spi_prepare_message;
1138         master->transfer_one = s3c64xx_spi_transfer_one;
1139         master->num_chipselect = sci->num_cs;
1140         master->dma_alignment = 8;
1141         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1142                                         SPI_BPW_MASK(8);
1143         /* the spi->mode bits understood by this driver: */
1144         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1145         master->auto_runtime_pm = true;
1146         if (!is_polling(sdd))
1147                 master->can_dma = s3c64xx_spi_can_dma;
1148
1149         sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1150         if (IS_ERR(sdd->regs)) {
1151                 ret = PTR_ERR(sdd->regs);
1152                 goto err_deref_master;
1153         }
1154
1155         if (sci->cfg_gpio && sci->cfg_gpio()) {
1156                 dev_err(&pdev->dev, "Unable to config gpio\n");
1157                 ret = -EBUSY;
1158                 goto err_deref_master;
1159         }
1160
1161         /* Setup clocks */
1162         sdd->clk = devm_clk_get(&pdev->dev, "spi");
1163         if (IS_ERR(sdd->clk)) {
1164                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1165                 ret = PTR_ERR(sdd->clk);
1166                 goto err_deref_master;
1167         }
1168
1169         ret = clk_prepare_enable(sdd->clk);
1170         if (ret) {
1171                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1172                 goto err_deref_master;
1173         }
1174
1175         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1176         sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1177         if (IS_ERR(sdd->src_clk)) {
1178                 dev_err(&pdev->dev,
1179                         "Unable to acquire clock '%s'\n", clk_name);
1180                 ret = PTR_ERR(sdd->src_clk);
1181                 goto err_disable_clk;
1182         }
1183
1184         ret = clk_prepare_enable(sdd->src_clk);
1185         if (ret) {
1186                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1187                 goto err_disable_clk;
1188         }
1189
1190         if (sdd->port_conf->clk_ioclk) {
1191                 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk");
1192                 if (IS_ERR(sdd->ioclk)) {
1193                         dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n");
1194                         ret = PTR_ERR(sdd->ioclk);
1195                         goto err_disable_src_clk;
1196                 }
1197
1198                 ret = clk_prepare_enable(sdd->ioclk);
1199                 if (ret) {
1200                         dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n");
1201                         goto err_disable_src_clk;
1202                 }
1203         }
1204
1205         if (!is_polling(sdd)) {
1206                 /* Acquire DMA channels */
1207                 sdd->rx_dma.ch = dma_request_chan(&pdev->dev, "rx");
1208                 if (IS_ERR(sdd->rx_dma.ch)) {
1209                         dev_err(&pdev->dev, "Failed to get RX DMA channel\n");
1210                         ret = PTR_ERR(sdd->rx_dma.ch);
1211                         goto err_disable_io_clk;
1212                 }
1213                 sdd->tx_dma.ch = dma_request_chan(&pdev->dev, "tx");
1214                 if (IS_ERR(sdd->tx_dma.ch)) {
1215                         dev_err(&pdev->dev, "Failed to get TX DMA channel\n");
1216                         ret = PTR_ERR(sdd->tx_dma.ch);
1217                         goto err_release_rx_dma;
1218                 }
1219         }
1220
1221         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1222         pm_runtime_use_autosuspend(&pdev->dev);
1223         pm_runtime_set_active(&pdev->dev);
1224         pm_runtime_enable(&pdev->dev);
1225         pm_runtime_get_sync(&pdev->dev);
1226
1227         /* Setup Deufult Mode */
1228         s3c64xx_spi_hwinit(sdd);
1229
1230         spin_lock_init(&sdd->lock);
1231         init_completion(&sdd->xfer_completion);
1232
1233         ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1234                                 "spi-s3c64xx", sdd);
1235         if (ret != 0) {
1236                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1237                         irq, ret);
1238                 goto err_pm_put;
1239         }
1240
1241         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1242                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1243                sdd->regs + S3C64XX_SPI_INT_EN);
1244
1245         ret = devm_spi_register_master(&pdev->dev, master);
1246         if (ret != 0) {
1247                 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1248                 goto err_pm_put;
1249         }
1250
1251         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1252                                         sdd->port_id, master->num_chipselect);
1253         dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1254                                         mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1);
1255
1256         pm_runtime_mark_last_busy(&pdev->dev);
1257         pm_runtime_put_autosuspend(&pdev->dev);
1258
1259         return 0;
1260
1261 err_pm_put:
1262         pm_runtime_put_noidle(&pdev->dev);
1263         pm_runtime_disable(&pdev->dev);
1264         pm_runtime_set_suspended(&pdev->dev);
1265
1266         if (!is_polling(sdd))
1267                 dma_release_channel(sdd->tx_dma.ch);
1268 err_release_rx_dma:
1269         if (!is_polling(sdd))
1270                 dma_release_channel(sdd->rx_dma.ch);
1271 err_disable_io_clk:
1272         clk_disable_unprepare(sdd->ioclk);
1273 err_disable_src_clk:
1274         clk_disable_unprepare(sdd->src_clk);
1275 err_disable_clk:
1276         clk_disable_unprepare(sdd->clk);
1277 err_deref_master:
1278         spi_master_put(master);
1279
1280         return ret;
1281 }
1282
1283 static int s3c64xx_spi_remove(struct platform_device *pdev)
1284 {
1285         struct spi_master *master = platform_get_drvdata(pdev);
1286         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1287
1288         pm_runtime_get_sync(&pdev->dev);
1289
1290         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1291
1292         if (!is_polling(sdd)) {
1293                 dma_release_channel(sdd->rx_dma.ch);
1294                 dma_release_channel(sdd->tx_dma.ch);
1295         }
1296
1297         clk_disable_unprepare(sdd->ioclk);
1298
1299         clk_disable_unprepare(sdd->src_clk);
1300
1301         clk_disable_unprepare(sdd->clk);
1302
1303         pm_runtime_put_noidle(&pdev->dev);
1304         pm_runtime_disable(&pdev->dev);
1305         pm_runtime_set_suspended(&pdev->dev);
1306
1307         return 0;
1308 }
1309
1310 #ifdef CONFIG_PM_SLEEP
1311 static int s3c64xx_spi_suspend(struct device *dev)
1312 {
1313         struct spi_master *master = dev_get_drvdata(dev);
1314         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1315
1316         int ret = spi_master_suspend(master);
1317         if (ret)
1318                 return ret;
1319
1320         ret = pm_runtime_force_suspend(dev);
1321         if (ret < 0)
1322                 return ret;
1323
1324         sdd->cur_speed = 0; /* Output Clock is stopped */
1325
1326         return 0;
1327 }
1328
1329 static int s3c64xx_spi_resume(struct device *dev)
1330 {
1331         struct spi_master *master = dev_get_drvdata(dev);
1332         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1333         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1334         int ret;
1335
1336         if (sci->cfg_gpio)
1337                 sci->cfg_gpio();
1338
1339         ret = pm_runtime_force_resume(dev);
1340         if (ret < 0)
1341                 return ret;
1342
1343         return spi_master_resume(master);
1344 }
1345 #endif /* CONFIG_PM_SLEEP */
1346
1347 #ifdef CONFIG_PM
1348 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1349 {
1350         struct spi_master *master = dev_get_drvdata(dev);
1351         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1352
1353         clk_disable_unprepare(sdd->clk);
1354         clk_disable_unprepare(sdd->src_clk);
1355         clk_disable_unprepare(sdd->ioclk);
1356
1357         return 0;
1358 }
1359
1360 static int s3c64xx_spi_runtime_resume(struct device *dev)
1361 {
1362         struct spi_master *master = dev_get_drvdata(dev);
1363         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1364         int ret;
1365
1366         if (sdd->port_conf->clk_ioclk) {
1367                 ret = clk_prepare_enable(sdd->ioclk);
1368                 if (ret != 0)
1369                         return ret;
1370         }
1371
1372         ret = clk_prepare_enable(sdd->src_clk);
1373         if (ret != 0)
1374                 goto err_disable_ioclk;
1375
1376         ret = clk_prepare_enable(sdd->clk);
1377         if (ret != 0)
1378                 goto err_disable_src_clk;
1379
1380         s3c64xx_spi_hwinit(sdd);
1381
1382         return 0;
1383
1384 err_disable_src_clk:
1385         clk_disable_unprepare(sdd->src_clk);
1386 err_disable_ioclk:
1387         clk_disable_unprepare(sdd->ioclk);
1388
1389         return ret;
1390 }
1391 #endif /* CONFIG_PM */
1392
1393 static const struct dev_pm_ops s3c64xx_spi_pm = {
1394         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1395         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1396                            s3c64xx_spi_runtime_resume, NULL)
1397 };
1398
1399 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1400         .fifo_lvl_mask  = { 0x7f },
1401         .rx_lvl_offset  = 13,
1402         .tx_st_done     = 21,
1403         .high_speed     = true,
1404 };
1405
1406 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1407         .fifo_lvl_mask  = { 0x7f, 0x7F },
1408         .rx_lvl_offset  = 13,
1409         .tx_st_done     = 21,
1410 };
1411
1412 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1413         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1414         .rx_lvl_offset  = 15,
1415         .tx_st_done     = 25,
1416         .high_speed     = true,
1417 };
1418
1419 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1420         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1421         .rx_lvl_offset  = 15,
1422         .tx_st_done     = 25,
1423         .high_speed     = true,
1424         .clk_from_cmu   = true,
1425         .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1426 };
1427
1428 static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1429         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1430         .rx_lvl_offset  = 15,
1431         .tx_st_done     = 25,
1432         .high_speed     = true,
1433         .clk_from_cmu   = true,
1434         .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1435 };
1436
1437 static struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
1438         .fifo_lvl_mask  = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1439         .rx_lvl_offset  = 15,
1440         .tx_st_done     = 25,
1441         .high_speed     = true,
1442         .clk_from_cmu   = true,
1443         .clk_ioclk      = true,
1444         .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1445 };
1446
1447 static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1448         {
1449                 .name           = "s3c2443-spi",
1450                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1451         }, {
1452                 .name           = "s3c6410-spi",
1453                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1454         },
1455         { },
1456 };
1457
1458 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1459         { .compatible = "samsung,s3c2443-spi",
1460                         .data = (void *)&s3c2443_spi_port_config,
1461         },
1462         { .compatible = "samsung,s3c6410-spi",
1463                         .data = (void *)&s3c6410_spi_port_config,
1464         },
1465         { .compatible = "samsung,s5pv210-spi",
1466                         .data = (void *)&s5pv210_spi_port_config,
1467         },
1468         { .compatible = "samsung,exynos4210-spi",
1469                         .data = (void *)&exynos4_spi_port_config,
1470         },
1471         { .compatible = "samsung,exynos7-spi",
1472                         .data = (void *)&exynos7_spi_port_config,
1473         },
1474         { .compatible = "samsung,exynos5433-spi",
1475                         .data = (void *)&exynos5433_spi_port_config,
1476         },
1477         { },
1478 };
1479 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1480
1481 static struct platform_driver s3c64xx_spi_driver = {
1482         .driver = {
1483                 .name   = "s3c64xx-spi",
1484                 .pm = &s3c64xx_spi_pm,
1485                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1486         },
1487         .probe = s3c64xx_spi_probe,
1488         .remove = s3c64xx_spi_remove,
1489         .id_table = s3c64xx_spi_driver_ids,
1490 };
1491 MODULE_ALIAS("platform:s3c64xx-spi");
1492
1493 module_platform_driver(s3c64xx_spi_driver);
1494
1495 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1496 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1497 MODULE_LICENSE("GPL");