4 * Copyright (C) 2012, 2013 Renesas Solutions Corp.
5 * Copyright (C) 2014 Glider bvba
8 * Copyright (C) 2011 Renesas Solutions Corp.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/sched.h>
28 #include <linux/errno.h>
29 #include <linux/interrupt.h>
30 #include <linux/platform_device.h>
32 #include <linux/clk.h>
33 #include <linux/dmaengine.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/of_device.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/sh_dma.h>
38 #include <linux/spi/spi.h>
39 #include <linux/spi/rspi.h>
41 #define RSPI_SPCR 0x00 /* Control Register */
42 #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
43 #define RSPI_SPPCR 0x02 /* Pin Control Register */
44 #define RSPI_SPSR 0x03 /* Status Register */
45 #define RSPI_SPDR 0x04 /* Data Register */
46 #define RSPI_SPSCR 0x08 /* Sequence Control Register */
47 #define RSPI_SPSSR 0x09 /* Sequence Status Register */
48 #define RSPI_SPBR 0x0a /* Bit Rate Register */
49 #define RSPI_SPDCR 0x0b /* Data Control Register */
50 #define RSPI_SPCKD 0x0c /* Clock Delay Register */
51 #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
52 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
53 #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */
54 #define RSPI_SPCMD0 0x10 /* Command Register 0 */
55 #define RSPI_SPCMD1 0x12 /* Command Register 1 */
56 #define RSPI_SPCMD2 0x14 /* Command Register 2 */
57 #define RSPI_SPCMD3 0x16 /* Command Register 3 */
58 #define RSPI_SPCMD4 0x18 /* Command Register 4 */
59 #define RSPI_SPCMD5 0x1a /* Command Register 5 */
60 #define RSPI_SPCMD6 0x1c /* Command Register 6 */
61 #define RSPI_SPCMD7 0x1e /* Command Register 7 */
62 #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2)
63 #define RSPI_NUM_SPCMD 8
64 #define RSPI_RZ_NUM_SPCMD 4
65 #define QSPI_NUM_SPCMD 4
68 #define RSPI_SPBFCR 0x20 /* Buffer Control Register */
69 #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
72 #define QSPI_SPBFCR 0x18 /* Buffer Control Register */
73 #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
74 #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
75 #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
76 #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
77 #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
78 #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4)
80 /* SPCR - Control Register */
81 #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
82 #define SPCR_SPE 0x40 /* Function Enable */
83 #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */
84 #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */
85 #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
86 #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
88 #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
89 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
90 /* QSPI on R-Car M2 only */
91 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
92 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
94 /* SSLP - Slave Select Polarity Register */
95 #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */
96 #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */
98 /* SPPCR - Pin Control Register */
99 #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
100 #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */
101 #define SPPCR_SPOM 0x04
102 #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
103 #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
105 #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
106 #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
108 /* SPSR - Status Register */
109 #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */
110 #define SPSR_TEND 0x40 /* Transmit End */
111 #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */
112 #define SPSR_PERF 0x08 /* Parity Error Flag */
113 #define SPSR_MODF 0x04 /* Mode Fault Error Flag */
114 #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
115 #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */
117 /* SPSCR - Sequence Control Register */
118 #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
120 /* SPSSR - Sequence Status Register */
121 #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */
122 #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */
124 /* SPDCR - Data Control Register */
125 #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */
126 #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */
127 #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */
128 #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
129 #define SPDCR_SPLWORD SPDCR_SPLW1
130 #define SPDCR_SPLBYTE SPDCR_SPLW0
131 #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
132 #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */
133 #define SPDCR_SLSEL1 0x08
134 #define SPDCR_SLSEL0 0x04
135 #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */
136 #define SPDCR_SPFC1 0x02
137 #define SPDCR_SPFC0 0x01
138 #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
140 /* SPCKD - Clock Delay Register */
141 #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
143 /* SSLND - Slave Select Negation Delay Register */
144 #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
146 /* SPND - Next-Access Delay Register */
147 #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
149 /* SPCR2 - Control Register 2 */
150 #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
151 #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */
152 #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */
153 #define SPCR2_SPPE 0x01 /* Parity Enable */
155 /* SPCMDn - Command Registers */
156 #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */
157 #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */
158 #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
159 #define SPCMD_LSBF 0x1000 /* LSB First */
160 #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
161 #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
162 #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */
163 #define SPCMD_SPB_16BIT 0x0100
164 #define SPCMD_SPB_20BIT 0x0000
165 #define SPCMD_SPB_24BIT 0x0100
166 #define SPCMD_SPB_32BIT 0x0200
167 #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */
168 #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */
169 #define SPCMD_SPIMOD1 0x0040
170 #define SPCMD_SPIMOD0 0x0020
171 #define SPCMD_SPIMOD_SINGLE 0
172 #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0
173 #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1
174 #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */
175 #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */
176 #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
177 #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
178 #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
180 /* SPBFCR - Buffer Control Register */
181 #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */
182 #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */
183 #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
184 #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
189 struct spi_master *master;
190 wait_queue_head_t wait;
196 const struct spi_ops *ops;
199 struct dma_chan *chan_tx;
200 struct dma_chan *chan_rx;
202 unsigned dma_callbacked:1;
203 unsigned byte_access:1;
206 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
208 iowrite8(data, rspi->addr + offset);
211 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
213 iowrite16(data, rspi->addr + offset);
216 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
218 iowrite32(data, rspi->addr + offset);
221 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
223 return ioread8(rspi->addr + offset);
226 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
228 return ioread16(rspi->addr + offset);
231 static void rspi_write_data(const struct rspi_data *rspi, u16 data)
233 if (rspi->byte_access)
234 rspi_write8(rspi, data, RSPI_SPDR);
236 rspi_write16(rspi, data, RSPI_SPDR);
239 static u16 rspi_read_data(const struct rspi_data *rspi)
241 if (rspi->byte_access)
242 return rspi_read8(rspi, RSPI_SPDR);
244 return rspi_read16(rspi, RSPI_SPDR);
247 /* optional functions */
249 int (*set_config_register)(struct rspi_data *rspi, int access_size);
250 int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
251 struct spi_transfer *xfer);
257 * functions for RSPI on legacy SH
259 static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
263 /* Sets output mode, MOSI signal, and (optionally) loopback */
264 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
266 /* Sets transfer bit rate */
267 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
268 2 * rspi->max_speed_hz) - 1;
269 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
271 /* Disable dummy transmission, set 16-bit word access, 1 frame */
272 rspi_write8(rspi, 0, RSPI_SPDCR);
273 rspi->byte_access = 0;
275 /* Sets RSPCK, SSL, next-access delay value */
276 rspi_write8(rspi, 0x00, RSPI_SPCKD);
277 rspi_write8(rspi, 0x00, RSPI_SSLND);
278 rspi_write8(rspi, 0x00, RSPI_SPND);
280 /* Sets parity, interrupt mask */
281 rspi_write8(rspi, 0x00, RSPI_SPCR2);
284 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
285 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
288 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
294 * functions for RSPI on RZ
296 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
300 /* Sets output mode, MOSI signal, and (optionally) loopback */
301 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
303 /* Sets transfer bit rate */
304 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
305 2 * rspi->max_speed_hz) - 1;
306 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
308 /* Disable dummy transmission, set byte access */
309 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
310 rspi->byte_access = 1;
312 /* Sets RSPCK, SSL, next-access delay value */
313 rspi_write8(rspi, 0x00, RSPI_SPCKD);
314 rspi_write8(rspi, 0x00, RSPI_SSLND);
315 rspi_write8(rspi, 0x00, RSPI_SPND);
318 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
319 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
322 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
330 static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
334 /* Sets output mode, MOSI signal, and (optionally) loopback */
335 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
337 /* Sets transfer bit rate */
338 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz);
339 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
341 /* Disable dummy transmission, set byte access */
342 rspi_write8(rspi, 0, RSPI_SPDCR);
343 rspi->byte_access = 1;
345 /* Sets RSPCK, SSL, next-access delay value */
346 rspi_write8(rspi, 0x00, RSPI_SPCKD);
347 rspi_write8(rspi, 0x00, RSPI_SSLND);
348 rspi_write8(rspi, 0x00, RSPI_SPND);
350 /* Data Length Setting */
351 if (access_size == 8)
352 rspi->spcmd |= SPCMD_SPB_8BIT;
353 else if (access_size == 16)
354 rspi->spcmd |= SPCMD_SPB_16BIT;
356 rspi->spcmd |= SPCMD_SPB_32BIT;
358 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
360 /* Resets transfer data length */
361 rspi_write32(rspi, 0, QSPI_SPBMUL0);
363 /* Resets transmit and receive buffer */
364 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
365 /* Sets buffer to allow normal operation */
366 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
369 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
371 /* Enables SPI function in master mode */
372 rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR);
377 #define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
379 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
381 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
384 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
386 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
389 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
394 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
395 if (rspi->spsr & wait_mask)
398 rspi_enable_irq(rspi, enable_bit);
399 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
400 if (ret == 0 && !(rspi->spsr & wait_mask))
406 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
408 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
411 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
413 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
416 static int rspi_data_out(struct rspi_data *rspi, u8 data)
418 int error = rspi_wait_for_tx_empty(rspi);
420 dev_err(&rspi->master->dev, "transmit timeout\n");
423 rspi_write_data(rspi, data);
427 static int rspi_data_in(struct rspi_data *rspi)
432 error = rspi_wait_for_rx_full(rspi);
434 dev_err(&rspi->master->dev, "receive timeout\n");
437 data = rspi_read_data(rspi);
441 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
446 int ret = rspi_data_out(rspi, *tx++);
451 int ret = rspi_data_in(rspi);
461 static void rspi_dma_complete(void *arg)
463 struct rspi_data *rspi = arg;
465 rspi->dma_callbacked = 1;
466 wake_up_interruptible(&rspi->wait);
469 static int rspi_dma_map_sg(struct scatterlist *sg, const void *buf,
470 unsigned len, struct dma_chan *chan,
471 enum dma_transfer_direction dir)
473 sg_init_table(sg, 1);
474 sg_set_buf(sg, buf, len);
475 sg_dma_len(sg) = len;
476 return dma_map_sg(chan->device->dev, sg, 1, dir);
479 static void rspi_dma_unmap_sg(struct scatterlist *sg, struct dma_chan *chan,
480 enum dma_transfer_direction dir)
482 dma_unmap_sg(chan->device->dev, sg, 1, dir);
485 static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
487 struct scatterlist sg;
488 const void *buf = t->tx_buf;
489 struct dma_async_tx_descriptor *desc;
490 unsigned int len = t->len;
493 if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE))
496 desc = dmaengine_prep_slave_sg(rspi->chan_tx, &sg, 1, DMA_TO_DEVICE,
497 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
504 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
505 * called. So, this driver disables the IRQ while DMA transfer.
507 disable_irq(rspi->tx_irq);
509 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR);
510 rspi_enable_irq(rspi, SPCR_SPTIE);
511 rspi->dma_callbacked = 0;
513 desc->callback = rspi_dma_complete;
514 desc->callback_param = rspi;
515 dmaengine_submit(desc);
516 dma_async_issue_pending(rspi->chan_tx);
518 ret = wait_event_interruptible_timeout(rspi->wait,
519 rspi->dma_callbacked, HZ);
520 if (ret > 0 && rspi->dma_callbacked)
524 rspi_disable_irq(rspi, SPCR_SPTIE);
526 enable_irq(rspi->tx_irq);
529 rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE);
533 static void rspi_receive_init(const struct rspi_data *rspi)
537 spsr = rspi_read8(rspi, RSPI_SPSR);
538 if (spsr & SPSR_SPRF)
539 rspi_read_data(rspi); /* dummy read */
540 if (spsr & SPSR_OVRF)
541 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
545 static void rspi_rz_receive_init(const struct rspi_data *rspi)
547 rspi_receive_init(rspi);
548 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
549 rspi_write8(rspi, 0, RSPI_SPBFCR);
552 static void qspi_receive_init(const struct rspi_data *rspi)
556 spsr = rspi_read8(rspi, RSPI_SPSR);
557 if (spsr & SPSR_SPRF)
558 rspi_read_data(rspi); /* dummy read */
559 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
560 rspi_write8(rspi, 0, QSPI_SPBFCR);
563 static int rspi_send_receive_dma(struct rspi_data *rspi, struct spi_transfer *t)
565 struct scatterlist sg_rx, sg_tx;
566 const void *tx_buf = t->tx_buf;
567 void *rx_buf = t->rx_buf;
568 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
569 unsigned int len = t->len;
572 /* prepare transmit transfer */
573 if (!rspi_dma_map_sg(&sg_tx, tx_buf, len, rspi->chan_tx,
577 desc_tx = dmaengine_prep_slave_sg(rspi->chan_tx, &sg_tx, 1,
578 DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
584 /* prepare receive transfer */
585 if (!rspi_dma_map_sg(&sg_rx, rx_buf, len, rspi->chan_rx,
591 desc_rx = dmaengine_prep_slave_sg(rspi->chan_rx, &sg_rx, 1,
593 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
599 rspi_receive_init(rspi);
602 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
603 * called. So, this driver disables the IRQ while DMA transfer.
605 disable_irq(rspi->tx_irq);
606 if (rspi->rx_irq != rspi->tx_irq)
607 disable_irq(rspi->rx_irq);
609 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR);
610 rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
611 rspi->dma_callbacked = 0;
613 desc_rx->callback = rspi_dma_complete;
614 desc_rx->callback_param = rspi;
615 dmaengine_submit(desc_rx);
616 dma_async_issue_pending(rspi->chan_rx);
618 desc_tx->callback = NULL; /* No callback */
619 dmaengine_submit(desc_tx);
620 dma_async_issue_pending(rspi->chan_tx);
622 ret = wait_event_interruptible_timeout(rspi->wait,
623 rspi->dma_callbacked, HZ);
624 if (ret > 0 && rspi->dma_callbacked)
628 rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
630 enable_irq(rspi->tx_irq);
631 if (rspi->rx_irq != rspi->tx_irq)
632 enable_irq(rspi->rx_irq);
635 rspi_dma_unmap_sg(&sg_rx, rspi->chan_rx, DMA_FROM_DEVICE);
637 rspi_dma_unmap_sg(&sg_tx, rspi->chan_tx, DMA_TO_DEVICE);
641 static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t)
649 static int rspi_transfer_out_in(struct rspi_data *rspi,
650 struct spi_transfer *xfer)
655 spcr = rspi_read8(rspi, RSPI_SPCR);
657 rspi_receive_init(rspi);
662 rspi_write8(rspi, spcr, RSPI_SPCR);
664 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
668 /* Wait for the last transmission */
669 rspi_wait_for_tx_empty(rspi);
674 static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi,
675 struct spi_transfer *xfer)
677 struct rspi_data *rspi = spi_master_get_devdata(master);
679 if (!rspi_is_dma(rspi, xfer))
680 return rspi_transfer_out_in(rspi, xfer);
683 return rspi_send_receive_dma(rspi, xfer);
685 return rspi_send_dma(rspi, xfer);
688 static int rspi_rz_transfer_out_in(struct rspi_data *rspi,
689 struct spi_transfer *xfer)
693 rspi_rz_receive_init(rspi);
695 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
699 /* Wait for the last transmission */
700 rspi_wait_for_tx_empty(rspi);
705 static int rspi_rz_transfer_one(struct spi_master *master,
706 struct spi_device *spi,
707 struct spi_transfer *xfer)
709 struct rspi_data *rspi = spi_master_get_devdata(master);
711 return rspi_rz_transfer_out_in(rspi, xfer);
714 static int qspi_transfer_out_in(struct rspi_data *rspi,
715 struct spi_transfer *xfer)
719 qspi_receive_init(rspi);
721 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
725 /* Wait for the last transmission */
726 rspi_wait_for_tx_empty(rspi);
731 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
735 ret = rspi_pio_transfer(rspi, xfer->tx_buf, NULL, xfer->len);
739 /* Wait for the last transmission */
740 rspi_wait_for_tx_empty(rspi);
745 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
747 return rspi_pio_transfer(rspi, NULL, xfer->rx_buf, xfer->len);
750 static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,
751 struct spi_transfer *xfer)
753 struct rspi_data *rspi = spi_master_get_devdata(master);
755 if (spi->mode & SPI_LOOP) {
756 return qspi_transfer_out_in(rspi, xfer);
757 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
758 /* Quad or Dual SPI Write */
759 return qspi_transfer_out(rspi, xfer);
760 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
761 /* Quad or Dual SPI Read */
762 return qspi_transfer_in(rspi, xfer);
764 /* Single SPI Transfer */
765 return qspi_transfer_out_in(rspi, xfer);
769 static int rspi_setup(struct spi_device *spi)
771 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
773 rspi->max_speed_hz = spi->max_speed_hz;
775 rspi->spcmd = SPCMD_SSLKP;
776 if (spi->mode & SPI_CPOL)
777 rspi->spcmd |= SPCMD_CPOL;
778 if (spi->mode & SPI_CPHA)
779 rspi->spcmd |= SPCMD_CPHA;
781 /* CMOS output mode and MOSI signal from previous transfer */
783 if (spi->mode & SPI_LOOP)
784 rspi->sppcr |= SPPCR_SPLP;
786 set_config_register(rspi, 8);
791 static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
794 switch (xfer->tx_nbits) {
796 return SPCMD_SPIMOD_QUAD;
798 return SPCMD_SPIMOD_DUAL;
803 switch (xfer->rx_nbits) {
805 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
807 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
815 static int qspi_setup_sequencer(struct rspi_data *rspi,
816 const struct spi_message *msg)
818 const struct spi_transfer *xfer;
819 unsigned int i = 0, len = 0;
820 u16 current_mode = 0xffff, mode;
822 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
823 mode = qspi_transfer_mode(xfer);
824 if (mode == current_mode) {
829 /* Transfer mode change */
831 /* Set transfer data length of previous transfer */
832 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
835 if (i >= QSPI_NUM_SPCMD) {
836 dev_err(&msg->spi->dev,
837 "Too many different transfer modes");
841 /* Program transfer mode for this transfer */
842 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
848 /* Set final transfer data length and sequence length */
849 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
850 rspi_write8(rspi, i - 1, RSPI_SPSCR);
856 static int rspi_prepare_message(struct spi_master *master,
857 struct spi_message *msg)
859 struct rspi_data *rspi = spi_master_get_devdata(master);
863 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
864 /* Setup sequencer for messages with multiple transfer modes */
865 ret = qspi_setup_sequencer(rspi, msg);
870 /* Enable SPI function in master mode */
871 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
875 static int rspi_unprepare_message(struct spi_master *master,
876 struct spi_message *msg)
878 struct rspi_data *rspi = spi_master_get_devdata(master);
880 /* Disable SPI function */
881 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
883 /* Reset sequencer for Single SPI Transfers */
884 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
885 rspi_write8(rspi, 0, RSPI_SPSCR);
889 static irqreturn_t rspi_irq_mux(int irq, void *_sr)
891 struct rspi_data *rspi = _sr;
893 irqreturn_t ret = IRQ_NONE;
896 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
897 if (spsr & SPSR_SPRF)
898 disable_irq |= SPCR_SPRIE;
899 if (spsr & SPSR_SPTEF)
900 disable_irq |= SPCR_SPTIE;
904 rspi_disable_irq(rspi, disable_irq);
905 wake_up(&rspi->wait);
911 static irqreturn_t rspi_irq_rx(int irq, void *_sr)
913 struct rspi_data *rspi = _sr;
916 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
917 if (spsr & SPSR_SPRF) {
918 rspi_disable_irq(rspi, SPCR_SPRIE);
919 wake_up(&rspi->wait);
926 static irqreturn_t rspi_irq_tx(int irq, void *_sr)
928 struct rspi_data *rspi = _sr;
931 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
932 if (spsr & SPSR_SPTEF) {
933 rspi_disable_irq(rspi, SPCR_SPTIE);
934 wake_up(&rspi->wait);
941 static struct dma_chan *rspi_request_dma_chan(struct device *dev,
942 enum dma_transfer_direction dir,
944 dma_addr_t port_addr)
947 struct dma_chan *chan;
948 struct dma_slave_config cfg;
952 dma_cap_set(DMA_SLAVE, mask);
954 chan = dma_request_channel(mask, shdma_chan_filter,
955 (void *)(unsigned long)id);
957 dev_warn(dev, "dma_request_channel failed\n");
961 memset(&cfg, 0, sizeof(cfg));
964 if (dir == DMA_MEM_TO_DEV)
965 cfg.dst_addr = port_addr;
967 cfg.src_addr = port_addr;
969 ret = dmaengine_slave_config(chan, &cfg);
971 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
972 dma_release_channel(chan);
979 static int rspi_request_dma(struct device *dev, struct rspi_data *rspi,
980 const struct resource *res)
982 const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev);
984 if (!rspi_pd || !rspi_pd->dma_rx_id || !rspi_pd->dma_tx_id)
985 return 0; /* The driver assumes no error. */
987 rspi->chan_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM,
989 res->start + RSPI_SPDR);
993 rspi->chan_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV,
995 res->start + RSPI_SPDR);
996 if (!rspi->chan_tx) {
997 dma_release_channel(rspi->chan_rx);
998 rspi->chan_rx = NULL;
1002 dev_info(dev, "DMA available");
1006 static void rspi_release_dma(struct rspi_data *rspi)
1009 dma_release_channel(rspi->chan_tx);
1011 dma_release_channel(rspi->chan_rx);
1014 static int rspi_remove(struct platform_device *pdev)
1016 struct rspi_data *rspi = platform_get_drvdata(pdev);
1018 rspi_release_dma(rspi);
1019 pm_runtime_disable(&pdev->dev);
1024 static const struct spi_ops rspi_ops = {
1025 .set_config_register = rspi_set_config_register,
1026 .transfer_one = rspi_transfer_one,
1027 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1028 .flags = SPI_MASTER_MUST_TX,
1031 static const struct spi_ops rspi_rz_ops = {
1032 .set_config_register = rspi_rz_set_config_register,
1033 .transfer_one = rspi_rz_transfer_one,
1034 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1035 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
1038 static const struct spi_ops qspi_ops = {
1039 .set_config_register = qspi_set_config_register,
1040 .transfer_one = qspi_transfer_one,
1041 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP |
1042 SPI_TX_DUAL | SPI_TX_QUAD |
1043 SPI_RX_DUAL | SPI_RX_QUAD,
1044 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
1048 static const struct of_device_id rspi_of_match[] = {
1049 /* RSPI on legacy SH */
1050 { .compatible = "renesas,rspi", .data = &rspi_ops },
1051 /* RSPI on RZ/A1H */
1052 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1053 /* QSPI on R-Car Gen2 */
1054 { .compatible = "renesas,qspi", .data = &qspi_ops },
1058 MODULE_DEVICE_TABLE(of, rspi_of_match);
1060 static int rspi_parse_dt(struct device *dev, struct spi_master *master)
1065 /* Parse DT properties */
1066 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1068 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1072 master->num_chipselect = num_cs;
1076 #define rspi_of_match NULL
1077 static inline int rspi_parse_dt(struct device *dev, struct spi_master *master)
1081 #endif /* CONFIG_OF */
1083 static int rspi_request_irq(struct device *dev, unsigned int irq,
1084 irq_handler_t handler, const char *suffix,
1087 const char *base = dev_name(dev);
1088 size_t len = strlen(base) + strlen(suffix) + 2;
1089 char *name = devm_kzalloc(dev, len, GFP_KERNEL);
1092 snprintf(name, len, "%s:%s", base, suffix);
1093 return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1096 static int rspi_probe(struct platform_device *pdev)
1098 struct resource *res;
1099 struct spi_master *master;
1100 struct rspi_data *rspi;
1102 const struct of_device_id *of_id;
1103 const struct rspi_plat_data *rspi_pd;
1104 const struct spi_ops *ops;
1106 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
1107 if (master == NULL) {
1108 dev_err(&pdev->dev, "spi_alloc_master error.\n");
1112 of_id = of_match_device(rspi_of_match, &pdev->dev);
1115 ret = rspi_parse_dt(&pdev->dev, master);
1119 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1120 rspi_pd = dev_get_platdata(&pdev->dev);
1121 if (rspi_pd && rspi_pd->num_chipselect)
1122 master->num_chipselect = rspi_pd->num_chipselect;
1124 master->num_chipselect = 2; /* default */
1127 /* ops parameter check */
1128 if (!ops->set_config_register) {
1129 dev_err(&pdev->dev, "there is no set_config_register\n");
1134 rspi = spi_master_get_devdata(master);
1135 platform_set_drvdata(pdev, rspi);
1137 rspi->master = master;
1139 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1140 rspi->addr = devm_ioremap_resource(&pdev->dev, res);
1141 if (IS_ERR(rspi->addr)) {
1142 ret = PTR_ERR(rspi->addr);
1146 rspi->clk = devm_clk_get(&pdev->dev, NULL);
1147 if (IS_ERR(rspi->clk)) {
1148 dev_err(&pdev->dev, "cannot get clock\n");
1149 ret = PTR_ERR(rspi->clk);
1153 pm_runtime_enable(&pdev->dev);
1155 init_waitqueue_head(&rspi->wait);
1157 master->bus_num = pdev->id;
1158 master->setup = rspi_setup;
1159 master->auto_runtime_pm = true;
1160 master->transfer_one = ops->transfer_one;
1161 master->prepare_message = rspi_prepare_message;
1162 master->unprepare_message = rspi_unprepare_message;
1163 master->mode_bits = ops->mode_bits;
1164 master->flags = ops->flags;
1165 master->dev.of_node = pdev->dev.of_node;
1167 ret = platform_get_irq_byname(pdev, "rx");
1169 ret = platform_get_irq_byname(pdev, "mux");
1171 ret = platform_get_irq(pdev, 0);
1173 rspi->rx_irq = rspi->tx_irq = ret;
1176 ret = platform_get_irq_byname(pdev, "tx");
1181 dev_err(&pdev->dev, "platform_get_irq error\n");
1185 if (rspi->rx_irq == rspi->tx_irq) {
1186 /* Single multiplexed interrupt */
1187 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1190 /* Multi-interrupt mode, only SPRI and SPTI are used */
1191 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1194 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1195 rspi_irq_tx, "tx", rspi);
1198 dev_err(&pdev->dev, "request_irq error\n");
1202 ret = rspi_request_dma(&pdev->dev, rspi, res);
1204 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1206 ret = devm_spi_register_master(&pdev->dev, master);
1208 dev_err(&pdev->dev, "spi_register_master error.\n");
1212 dev_info(&pdev->dev, "probed\n");
1217 rspi_release_dma(rspi);
1219 pm_runtime_disable(&pdev->dev);
1221 spi_master_put(master);
1226 static struct platform_device_id spi_driver_ids[] = {
1227 { "rspi", (kernel_ulong_t)&rspi_ops },
1228 { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops },
1229 { "qspi", (kernel_ulong_t)&qspi_ops },
1233 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1235 static struct platform_driver rspi_driver = {
1236 .probe = rspi_probe,
1237 .remove = rspi_remove,
1238 .id_table = spi_driver_ids,
1240 .name = "renesas_spi",
1241 .owner = THIS_MODULE,
1242 .of_match_table = of_match_ptr(rspi_of_match),
1245 module_platform_driver(rspi_driver);
1247 MODULE_DESCRIPTION("Renesas RSPI bus driver");
1248 MODULE_LICENSE("GPL v2");
1249 MODULE_AUTHOR("Yoshihiro Shimoda");
1250 MODULE_ALIAS("platform:rspi");