drivers/spi/spi-rspi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SH RSPI driver
   4  *
   5  * Copyright (C) 2012, 2013  Renesas Solutions Corp.
   6  * Copyright (C) 2014 Glider bvba
   7  *
   8  * Based on spi-sh.c:
   9  * Copyright (C) 2011 Renesas Solutions Corp.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/sched.h>
  15 #include <linux/errno.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/io.h>
  19 #include <linux/clk.h>
  20 #include <linux/dmaengine.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/of.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/reset.h>
  25 #include <linux/sh_dma.h>
  26 #include <linux/spi/spi.h>
  27 #include <linux/spi/rspi.h>
  28 #include <linux/spinlock.h>
  29
  30 #define RSPI_SPCR               0x00    /* Control Register */
  31 #define RSPI_SSLP               0x01    /* Slave Select Polarity Register */
  32 #define RSPI_SPPCR              0x02    /* Pin Control Register */
  33 #define RSPI_SPSR               0x03    /* Status Register */
  34 #define RSPI_SPDR               0x04    /* Data Register */
  35 #define RSPI_SPSCR              0x08    /* Sequence Control Register */
  36 #define RSPI_SPSSR              0x09    /* Sequence Status Register */
  37 #define RSPI_SPBR               0x0a    /* Bit Rate Register */
  38 #define RSPI_SPDCR              0x0b    /* Data Control Register */
  39 #define RSPI_SPCKD              0x0c    /* Clock Delay Register */
  40 #define RSPI_SSLND              0x0d    /* Slave Select Negation Delay Register */
  41 #define RSPI_SPND               0x0e    /* Next-Access Delay Register */
  42 #define RSPI_SPCR2              0x0f    /* Control Register 2 (SH only) */
  43 #define RSPI_SPCMD0             0x10    /* Command Register 0 */
  44 #define RSPI_SPCMD1             0x12    /* Command Register 1 */
  45 #define RSPI_SPCMD2             0x14    /* Command Register 2 */
  46 #define RSPI_SPCMD3             0x16    /* Command Register 3 */
  47 #define RSPI_SPCMD4             0x18    /* Command Register 4 */
  48 #define RSPI_SPCMD5             0x1a    /* Command Register 5 */
  49 #define RSPI_SPCMD6             0x1c    /* Command Register 6 */
  50 #define RSPI_SPCMD7             0x1e    /* Command Register 7 */
  51 #define RSPI_SPCMD(i)           (RSPI_SPCMD0 + (i) * 2)
  52 #define RSPI_NUM_SPCMD          8
  53 #define RSPI_RZ_NUM_SPCMD       4
  54 #define QSPI_NUM_SPCMD          4
  55
  56 /* RSPI on RZ only */
  57 #define RSPI_SPBFCR             0x20    /* Buffer Control Register */
  58 #define RSPI_SPBFDR             0x22    /* Buffer Data Count Setting Register */
  59
  60 /* QSPI only */
  61 #define QSPI_SPBFCR             0x18    /* Buffer Control Register */
  62 #define QSPI_SPBDCR             0x1a    /* Buffer Data Count Register */
  63 #define QSPI_SPBMUL0            0x1c    /* Transfer Data Length Multiplier Setting Register 0 */
  64 #define QSPI_SPBMUL1            0x20    /* Transfer Data Length Multiplier Setting Register 1 */
  65 #define QSPI_SPBMUL2            0x24    /* Transfer Data Length Multiplier Setting Register 2 */
  66 #define QSPI_SPBMUL3            0x28    /* Transfer Data Length Multiplier Setting Register 3 */
  67 #define QSPI_SPBMUL(i)          (QSPI_SPBMUL0 + (i) * 4)
  68
  69 /* SPCR - Control Register */
  70 #define SPCR_SPRIE              0x80    /* Receive Interrupt Enable */
  71 #define SPCR_SPE                0x40    /* Function Enable */
  72 #define SPCR_SPTIE              0x20    /* Transmit Interrupt Enable */
  73 #define SPCR_SPEIE              0x10    /* Error Interrupt Enable */
  74 #define SPCR_MSTR               0x08    /* Master/Slave Mode Select */
  75 #define SPCR_MODFEN             0x04    /* Mode Fault Error Detection Enable */
  76 /* RSPI on SH only */
  77 #define SPCR_TXMD               0x02    /* TX Only Mode (vs. Full Duplex) */
  78 #define SPCR_SPMS               0x01    /* 3-wire Mode (vs. 4-wire) */
  79 /* QSPI on R-Car Gen2 only */
  80 #define SPCR_WSWAP              0x02    /* Word Swap of read-data for DMAC */
  81 #define SPCR_BSWAP              0x01    /* Byte Swap of read-data for DMAC */
  82
  83 /* SSLP - Slave Select Polarity Register */
  84 #define SSLP_SSLP(i)            BIT(i)  /* SSLi Signal Polarity Setting */
  85
  86 /* SPPCR - Pin Control Register */
  87 #define SPPCR_MOIFE             0x20    /* MOSI Idle Value Fixing Enable */
  88 #define SPPCR_MOIFV             0x10    /* MOSI Idle Fixed Value */
  89 #define SPPCR_SPOM              0x04
  90 #define SPPCR_SPLP2             0x02    /* Loopback Mode 2 (non-inverting) */
  91 #define SPPCR_SPLP              0x01    /* Loopback Mode (inverting) */
  92
  93 #define SPPCR_IO3FV             0x04    /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
  94 #define SPPCR_IO2FV             0x04    /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
  95
  96 /* SPSR - Status Register */
  97 #define SPSR_SPRF               0x80    /* Receive Buffer Full Flag */
  98 #define SPSR_TEND               0x40    /* Transmit End */
  99 #define SPSR_SPTEF              0x20    /* Transmit Buffer Empty Flag */
 100 #define SPSR_PERF               0x08    /* Parity Error Flag */
 101 #define SPSR_MODF               0x04    /* Mode Fault Error Flag */
 102 #define SPSR_IDLNF              0x02    /* RSPI Idle Flag */
 103 #define SPSR_OVRF               0x01    /* Overrun Error Flag (RSPI only) */
 104
 105 /* SPSCR - Sequence Control Register */
 106 #define SPSCR_SPSLN_MASK        0x07    /* Sequence Length Specification */
 107
 108 /* SPSSR - Sequence Status Register */
 109 #define SPSSR_SPECM_MASK        0x70    /* Command Error Mask */
 110 #define SPSSR_SPCP_MASK         0x07    /* Command Pointer Mask */
 111
 112 /* SPDCR - Data Control Register */
 113 #define SPDCR_TXDMY             0x80    /* Dummy Data Transmission Enable */
 114 #define SPDCR_SPLW1             0x40    /* Access Width Specification (RZ) */
 115 #define SPDCR_SPLW0             0x20    /* Access Width Specification (RZ) */
 116 #define SPDCR_SPLLWORD          (SPDCR_SPLW1 | SPDCR_SPLW0)
 117 #define SPDCR_SPLWORD           SPDCR_SPLW1
 118 #define SPDCR_SPLBYTE           SPDCR_SPLW0
 119 #define SPDCR_SPLW              0x20    /* Access Width Specification (SH) */
 120 #define SPDCR_SPRDTD            0x10    /* Receive Transmit Data Select (SH) */
 121 #define SPDCR_SLSEL1            0x08
 122 #define SPDCR_SLSEL0            0x04
 123 #define SPDCR_SLSEL_MASK        0x0c    /* SSL1 Output Select (SH) */
 124 #define SPDCR_SPFC1             0x02
 125 #define SPDCR_SPFC0             0x01
 126 #define SPDCR_SPFC_MASK         0x03    /* Frame Count Setting (1-4) (SH) */
 127
 128 /* SPCKD - Clock Delay Register */
 129 #define SPCKD_SCKDL_MASK        0x07    /* Clock Delay Setting (1-8) */
 130
 131 /* SSLND - Slave Select Negation Delay Register */
 132 #define SSLND_SLNDL_MASK        0x07    /* SSL Negation Delay Setting (1-8) */
 133
 134 /* SPND - Next-Access Delay Register */
 135 #define SPND_SPNDL_MASK         0x07    /* Next-Access Delay Setting (1-8) */
 136
 137 /* SPCR2 - Control Register 2 */
 138 #define SPCR2_PTE               0x08    /* Parity Self-Test Enable */
 139 #define SPCR2_SPIE              0x04    /* Idle Interrupt Enable */
 140 #define SPCR2_SPOE              0x02    /* Odd Parity Enable (vs. Even) */
 141 #define SPCR2_SPPE              0x01    /* Parity Enable */
 142
 143 /* SPCMDn - Command Registers */
 144 #define SPCMD_SCKDEN            0x8000  /* Clock Delay Setting Enable */
 145 #define SPCMD_SLNDEN            0x4000  /* SSL Negation Delay Setting Enable */
 146 #define SPCMD_SPNDEN            0x2000  /* Next-Access Delay Enable */
 147 #define SPCMD_LSBF              0x1000  /* LSB First */
 148 #define SPCMD_SPB_MASK          0x0f00  /* Data Length Setting */
 149 #define SPCMD_SPB_8_TO_16(bit)  (((bit - 1) << 8) & SPCMD_SPB_MASK)
 150 #define SPCMD_SPB_8BIT          0x0000  /* QSPI only */
 151 #define SPCMD_SPB_16BIT         0x0100
 152 #define SPCMD_SPB_20BIT         0x0000
 153 #define SPCMD_SPB_24BIT         0x0100
 154 #define SPCMD_SPB_32BIT         0x0200
 155 #define SPCMD_SSLKP             0x0080  /* SSL Signal Level Keeping */
 156 #define SPCMD_SPIMOD_MASK       0x0060  /* SPI Operating Mode (QSPI only) */
 157 #define SPCMD_SPIMOD1           0x0040
 158 #define SPCMD_SPIMOD0           0x0020
 159 #define SPCMD_SPIMOD_SINGLE     0
 160 #define SPCMD_SPIMOD_DUAL       SPCMD_SPIMOD0
 161 #define SPCMD_SPIMOD_QUAD       SPCMD_SPIMOD1
 162 #define SPCMD_SPRW              0x0010  /* SPI Read/Write Access (Dual/Quad) */
 163 #define SPCMD_SSLA(i)           ((i) << 4)      /* SSL Assert Signal Setting */
 164 #define SPCMD_BRDV_MASK         0x000c  /* Bit Rate Division Setting */
 165 #define SPCMD_BRDV(brdv)        ((brdv) << 2)
 166 #define SPCMD_CPOL              0x0002  /* Clock Polarity Setting */
 167 #define SPCMD_CPHA              0x0001  /* Clock Phase Setting */
 168
 169 /* SPBFCR - Buffer Control Register */
 170 #define SPBFCR_TXRST            0x80    /* Transmit Buffer Data Reset */
 171 #define SPBFCR_RXRST            0x40    /* Receive Buffer Data Reset */
 172 #define SPBFCR_TXTRG_MASK       0x30    /* Transmit Buffer Data Triggering Number */
 173 #define SPBFCR_RXTRG_MASK       0x07    /* Receive Buffer Data Triggering Number */
 174 /* QSPI on R-Car Gen2 */
 175 #define SPBFCR_TXTRG_1B         0x00    /* 31 bytes (1 byte available) */
 176 #define SPBFCR_TXTRG_32B        0x30    /* 0 byte (32 bytes available) */
 177 #define SPBFCR_RXTRG_1B         0x00    /* 1 byte (31 bytes available) */
 178 #define SPBFCR_RXTRG_32B        0x07    /* 32 bytes (0 byte available) */
 179
 180 #define QSPI_BUFFER_SIZE        32u
 181
 182 struct rspi_data {
 183         void __iomem *addr;
 184         u32 speed_hz;
 185         struct spi_controller *ctlr;
 186         struct platform_device *pdev;
 187         wait_queue_head_t wait;
 188         spinlock_t lock;                /* Protects RMW-access to RSPI_SSLP */
 189         struct clk *clk;
 190         u16 spcmd;
 191         u8 spsr;
 192         u8 sppcr;
 193         int rx_irq, tx_irq;
 194         const struct spi_ops *ops;
 195
 196         unsigned dma_callbacked:1;
 197         unsigned byte_access:1;
 198 };
 199
 200 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
 201 {
 202         iowrite8(data, rspi->addr + offset);
 203 }
 204
 205 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
 206 {
 207         iowrite16(data, rspi->addr + offset);
 208 }
 209
 210 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
 211 {
 212         iowrite32(data, rspi->addr + offset);
 213 }
 214
 215 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
 216 {
 217         return ioread8(rspi->addr + offset);
 218 }
 219
 220 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
 221 {
 222         return ioread16(rspi->addr + offset);
 223 }
 224
 225 static void rspi_write_data(const struct rspi_data *rspi, u16 data)
 226 {
 227         if (rspi->byte_access)
 228                 rspi_write8(rspi, data, RSPI_SPDR);
 229         else /* 16 bit */
 230                 rspi_write16(rspi, data, RSPI_SPDR);
 231 }
 232
 233 static u16 rspi_read_data(const struct rspi_data *rspi)
 234 {
 235         if (rspi->byte_access)
 236                 return rspi_read8(rspi, RSPI_SPDR);
 237         else /* 16 bit */
 238                 return rspi_read16(rspi, RSPI_SPDR);
 239 }
 240
 241 /* optional functions */
 242 struct spi_ops {
 243         int (*set_config_register)(struct rspi_data *rspi, int access_size);
 244         int (*transfer_one)(struct spi_controller *ctlr,
 245                             struct spi_device *spi, struct spi_transfer *xfer);
 246         u16 extra_mode_bits;
 247         u16 min_div;
 248         u16 max_div;
 249         u16 flags;
 250         u16 fifo_size;
 251         u8 num_hw_ss;
 252 };
 253
 254 static void rspi_set_rate(struct rspi_data *rspi)
 255 {
 256         unsigned long clksrc;
 257         int brdv = 0, spbr;
 258
 259         clksrc = clk_get_rate(rspi->clk);
 260         spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1;
 261         while (spbr > 255 && brdv < 3) {
 262                 brdv++;
 263                 spbr = DIV_ROUND_UP(spbr + 1, 2) - 1;
 264         }
 265
 266         rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
 267         rspi->spcmd |= SPCMD_BRDV(brdv);
 268         rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * (spbr + 1));
 269 }
 270
 271 /*
 272  * functions for RSPI on legacy SH
 273  */
 274 static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
 275 {
 276         /* Sets output mode, MOSI signal, and (optionally) loopback */
 277         rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
 278
 279         /* Sets transfer bit rate */
 280         rspi_set_rate(rspi);
 281
 282         /* Disable dummy transmission, set 16-bit word access, 1 frame */
 283         rspi_write8(rspi, 0, RSPI_SPDCR);
 284         rspi->byte_access = 0;
 285
 286         /* Sets RSPCK, SSL, next-access delay value */
 287         rspi_write8(rspi, 0x00, RSPI_SPCKD);
 288         rspi_write8(rspi, 0x00, RSPI_SSLND);
 289         rspi_write8(rspi, 0x00, RSPI_SPND);
 290
 291         /* Sets parity, interrupt mask */
 292         rspi_write8(rspi, 0x00, RSPI_SPCR2);
 293
 294         /* Resets sequencer */
 295         rspi_write8(rspi, 0, RSPI_SPSCR);
 296         rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
 297         rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
 298
 299         /* Sets RSPI mode */
 300         rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
 301
 302         return 0;
 303 }
 304
 305 /*
 306  * functions for RSPI on RZ
 307  */
 308 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
 309 {
 310         /* Sets output mode, MOSI signal, and (optionally) loopback */
 311         rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
 312
 313         /* Sets transfer bit rate */
 314         rspi_set_rate(rspi);
 315
 316         /* Disable dummy transmission, set byte access */
 317         rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
 318         rspi->byte_access = 1;
 319
 320         /* Sets RSPCK, SSL, next-access delay value */
 321         rspi_write8(rspi, 0x00, RSPI_SPCKD);
 322         rspi_write8(rspi, 0x00, RSPI_SSLND);
 323         rspi_write8(rspi, 0x00, RSPI_SPND);
 324
 325         /* Resets sequencer */
 326         rspi_write8(rspi, 0, RSPI_SPSCR);
 327         rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
 328         rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
 329
 330         /* Sets RSPI mode */
 331         rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
 332
 333         return 0;
 334 }
 335
 336 /*
 337  * functions for QSPI
 338  */
 339 static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
 340 {
 341         unsigned long clksrc;
 342         int brdv = 0, spbr;
 343
 344         /* Sets output mode, MOSI signal, and (optionally) loopback */
 345         rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
 346
 347         /* Sets transfer bit rate */
 348         clksrc = clk_get_rate(rspi->clk);
 349         if (rspi->speed_hz >= clksrc) {
 350                 spbr = 0;
 351                 rspi->speed_hz = clksrc;
 352         } else {
 353                 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz);
 354                 while (spbr > 255 && brdv < 3) {
 355                         brdv++;
 356                         spbr = DIV_ROUND_UP(spbr, 2);
 357                 }
 358                 spbr = clamp(spbr, 0, 255);
 359                 rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * spbr);
 360         }
 361         rspi_write8(rspi, spbr, RSPI_SPBR);
 362         rspi->spcmd |= SPCMD_BRDV(brdv);
 363
 364         /* Disable dummy transmission, set byte access */
 365         rspi_write8(rspi, 0, RSPI_SPDCR);
 366         rspi->byte_access = 1;
 367
 368         /* Sets RSPCK, SSL, next-access delay value */
 369         rspi_write8(rspi, 0x00, RSPI_SPCKD);
 370         rspi_write8(rspi, 0x00, RSPI_SSLND);
 371         rspi_write8(rspi, 0x00, RSPI_SPND);
 372
 373         /* Data Length Setting */
 374         if (access_size == 8)
 375                 rspi->spcmd |= SPCMD_SPB_8BIT;
 376         else if (access_size == 16)
 377                 rspi->spcmd |= SPCMD_SPB_16BIT;
 378         else
 379                 rspi->spcmd |= SPCMD_SPB_32BIT;
 380
 381         rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
 382
 383         /* Resets transfer data length */
 384         rspi_write32(rspi, 0, QSPI_SPBMUL0);
 385
 386         /* Resets transmit and receive buffer */
 387         rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
 388         /* Sets buffer to allow normal operation */
 389         rspi_write8(rspi, 0x00, QSPI_SPBFCR);
 390
 391         /* Resets sequencer */
 392         rspi_write8(rspi, 0, RSPI_SPSCR);
 393         rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
 394
 395         /* Sets RSPI mode */
 396         rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
 397
 398         return 0;
 399 }
 400
 401 static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg)
 402 {
 403         u8 data;
 404
 405         data = rspi_read8(rspi, reg);
 406         data &= ~mask;
 407         data |= (val & mask);
 408         rspi_write8(rspi, data, reg);
 409 }
 410
 411 static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
 412                                           unsigned int len)
 413 {
 414         unsigned int n;
 415
 416         n = min(len, QSPI_BUFFER_SIZE);
 417
 418         if (len >= QSPI_BUFFER_SIZE) {
 419                 /* sets triggering number to 32 bytes */
 420                 qspi_update(rspi, SPBFCR_TXTRG_MASK,
 421                              SPBFCR_TXTRG_32B, QSPI_SPBFCR);
 422         } else {
 423                 /* sets triggering number to 1 byte */
 424                 qspi_update(rspi, SPBFCR_TXTRG_MASK,
 425                              SPBFCR_TXTRG_1B, QSPI_SPBFCR);
 426         }
 427
 428         return n;
 429 }
 430
 431 static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
 432 {
 433         unsigned int n;
 434
 435         n = min(len, QSPI_BUFFER_SIZE);
 436
 437         if (len >= QSPI_BUFFER_SIZE) {
 438                 /* sets triggering number to 32 bytes */
 439                 qspi_update(rspi, SPBFCR_RXTRG_MASK,
 440                              SPBFCR_RXTRG_32B, QSPI_SPBFCR);
 441         } else {
 442                 /* sets triggering number to 1 byte */
 443                 qspi_update(rspi, SPBFCR_RXTRG_MASK,
 444                              SPBFCR_RXTRG_1B, QSPI_SPBFCR);
 445         }
 446         return n;
 447 }
 448
 449 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
 450 {
 451         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
 452 }
 453
 454 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
 455 {
 456         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
 457 }
 458
 459 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
 460                                    u8 enable_bit)
 461 {
 462         int ret;
 463
 464         rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
 465         if (rspi->spsr & wait_mask)
 466                 return 0;
 467
 468         rspi_enable_irq(rspi, enable_bit);
 469         ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
 470         if (ret == 0 && !(rspi->spsr & wait_mask))
 471                 return -ETIMEDOUT;
 472
 473         return 0;
 474 }
 475
 476 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
 477 {
 478         return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
 479 }
 480
 481 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
 482 {
 483         return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
 484 }
 485
 486 static int rspi_data_out(struct rspi_data *rspi, u8 data)
 487 {
 488         int error = rspi_wait_for_tx_empty(rspi);
 489         if (error < 0) {
 490                 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
 491                 return error;
 492         }
 493         rspi_write_data(rspi, data);
 494         return 0;
 495 }
 496
 497 static int rspi_data_in(struct rspi_data *rspi)
 498 {
 499         int error;
 500         u8 data;
 501
 502         error = rspi_wait_for_rx_full(rspi);
 503         if (error < 0) {
 504                 dev_err(&rspi->ctlr->dev, "receive timeout\n");
 505                 return error;
 506         }
 507         data = rspi_read_data(rspi);
 508         return data;
 509 }
 510
 511 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
 512                              unsigned int n)
 513 {
 514         while (n-- > 0) {
 515                 if (tx) {
 516                         int ret = rspi_data_out(rspi, *tx++);
 517                         if (ret < 0)
 518                                 return ret;
 519                 }
 520                 if (rx) {
 521                         int ret = rspi_data_in(rspi);
 522                         if (ret < 0)
 523                                 return ret;
 524                         *rx++ = ret;
 525                 }
 526         }
 527
 528         return 0;
 529 }
 530
 531 static void rspi_dma_complete(void *arg)
 532 {
 533         struct rspi_data *rspi = arg;
 534
 535         rspi->dma_callbacked = 1;
 536         wake_up_interruptible(&rspi->wait);
 537 }
 538
 539 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
 540                              struct sg_table *rx)
 541 {
 542         struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
 543         u8 irq_mask = 0;
 544         unsigned int other_irq = 0;
 545         dma_cookie_t cookie;
 546         int ret;
 547
 548         /* First prepare and submit the DMA request(s), as this may fail */
 549         if (rx) {
 550                 desc_rx = dmaengine_prep_slave_sg(rspi->ctlr->dma_rx, rx->sgl,
 551                                         rx->nents, DMA_DEV_TO_MEM,
 552                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 553                 if (!desc_rx) {
 554                         ret = -EAGAIN;
 555                         goto no_dma_rx;
 556                 }
 557
 558                 desc_rx->callback = rspi_dma_complete;
 559                 desc_rx->callback_param = rspi;
 560                 cookie = dmaengine_submit(desc_rx);
 561                 if (dma_submit_error(cookie)) {
 562                         ret = cookie;
 563                         goto no_dma_rx;
 564                 }
 565
 566                 irq_mask |= SPCR_SPRIE;
 567         }
 568
 569         if (tx) {
 570                 desc_tx = dmaengine_prep_slave_sg(rspi->ctlr->dma_tx, tx->sgl,
 571                                         tx->nents, DMA_MEM_TO_DEV,
 572                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 573                 if (!desc_tx) {
 574                         ret = -EAGAIN;
 575                         goto no_dma_tx;
 576                 }
 577
 578                 if (rx) {
 579                         /* No callback */
 580                         desc_tx->callback = NULL;
 581                 } else {
 582                         desc_tx->callback = rspi_dma_complete;
 583                         desc_tx->callback_param = rspi;
 584                 }
 585                 cookie = dmaengine_submit(desc_tx);
 586                 if (dma_submit_error(cookie)) {
 587                         ret = cookie;
 588                         goto no_dma_tx;
 589                 }
 590
 591                 irq_mask |= SPCR_SPTIE;
 592         }
 593
 594         /*
 595          * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be
 596          * called. So, this driver disables the IRQ while DMA transfer.
 597          */
 598         if (tx)
 599                 disable_irq(other_irq = rspi->tx_irq);
 600         if (rx && rspi->rx_irq != other_irq)
 601                 disable_irq(rspi->rx_irq);
 602
 603         rspi_enable_irq(rspi, irq_mask);
 604         rspi->dma_callbacked = 0;
 605
 606         /* Now start DMA */
 607         if (rx)
 608                 dma_async_issue_pending(rspi->ctlr->dma_rx);
 609         if (tx)
 610                 dma_async_issue_pending(rspi->ctlr->dma_tx);
 611
 612         ret = wait_event_interruptible_timeout(rspi->wait,
 613                                                rspi->dma_callbacked, HZ);
 614         if (ret > 0 && rspi->dma_callbacked) {
 615                 ret = 0;
 616                 if (tx)
 617                         dmaengine_synchronize(rspi->ctlr->dma_tx);
 618                 if (rx)
 619                         dmaengine_synchronize(rspi->ctlr->dma_rx);
 620         } else {
 621                 if (!ret) {
 622                         dev_err(&rspi->ctlr->dev, "DMA timeout\n");
 623                         ret = -ETIMEDOUT;
 624                 }
 625                 if (tx)
 626                         dmaengine_terminate_sync(rspi->ctlr->dma_tx);
 627                 if (rx)
 628                         dmaengine_terminate_sync(rspi->ctlr->dma_rx);
 629         }
 630
 631         rspi_disable_irq(rspi, irq_mask);
 632
 633         if (tx)
 634                 enable_irq(rspi->tx_irq);
 635         if (rx && rspi->rx_irq != other_irq)
 636                 enable_irq(rspi->rx_irq);
 637
 638         return ret;
 639
 640 no_dma_tx:
 641         if (rx)
 642                 dmaengine_terminate_sync(rspi->ctlr->dma_rx);
 643 no_dma_rx:
 644         if (ret == -EAGAIN) {
 645                 dev_warn_once(&rspi->ctlr->dev,
 646                               "DMA not available, falling back to PIO\n");
 647         }
 648         return ret;
 649 }
 650
 651 static void rspi_receive_init(const struct rspi_data *rspi)
 652 {
 653         u8 spsr;
 654
 655         spsr = rspi_read8(rspi, RSPI_SPSR);
 656         if (spsr & SPSR_SPRF)
 657                 rspi_read_data(rspi);   /* dummy read */
 658         if (spsr & SPSR_OVRF)
 659                 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
 660                             RSPI_SPSR);
 661 }
 662
 663 static void rspi_rz_receive_init(const struct rspi_data *rspi)
 664 {
 665         rspi_receive_init(rspi);
 666         rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
 667         rspi_write8(rspi, 0, RSPI_SPBFCR);
 668 }
 669
 670 static void qspi_receive_init(const struct rspi_data *rspi)
 671 {
 672         u8 spsr;
 673
 674         spsr = rspi_read8(rspi, RSPI_SPSR);
 675         if (spsr & SPSR_SPRF)
 676                 rspi_read_data(rspi);   /* dummy read */
 677         rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
 678         rspi_write8(rspi, 0, QSPI_SPBFCR);
 679 }
 680
 681 static bool __rspi_can_dma(const struct rspi_data *rspi,
 682                            const struct spi_transfer *xfer)
 683 {
 684         return xfer->len > rspi->ops->fifo_size;
 685 }
 686
 687 static bool rspi_can_dma(struct spi_controller *ctlr, struct spi_device *spi,
 688                          struct spi_transfer *xfer)
 689 {
 690         struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
 691
 692         return __rspi_can_dma(rspi, xfer);
 693 }
 694
 695 static int rspi_dma_check_then_transfer(struct rspi_data *rspi,
 696                                          struct spi_transfer *xfer)
 697 {
 698         if (!rspi->ctlr->can_dma || !__rspi_can_dma(rspi, xfer))
 699                 return -EAGAIN;
 700
 701         /* rx_buf can be NULL on RSPI on SH in TX-only Mode */
 702         return rspi_dma_transfer(rspi, &xfer->tx_sg,
 703                                 xfer->rx_buf ? &xfer->rx_sg : NULL);
 704 }
 705
 706 static int rspi_common_transfer(struct rspi_data *rspi,
 707                                 struct spi_transfer *xfer)
 708 {
 709         int ret;
 710
 711         xfer->effective_speed_hz = rspi->speed_hz;
 712
 713         ret = rspi_dma_check_then_transfer(rspi, xfer);
 714         if (ret != -EAGAIN)
 715                 return ret;
 716
 717         ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
 718         if (ret < 0)
 719                 return ret;
 720
 721         /* Wait for the last transmission */
 722         rspi_wait_for_tx_empty(rspi);
 723
 724         return 0;
 725 }
 726
 727 static int rspi_transfer_one(struct spi_controller *ctlr,
 728                              struct spi_device *spi, struct spi_transfer *xfer)
 729 {
 730         struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
 731         u8 spcr;
 732
 733         spcr = rspi_read8(rspi, RSPI_SPCR);
 734         if (xfer->rx_buf) {
 735                 rspi_receive_init(rspi);
 736                 spcr &= ~SPCR_TXMD;
 737         } else {
 738                 spcr |= SPCR_TXMD;
 739         }
 740         rspi_write8(rspi, spcr, RSPI_SPCR);
 741
 742         return rspi_common_transfer(rspi, xfer);
 743 }
 744
 745 static int rspi_rz_transfer_one(struct spi_controller *ctlr,
 746                                 struct spi_device *spi,
 747                                 struct spi_transfer *xfer)
 748 {
 749         struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
 750
 751         rspi_rz_receive_init(rspi);
 752
 753         return rspi_common_transfer(rspi, xfer);
 754 }
 755
 756 static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx,
 757                                         u8 *rx, unsigned int len)
 758 {
 759         unsigned int i, n;
 760         int ret;
 761
 762         while (len > 0) {
 763                 n = qspi_set_send_trigger(rspi, len);
 764                 qspi_set_receive_trigger(rspi, len);
 765                 ret = rspi_wait_for_tx_empty(rspi);
 766                 if (ret < 0) {
 767                         dev_err(&rspi->ctlr->dev, "transmit timeout\n");
 768                         return ret;
 769                 }
 770                 for (i = 0; i < n; i++)
 771                         rspi_write_data(rspi, *tx++);
 772
 773                 ret = rspi_wait_for_rx_full(rspi);
 774                 if (ret < 0) {
 775                         dev_err(&rspi->ctlr->dev, "receive timeout\n");
 776                         return ret;
 777                 }
 778                 for (i = 0; i < n; i++)
 779                         *rx++ = rspi_read_data(rspi);
 780
 781                 len -= n;
 782         }
 783
 784         return 0;
 785 }
 786
 787 static int qspi_transfer_out_in(struct rspi_data *rspi,
 788                                 struct spi_transfer *xfer)
 789 {
 790         int ret;
 791
 792         qspi_receive_init(rspi);
 793
 794         ret = rspi_dma_check_then_transfer(rspi, xfer);
 795         if (ret != -EAGAIN)
 796                 return ret;
 797
 798         return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf,
 799                                             xfer->rx_buf, xfer->len);
 800 }
 801
 802 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
 803 {
 804         const u8 *tx = xfer->tx_buf;
 805         unsigned int n = xfer->len;
 806         unsigned int i, len;
 807         int ret;
 808
 809         if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
 810                 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
 811                 if (ret != -EAGAIN)
 812                         return ret;
 813         }
 814
 815         while (n > 0) {
 816                 len = qspi_set_send_trigger(rspi, n);
 817                 ret = rspi_wait_for_tx_empty(rspi);
 818                 if (ret < 0) {
 819                         dev_err(&rspi->ctlr->dev, "transmit timeout\n");
 820                         return ret;
 821                 }
 822                 for (i = 0; i < len; i++)
 823                         rspi_write_data(rspi, *tx++);
 824
 825                 n -= len;
 826         }
 827
 828         /* Wait for the last transmission */
 829         rspi_wait_for_tx_empty(rspi);
 830
 831         return 0;
 832 }
 833
 834 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
 835 {
 836         u8 *rx = xfer->rx_buf;
 837         unsigned int n = xfer->len;
 838         unsigned int i, len;
 839         int ret;
 840
 841         if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
 842                 ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
 843                 if (ret != -EAGAIN)
 844                         return ret;
 845         }
 846
 847         while (n > 0) {
 848                 len = qspi_set_receive_trigger(rspi, n);
 849                 ret = rspi_wait_for_rx_full(rspi);
 850                 if (ret < 0) {
 851                         dev_err(&rspi->ctlr->dev, "receive timeout\n");
 852                         return ret;
 853                 }
 854                 for (i = 0; i < len; i++)
 855                         *rx++ = rspi_read_data(rspi);
 856
 857                 n -= len;
 858         }
 859
 860         return 0;
 861 }
 862
 863 static int qspi_transfer_one(struct spi_controller *ctlr,
 864                              struct spi_device *spi, struct spi_transfer *xfer)
 865 {
 866         struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
 867
 868         xfer->effective_speed_hz = rspi->speed_hz;
 869         if (spi->mode & SPI_LOOP) {
 870                 return qspi_transfer_out_in(rspi, xfer);
 871         } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
 872                 /* Quad or Dual SPI Write */
 873                 return qspi_transfer_out(rspi, xfer);
 874         } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
 875                 /* Quad or Dual SPI Read */
 876                 return qspi_transfer_in(rspi, xfer);
 877         } else {
 878                 /* Single SPI Transfer */
 879                 return qspi_transfer_out_in(rspi, xfer);
 880         }
 881 }
 882
 883 static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
 884 {
 885         if (xfer->tx_buf)
 886                 switch (xfer->tx_nbits) {
 887                 case SPI_NBITS_QUAD:
 888                         return SPCMD_SPIMOD_QUAD;
 889                 case SPI_NBITS_DUAL:
 890                         return SPCMD_SPIMOD_DUAL;
 891                 default:
 892                         return 0;
 893                 }
 894         if (xfer->rx_buf)
 895                 switch (xfer->rx_nbits) {
 896                 case SPI_NBITS_QUAD:
 897                         return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
 898                 case SPI_NBITS_DUAL:
 899                         return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
 900                 default:
 901                         return 0;
 902                 }
 903
 904         return 0;
 905 }
 906
 907 static int qspi_setup_sequencer(struct rspi_data *rspi,
 908                                 const struct spi_message *msg)
 909 {
 910         const struct spi_transfer *xfer;
 911         unsigned int i = 0, len = 0;
 912         u16 current_mode = 0xffff, mode;
 913
 914         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 915                 mode = qspi_transfer_mode(xfer);
 916                 if (mode == current_mode) {
 917                         len += xfer->len;
 918                         continue;
 919                 }
 920
 921                 /* Transfer mode change */
 922                 if (i) {
 923                         /* Set transfer data length of previous transfer */
 924                         rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
 925                 }
 926
 927                 if (i >= QSPI_NUM_SPCMD) {
 928                         dev_err(&msg->spi->dev,
 929                                 "Too many different transfer modes");
 930                         return -EINVAL;
 931                 }
 932
 933                 /* Program transfer mode for this transfer */
 934                 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
 935                 current_mode = mode;
 936                 len = xfer->len;
 937                 i++;
 938         }
 939         if (i) {
 940                 /* Set final transfer data length and sequence length */
 941                 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
 942                 rspi_write8(rspi, i - 1, RSPI_SPSCR);
 943         }
 944
 945         return 0;
 946 }
 947
 948 static int rspi_setup(struct spi_device *spi)
 949 {
 950         struct rspi_data *rspi = spi_controller_get_devdata(spi->controller);
 951         u8 sslp;
 952
 953         if (spi_get_csgpiod(spi, 0))
 954                 return 0;
 955
 956         pm_runtime_get_sync(&rspi->pdev->dev);
 957         spin_lock_irq(&rspi->lock);
 958
 959         sslp = rspi_read8(rspi, RSPI_SSLP);
 960         if (spi->mode & SPI_CS_HIGH)
 961                 sslp |= SSLP_SSLP(spi_get_chipselect(spi, 0));
 962         else
 963                 sslp &= ~SSLP_SSLP(spi_get_chipselect(spi, 0));
 964         rspi_write8(rspi, sslp, RSPI_SSLP);
 965
 966         spin_unlock_irq(&rspi->lock);
 967         pm_runtime_put(&rspi->pdev->dev);
 968         return 0;
 969 }
 970
 971 static int rspi_prepare_message(struct spi_controller *ctlr,
 972                                 struct spi_message *msg)
 973 {
 974         struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
 975         struct spi_device *spi = msg->spi;
 976         const struct spi_transfer *xfer;
 977         int ret;
 978
 979         /*
 980          * As the Bit Rate Register must not be changed while the device is
 981          * active, all transfers in a message must use the same bit rate.
 982          * In theory, the sequencer could be enabled, and each Command Register
 983          * could divide the base bit rate by a different value.
 984          * However, most RSPI variants do not have Transfer Data Length
 985          * Multiplier Setting Registers, so each sequence step would be limited
 986          * to a single word, making this feature unsuitable for large
 987          * transfers, which would gain most from it.
 988          */
 989         rspi->speed_hz = spi->max_speed_hz;
 990         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 991                 if (xfer->speed_hz < rspi->speed_hz)
 992                         rspi->speed_hz = xfer->speed_hz;
 993         }
 994
 995         rspi->spcmd = SPCMD_SSLKP;
 996         if (spi->mode & SPI_CPOL)
 997                 rspi->spcmd |= SPCMD_CPOL;
 998         if (spi->mode & SPI_CPHA)
 999                 rspi->spcmd |= SPCMD_CPHA;
1000         if (spi->mode & SPI_LSB_FIRST)
1001                 rspi->spcmd |= SPCMD_LSBF;
1002
1003         /* Configure slave signal to assert */
1004         rspi->spcmd |= SPCMD_SSLA(spi_get_csgpiod(spi, 0) ? rspi->ctlr->unused_native_cs
1005                                                 : spi_get_chipselect(spi, 0));
1006
1007         /* CMOS output mode and MOSI signal from previous transfer */
1008         rspi->sppcr = 0;
1009         if (spi->mode & SPI_LOOP)
1010                 rspi->sppcr |= SPPCR_SPLP;
1011
1012         rspi->ops->set_config_register(rspi, 8);
1013
1014         if (msg->spi->mode &
1015             (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
1016                 /* Setup sequencer for messages with multiple transfer modes */
1017                 ret = qspi_setup_sequencer(rspi, msg);
1018                 if (ret < 0)
1019                         return ret;
1020         }
1021
1022         /* Enable SPI function in master mode */
1023         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
1024         return 0;
1025 }
1026
1027 static int rspi_unprepare_message(struct spi_controller *ctlr,
1028                                   struct spi_message *msg)
1029 {
1030         struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
1031
1032         /* Disable SPI function */
1033         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
1034
1035         /* Reset sequencer for Single SPI Transfers */
1036         rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
1037         rspi_write8(rspi, 0, RSPI_SPSCR);
1038         return 0;
1039 }
1040
1041 static irqreturn_t rspi_irq_mux(int irq, void *_sr)
1042 {
1043         struct rspi_data *rspi = _sr;
1044         u8 spsr;
1045         irqreturn_t ret = IRQ_NONE;
1046         u8 disable_irq = 0;
1047
1048         rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1049         if (spsr & SPSR_SPRF)
1050                 disable_irq |= SPCR_SPRIE;
1051         if (spsr & SPSR_SPTEF)
1052                 disable_irq |= SPCR_SPTIE;
1053
1054         if (disable_irq) {
1055                 ret = IRQ_HANDLED;
1056                 rspi_disable_irq(rspi, disable_irq);
1057                 wake_up(&rspi->wait);
1058         }
1059
1060         return ret;
1061 }
1062
1063 static irqreturn_t rspi_irq_rx(int irq, void *_sr)
1064 {
1065         struct rspi_data *rspi = _sr;
1066         u8 spsr;
1067
1068         rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1069         if (spsr & SPSR_SPRF) {
1070                 rspi_disable_irq(rspi, SPCR_SPRIE);
1071                 wake_up(&rspi->wait);
1072                 return IRQ_HANDLED;
1073         }
1074
1075         return 0;
1076 }
1077
1078 static irqreturn_t rspi_irq_tx(int irq, void *_sr)
1079 {
1080         struct rspi_data *rspi = _sr;
1081         u8 spsr;
1082
1083         rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1084         if (spsr & SPSR_SPTEF) {
1085                 rspi_disable_irq(rspi, SPCR_SPTIE);
1086                 wake_up(&rspi->wait);
1087                 return IRQ_HANDLED;
1088         }
1089
1090         return 0;
1091 }
1092
1093 static struct dma_chan *rspi_request_dma_chan(struct device *dev,
1094                                               enum dma_transfer_direction dir,
1095                                               unsigned int id,
1096                                               dma_addr_t port_addr)
1097 {
1098         dma_cap_mask_t mask;
1099         struct dma_chan *chan;
1100         struct dma_slave_config cfg;
1101         int ret;
1102
1103         dma_cap_zero(mask);
1104         dma_cap_set(DMA_SLAVE, mask);
1105
1106         chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1107                                 (void *)(unsigned long)id, dev,
1108                                 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1109         if (!chan) {
1110                 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1111                 return NULL;
1112         }
1113
1114         memset(&cfg, 0, sizeof(cfg));
1115         cfg.dst_addr = port_addr + RSPI_SPDR;
1116         cfg.src_addr = port_addr + RSPI_SPDR;
1117         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1118         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1119         cfg.direction = dir;
1120
1121         ret = dmaengine_slave_config(chan, &cfg);
1122         if (ret) {
1123                 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1124                 dma_release_channel(chan);
1125                 return NULL;
1126         }
1127
1128         return chan;
1129 }
1130
1131 static int rspi_request_dma(struct device *dev, struct spi_controller *ctlr,
1132                             const struct resource *res)
1133 {
1134         const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev);
1135         unsigned int dma_tx_id, dma_rx_id;
1136
1137         if (dev->of_node) {
1138                 /* In the OF case we will get the slave IDs from the DT */
1139                 dma_tx_id = 0;
1140                 dma_rx_id = 0;
1141         } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) {
1142                 dma_tx_id = rspi_pd->dma_tx_id;
1143                 dma_rx_id = rspi_pd->dma_rx_id;
1144         } else {
1145                 /* The driver assumes no error. */
1146                 return 0;
1147         }
1148
1149         ctlr->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id,
1150                                              res->start);
1151         if (!ctlr->dma_tx)
1152                 return -ENODEV;
1153
1154         ctlr->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id,
1155                                              res->start);
1156         if (!ctlr->dma_rx) {
1157                 dma_release_channel(ctlr->dma_tx);
1158                 ctlr->dma_tx = NULL;
1159                 return -ENODEV;
1160         }
1161
1162         ctlr->can_dma = rspi_can_dma;
1163         dev_info(dev, "DMA available");
1164         return 0;
1165 }
1166
1167 static void rspi_release_dma(struct spi_controller *ctlr)
1168 {
1169         if (ctlr->dma_tx)
1170                 dma_release_channel(ctlr->dma_tx);
1171         if (ctlr->dma_rx)
1172                 dma_release_channel(ctlr->dma_rx);
1173 }
1174
1175 static void rspi_remove(struct platform_device *pdev)
1176 {
1177         struct rspi_data *rspi = platform_get_drvdata(pdev);
1178
1179         rspi_release_dma(rspi->ctlr);
1180         pm_runtime_disable(&pdev->dev);
1181 }
1182
1183 static const struct spi_ops rspi_ops = {
1184         .set_config_register =  rspi_set_config_register,
1185         .transfer_one =         rspi_transfer_one,
1186         .min_div =              2,
1187         .max_div =              4096,
1188         .flags =                SPI_CONTROLLER_MUST_TX,
1189         .fifo_size =            8,
1190         .num_hw_ss =            2,
1191 };
1192
1193 static const struct spi_ops rspi_rz_ops __maybe_unused = {
1194         .set_config_register =  rspi_rz_set_config_register,
1195         .transfer_one =         rspi_rz_transfer_one,
1196         .min_div =              2,
1197         .max_div =              4096,
1198         .flags =                SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX,
1199         .fifo_size =            8,      /* 8 for TX, 32 for RX */
1200         .num_hw_ss =            1,
1201 };
1202
1203 static const struct spi_ops qspi_ops __maybe_unused = {
1204         .set_config_register =  qspi_set_config_register,
1205         .transfer_one =         qspi_transfer_one,
1206         .extra_mode_bits =      SPI_TX_DUAL | SPI_TX_QUAD |
1207                                 SPI_RX_DUAL | SPI_RX_QUAD,
1208         .min_div =              1,
1209         .max_div =              4080,
1210         .flags =                SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX,
1211         .fifo_size =            32,
1212         .num_hw_ss =            1,
1213 };
1214
1215 static const struct of_device_id rspi_of_match[] __maybe_unused = {
1216         /* RSPI on legacy SH */
1217         { .compatible = "renesas,rspi", .data = &rspi_ops },
1218         /* RSPI on RZ/A1H */
1219         { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1220         /* QSPI on R-Car Gen2 */
1221         { .compatible = "renesas,qspi", .data = &qspi_ops },
1222         { /* sentinel */ }
1223 };
1224
1225 MODULE_DEVICE_TABLE(of, rspi_of_match);
1226
1227 #ifdef CONFIG_OF
1228 static void rspi_reset_control_assert(void *data)
1229 {
1230         reset_control_assert(data);
1231 }
1232
1233 static int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr)
1234 {
1235         struct reset_control *rstc;
1236         u32 num_cs;
1237         int error;
1238
1239         /* Parse DT properties */
1240         error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1241         if (error) {
1242                 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1243                 return error;
1244         }
1245
1246         ctlr->num_chipselect = num_cs;
1247
1248         rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
1249         if (IS_ERR(rstc))
1250                 return dev_err_probe(dev, PTR_ERR(rstc),
1251                                              "failed to get reset ctrl\n");
1252
1253         error = reset_control_deassert(rstc);
1254         if (error) {
1255                 dev_err(dev, "failed to deassert reset %d\n", error);
1256                 return error;
1257         }
1258
1259         error = devm_add_action_or_reset(dev, rspi_reset_control_assert, rstc);
1260         if (error) {
1261                 dev_err(dev, "failed to register assert devm action, %d\n", error);
1262                 return error;
1263         }
1264
1265         return 0;
1266 }
1267 #else
1268 #define rspi_of_match   NULL
1269 static inline int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr)
1270 {
1271         return -EINVAL;
1272 }
1273 #endif /* CONFIG_OF */
1274
1275 static int rspi_request_irq(struct device *dev, unsigned int irq,
1276                             irq_handler_t handler, const char *suffix,
1277                             void *dev_id)
1278 {
1279         const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
1280                                           dev_name(dev), suffix);
1281         if (!name)
1282                 return -ENOMEM;
1283
1284         return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1285 }
1286
1287 static int rspi_probe(struct platform_device *pdev)
1288 {
1289         struct resource *res;
1290         struct spi_controller *ctlr;
1291         struct rspi_data *rspi;
1292         int ret;
1293         const struct rspi_plat_data *rspi_pd;
1294         const struct spi_ops *ops;
1295         unsigned long clksrc;
1296
1297         ctlr = spi_alloc_host(&pdev->dev, sizeof(struct rspi_data));
1298         if (ctlr == NULL)
1299                 return -ENOMEM;
1300
1301         ops = of_device_get_match_data(&pdev->dev);
1302         if (ops) {
1303                 ret = rspi_parse_dt(&pdev->dev, ctlr);
1304                 if (ret)
1305                         goto error1;
1306         } else {
1307                 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1308                 rspi_pd = dev_get_platdata(&pdev->dev);
1309                 if (rspi_pd && rspi_pd->num_chipselect)
1310                         ctlr->num_chipselect = rspi_pd->num_chipselect;
1311                 else
1312                         ctlr->num_chipselect = 2; /* default */
1313         }
1314
1315         rspi = spi_controller_get_devdata(ctlr);
1316         platform_set_drvdata(pdev, rspi);
1317         rspi->ops = ops;
1318         rspi->ctlr = ctlr;
1319
1320         rspi->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1321         if (IS_ERR(rspi->addr)) {
1322                 ret = PTR_ERR(rspi->addr);
1323                 goto error1;
1324         }
1325
1326         rspi->clk = devm_clk_get(&pdev->dev, NULL);
1327         if (IS_ERR(rspi->clk)) {
1328                 dev_err(&pdev->dev, "cannot get clock\n");
1329                 ret = PTR_ERR(rspi->clk);
1330                 goto error1;
1331         }
1332
1333         rspi->pdev = pdev;
1334         pm_runtime_enable(&pdev->dev);
1335
1336         init_waitqueue_head(&rspi->wait);
1337         spin_lock_init(&rspi->lock);
1338
1339         ctlr->bus_num = pdev->id;
1340         ctlr->setup = rspi_setup;
1341         ctlr->auto_runtime_pm = true;
1342         ctlr->transfer_one = ops->transfer_one;
1343         ctlr->prepare_message = rspi_prepare_message;
1344         ctlr->unprepare_message = rspi_unprepare_message;
1345         ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
1346                           SPI_LOOP | ops->extra_mode_bits;
1347         clksrc = clk_get_rate(rspi->clk);
1348         ctlr->min_speed_hz = DIV_ROUND_UP(clksrc, ops->max_div);
1349         ctlr->max_speed_hz = DIV_ROUND_UP(clksrc, ops->min_div);
1350         ctlr->flags = ops->flags;
1351         ctlr->dev.of_node = pdev->dev.of_node;
1352         ctlr->use_gpio_descriptors = true;
1353         ctlr->max_native_cs = rspi->ops->num_hw_ss;
1354
1355         ret = platform_get_irq_byname_optional(pdev, "rx");
1356         if (ret < 0) {
1357                 ret = platform_get_irq_byname_optional(pdev, "mux");
1358                 if (ret < 0)
1359                         ret = platform_get_irq(pdev, 0);
1360                 if (ret >= 0)
1361                         rspi->rx_irq = rspi->tx_irq = ret;
1362         } else {
1363                 rspi->rx_irq = ret;
1364                 ret = platform_get_irq_byname(pdev, "tx");
1365                 if (ret >= 0)
1366                         rspi->tx_irq = ret;
1367         }
1368
1369         if (rspi->rx_irq == rspi->tx_irq) {
1370                 /* Single multiplexed interrupt */
1371                 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1372                                        "mux", rspi);
1373         } else {
1374                 /* Multi-interrupt mode, only SPRI and SPTI are used */
1375                 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1376                                        "rx", rspi);
1377                 if (!ret)
1378                         ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1379                                                rspi_irq_tx, "tx", rspi);
1380         }
1381         if (ret < 0) {
1382                 dev_err(&pdev->dev, "request_irq error\n");
1383                 goto error2;
1384         }
1385
1386         ret = rspi_request_dma(&pdev->dev, ctlr, res);
1387         if (ret < 0)
1388                 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1389
1390         ret = devm_spi_register_controller(&pdev->dev, ctlr);
1391         if (ret < 0) {
1392                 dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
1393                 goto error3;
1394         }
1395
1396         dev_info(&pdev->dev, "probed\n");
1397
1398         return 0;
1399
1400 error3:
1401         rspi_release_dma(ctlr);
1402 error2:
1403         pm_runtime_disable(&pdev->dev);
1404 error1:
1405         spi_controller_put(ctlr);
1406
1407         return ret;
1408 }
1409
1410 static const struct platform_device_id spi_driver_ids[] = {
1411         { "rspi",       (kernel_ulong_t)&rspi_ops },
1412         {},
1413 };
1414
1415 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1416
1417 #ifdef CONFIG_PM_SLEEP
1418 static int rspi_suspend(struct device *dev)
1419 {
1420         struct rspi_data *rspi = dev_get_drvdata(dev);
1421
1422         return spi_controller_suspend(rspi->ctlr);
1423 }
1424
1425 static int rspi_resume(struct device *dev)
1426 {
1427         struct rspi_data *rspi = dev_get_drvdata(dev);
1428
1429         return spi_controller_resume(rspi->ctlr);
1430 }
1431
1432 static SIMPLE_DEV_PM_OPS(rspi_pm_ops, rspi_suspend, rspi_resume);
1433 #define DEV_PM_OPS      &rspi_pm_ops
1434 #else
1435 #define DEV_PM_OPS      NULL
1436 #endif /* CONFIG_PM_SLEEP */
1437
1438 static struct platform_driver rspi_driver = {
1439         .probe =        rspi_probe,
1440         .remove_new =   rspi_remove,
1441         .id_table =     spi_driver_ids,
1442         .driver         = {
1443                 .name = "renesas_spi",
1444                 .pm = DEV_PM_OPS,
1445                 .of_match_table = of_match_ptr(rspi_of_match),
1446         },
1447 };
1448 module_platform_driver(rspi_driver);
1449
1450 MODULE_DESCRIPTION("Renesas RSPI bus driver");
1451 MODULE_LICENSE("GPL v2");
1452 MODULE_AUTHOR("Yoshihiro Shimoda");