drivers/spi/spi-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   4  * Author: Addy Ke <addy.ke@rock-chips.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/dmaengine.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/pinctrl/consumer.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/scatterlist.h>
  17
  18 #define DRIVER_NAME "rockchip-spi"
  19
  20 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
  21                 writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
  22 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \
  23                 writel_relaxed(readl_relaxed(reg) | (bits), reg)
  24
  25 /* SPI register offsets */
  26 #define ROCKCHIP_SPI_CTRLR0                     0x0000
  27 #define ROCKCHIP_SPI_CTRLR1                     0x0004
  28 #define ROCKCHIP_SPI_SSIENR                     0x0008
  29 #define ROCKCHIP_SPI_SER                        0x000c
  30 #define ROCKCHIP_SPI_BAUDR                      0x0010
  31 #define ROCKCHIP_SPI_TXFTLR                     0x0014
  32 #define ROCKCHIP_SPI_RXFTLR                     0x0018
  33 #define ROCKCHIP_SPI_TXFLR                      0x001c
  34 #define ROCKCHIP_SPI_RXFLR                      0x0020
  35 #define ROCKCHIP_SPI_SR                         0x0024
  36 #define ROCKCHIP_SPI_IPR                        0x0028
  37 #define ROCKCHIP_SPI_IMR                        0x002c
  38 #define ROCKCHIP_SPI_ISR                        0x0030
  39 #define ROCKCHIP_SPI_RISR                       0x0034
  40 #define ROCKCHIP_SPI_ICR                        0x0038
  41 #define ROCKCHIP_SPI_DMACR                      0x003c
  42 #define ROCKCHIP_SPI_DMATDLR                    0x0040
  43 #define ROCKCHIP_SPI_DMARDLR                    0x0044
  44 #define ROCKCHIP_SPI_VERSION                    0x0048
  45 #define ROCKCHIP_SPI_TXDR                       0x0400
  46 #define ROCKCHIP_SPI_RXDR                       0x0800
  47
  48 /* Bit fields in CTRLR0 */
  49 #define CR0_DFS_OFFSET                          0
  50 #define CR0_DFS_4BIT                            0x0
  51 #define CR0_DFS_8BIT                            0x1
  52 #define CR0_DFS_16BIT                           0x2
  53
  54 #define CR0_CFS_OFFSET                          2
  55
  56 #define CR0_SCPH_OFFSET                         6
  57
  58 #define CR0_SCPOL_OFFSET                        7
  59
  60 #define CR0_CSM_OFFSET                          8
  61 #define CR0_CSM_KEEP                            0x0
  62 /* ss_n be high for half sclk_out cycles */
  63 #define CR0_CSM_HALF                            0X1
  64 /* ss_n be high for one sclk_out cycle */
  65 #define CR0_CSM_ONE                                     0x2
  66
  67 /* ss_n to sclk_out delay */
  68 #define CR0_SSD_OFFSET                          10
  69 /*
  70  * The period between ss_n active and
  71  * sclk_out active is half sclk_out cycles
  72  */
  73 #define CR0_SSD_HALF                            0x0
  74 /*
  75  * The period between ss_n active and
  76  * sclk_out active is one sclk_out cycle
  77  */
  78 #define CR0_SSD_ONE                                     0x1
  79
  80 #define CR0_EM_OFFSET                           11
  81 #define CR0_EM_LITTLE                           0x0
  82 #define CR0_EM_BIG                                      0x1
  83
  84 #define CR0_FBM_OFFSET                          12
  85 #define CR0_FBM_MSB                                     0x0
  86 #define CR0_FBM_LSB                                     0x1
  87
  88 #define CR0_BHT_OFFSET                          13
  89 #define CR0_BHT_16BIT                           0x0
  90 #define CR0_BHT_8BIT                            0x1
  91
  92 #define CR0_RSD_OFFSET                          14
  93 #define CR0_RSD_MAX                             0x3
  94
  95 #define CR0_FRF_OFFSET                          16
  96 #define CR0_FRF_SPI                                     0x0
  97 #define CR0_FRF_SSP                                     0x1
  98 #define CR0_FRF_MICROWIRE                       0x2
  99
 100 #define CR0_XFM_OFFSET                          18
 101 #define CR0_XFM_MASK                            (0x03 << SPI_XFM_OFFSET)
 102 #define CR0_XFM_TR                                      0x0
 103 #define CR0_XFM_TO                                      0x1
 104 #define CR0_XFM_RO                                      0x2
 105
 106 #define CR0_OPM_OFFSET                          20
 107 #define CR0_OPM_MASTER                          0x0
 108 #define CR0_OPM_SLAVE                           0x1
 109
 110 #define CR0_SOI_OFFSET                          23
 111
 112 #define CR0_MTM_OFFSET                          0x21
 113
 114 /* Bit fields in SER, 2bit */
 115 #define SER_MASK                                        0x3
 116
 117 /* Bit fields in BAUDR */
 118 #define BAUDR_SCKDV_MIN                         2
 119 #define BAUDR_SCKDV_MAX                         65534
 120
 121 /* Bit fields in SR, 6bit */
 122 #define SR_MASK                                         0x3f
 123 #define SR_BUSY                                         (1 << 0)
 124 #define SR_TF_FULL                                      (1 << 1)
 125 #define SR_TF_EMPTY                                     (1 << 2)
 126 #define SR_RF_EMPTY                                     (1 << 3)
 127 #define SR_RF_FULL                                      (1 << 4)
 128 #define SR_SLAVE_TX_BUSY                                (1 << 5)
 129
 130 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
 131 #define INT_MASK                                        0x1f
 132 #define INT_TF_EMPTY                            (1 << 0)
 133 #define INT_TF_OVERFLOW                         (1 << 1)
 134 #define INT_RF_UNDERFLOW                        (1 << 2)
 135 #define INT_RF_OVERFLOW                         (1 << 3)
 136 #define INT_RF_FULL                             (1 << 4)
 137 #define INT_CS_INACTIVE                         (1 << 6)
 138
 139 /* Bit fields in ICR, 4bit */
 140 #define ICR_MASK                                        0x0f
 141 #define ICR_ALL                                         (1 << 0)
 142 #define ICR_RF_UNDERFLOW                        (1 << 1)
 143 #define ICR_RF_OVERFLOW                         (1 << 2)
 144 #define ICR_TF_OVERFLOW                         (1 << 3)
 145
 146 /* Bit fields in DMACR */
 147 #define RF_DMA_EN                                       (1 << 0)
 148 #define TF_DMA_EN                                       (1 << 1)
 149
 150 /* Driver state flags */
 151 #define RXDMA                                   (1 << 0)
 152 #define TXDMA                                   (1 << 1)
 153
 154 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
 155 #define MAX_SCLK_OUT                            50000000U
 156
 157 /*
 158  * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
 159  * the controller seems to hang when given 0x10000, so stick with this for now.
 160  */
 161 #define ROCKCHIP_SPI_MAX_TRANLEN                0xffff
 162
 163 /* 2 for native cs, 2 for cs-gpio */
 164 #define ROCKCHIP_SPI_MAX_CS_NUM                 4
 165 #define ROCKCHIP_SPI_VER2_TYPE1                 0x05EC0002
 166 #define ROCKCHIP_SPI_VER2_TYPE2                 0x00110002
 167
 168 #define ROCKCHIP_AUTOSUSPEND_TIMEOUT            2000
 169
 170 struct rockchip_spi {
 171         struct device *dev;
 172
 173         struct clk *spiclk;
 174         struct clk *apb_pclk;
 175
 176         void __iomem *regs;
 177         dma_addr_t dma_addr_rx;
 178         dma_addr_t dma_addr_tx;
 179
 180         const void *tx;
 181         void *rx;
 182         unsigned int tx_left;
 183         unsigned int rx_left;
 184
 185         atomic_t state;
 186
 187         /*depth of the FIFO buffer */
 188         u32 fifo_len;
 189         /* frequency of spiclk */
 190         u32 freq;
 191
 192         u8 n_bytes;
 193         u8 rsd;
 194
 195         bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
 196
 197         bool slave_abort;
 198         bool cs_inactive; /* spi slave tansmition stop when cs inactive */
 199         bool cs_high_supported; /* native CS supports active-high polarity */
 200
 201         struct spi_transfer *xfer; /* Store xfer temporarily */
 202 };
 203
 204 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
 205 {
 206         writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
 207 }
 208
 209 static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool slave_mode)
 210 {
 211         unsigned long timeout = jiffies + msecs_to_jiffies(5);
 212
 213         do {
 214                 if (slave_mode) {
 215                         if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_SLAVE_TX_BUSY) &&
 216                             !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)))
 217                                 return;
 218                 } else {
 219                         if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
 220                                 return;
 221                 }
 222         } while (!time_after(jiffies, timeout));
 223
 224         dev_warn(rs->dev, "spi controller is in busy state!\n");
 225 }
 226
 227 static u32 get_fifo_len(struct rockchip_spi *rs)
 228 {
 229         u32 ver;
 230
 231         ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
 232
 233         switch (ver) {
 234         case ROCKCHIP_SPI_VER2_TYPE1:
 235         case ROCKCHIP_SPI_VER2_TYPE2:
 236                 return 64;
 237         default:
 238                 return 32;
 239         }
 240 }
 241
 242 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
 243 {
 244         struct spi_controller *ctlr = spi->controller;
 245         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 246         bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable;
 247
 248         /* Return immediately for no-op */
 249         if (cs_asserted == rs->cs_asserted[spi->chip_select])
 250                 return;
 251
 252         if (cs_asserted) {
 253                 /* Keep things powered as long as CS is asserted */
 254                 pm_runtime_get_sync(rs->dev);
 255
 256                 if (spi->cs_gpiod)
 257                         ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
 258                 else
 259                         ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
 260         } else {
 261                 if (spi->cs_gpiod)
 262                         ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
 263                 else
 264                         ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
 265
 266                 /* Drop reference from when we first asserted CS */
 267                 pm_runtime_put(rs->dev);
 268         }
 269
 270         rs->cs_asserted[spi->chip_select] = cs_asserted;
 271 }
 272
 273 static void rockchip_spi_handle_err(struct spi_controller *ctlr,
 274                                     struct spi_message *msg)
 275 {
 276         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 277
 278         /* stop running spi transfer
 279          * this also flushes both rx and tx fifos
 280          */
 281         spi_enable_chip(rs, false);
 282
 283         /* make sure all interrupts are masked */
 284         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 285
 286         if (atomic_read(&rs->state) & TXDMA)
 287                 dmaengine_terminate_async(ctlr->dma_tx);
 288
 289         if (atomic_read(&rs->state) & RXDMA)
 290                 dmaengine_terminate_async(ctlr->dma_rx);
 291 }
 292
 293 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
 294 {
 295         u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
 296         u32 words = min(rs->tx_left, tx_free);
 297
 298         rs->tx_left -= words;
 299         for (; words; words--) {
 300                 u32 txw;
 301
 302                 if (rs->n_bytes == 1)
 303                         txw = *(u8 *)rs->tx;
 304                 else
 305                         txw = *(u16 *)rs->tx;
 306
 307                 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
 308                 rs->tx += rs->n_bytes;
 309         }
 310 }
 311
 312 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
 313 {
 314         u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 315         u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0;
 316
 317         /* the hardware doesn't allow us to change fifo threshold
 318          * level while spi is enabled, so instead make sure to leave
 319          * enough words in the rx fifo to get the last interrupt
 320          * exactly when all words have been received
 321          */
 322         if (rx_left) {
 323                 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1;
 324
 325                 if (rx_left < ftl) {
 326                         rx_left = ftl;
 327                         words = rs->rx_left - rx_left;
 328                 }
 329         }
 330
 331         rs->rx_left = rx_left;
 332         for (; words; words--) {
 333                 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 334
 335                 if (!rs->rx)
 336                         continue;
 337
 338                 if (rs->n_bytes == 1)
 339                         *(u8 *)rs->rx = (u8)rxw;
 340                 else
 341                         *(u16 *)rs->rx = (u16)rxw;
 342                 rs->rx += rs->n_bytes;
 343         }
 344 }
 345
 346 static irqreturn_t rockchip_spi_isr(int irq, void *dev_id)
 347 {
 348         struct spi_controller *ctlr = dev_id;
 349         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 350
 351         /* When int_cs_inactive comes, spi slave abort */
 352         if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_IMR) & INT_CS_INACTIVE) {
 353                 ctlr->slave_abort(ctlr);
 354                 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 355                 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
 356
 357                 return IRQ_HANDLED;
 358         }
 359
 360         if (rs->tx_left)
 361                 rockchip_spi_pio_writer(rs);
 362
 363         rockchip_spi_pio_reader(rs);
 364         if (!rs->rx_left) {
 365                 spi_enable_chip(rs, false);
 366                 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 367                 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
 368                 spi_finalize_current_transfer(ctlr);
 369         }
 370
 371         return IRQ_HANDLED;
 372 }
 373
 374 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs,
 375                                     struct spi_controller *ctlr,
 376                                     struct spi_transfer *xfer)
 377 {
 378         rs->tx = xfer->tx_buf;
 379         rs->rx = xfer->rx_buf;
 380         rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
 381         rs->rx_left = xfer->len / rs->n_bytes;
 382
 383         if (rs->cs_inactive)
 384                 writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
 385         else
 386                 writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
 387         spi_enable_chip(rs, true);
 388
 389         if (rs->tx_left)
 390                 rockchip_spi_pio_writer(rs);
 391
 392         /* 1 means the transfer is in progress */
 393         return 1;
 394 }
 395
 396 static void rockchip_spi_dma_rxcb(void *data)
 397 {
 398         struct spi_controller *ctlr = data;
 399         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 400         int state = atomic_fetch_andnot(RXDMA, &rs->state);
 401
 402         if (state & TXDMA && !rs->slave_abort)
 403                 return;
 404
 405         if (rs->cs_inactive)
 406                 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 407
 408         spi_enable_chip(rs, false);
 409         spi_finalize_current_transfer(ctlr);
 410 }
 411
 412 static void rockchip_spi_dma_txcb(void *data)
 413 {
 414         struct spi_controller *ctlr = data;
 415         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 416         int state = atomic_fetch_andnot(TXDMA, &rs->state);
 417
 418         if (state & RXDMA && !rs->slave_abort)
 419                 return;
 420
 421         /* Wait until the FIFO data completely. */
 422         wait_for_tx_idle(rs, ctlr->slave);
 423
 424         spi_enable_chip(rs, false);
 425         spi_finalize_current_transfer(ctlr);
 426 }
 427
 428 static u32 rockchip_spi_calc_burst_size(u32 data_len)
 429 {
 430         u32 i;
 431
 432         /* burst size: 1, 2, 4, 8 */
 433         for (i = 1; i < 8; i <<= 1) {
 434                 if (data_len & i)
 435                         break;
 436         }
 437
 438         return i;
 439 }
 440
 441 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs,
 442                 struct spi_controller *ctlr, struct spi_transfer *xfer)
 443 {
 444         struct dma_async_tx_descriptor *rxdesc, *txdesc;
 445
 446         atomic_set(&rs->state, 0);
 447
 448         rs->tx = xfer->tx_buf;
 449         rs->rx = xfer->rx_buf;
 450
 451         rxdesc = NULL;
 452         if (xfer->rx_buf) {
 453                 struct dma_slave_config rxconf = {
 454                         .direction = DMA_DEV_TO_MEM,
 455                         .src_addr = rs->dma_addr_rx,
 456                         .src_addr_width = rs->n_bytes,
 457                         .src_maxburst = rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes),
 458                 };
 459
 460                 dmaengine_slave_config(ctlr->dma_rx, &rxconf);
 461
 462                 rxdesc = dmaengine_prep_slave_sg(
 463                                 ctlr->dma_rx,
 464                                 xfer->rx_sg.sgl, xfer->rx_sg.nents,
 465                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
 466                 if (!rxdesc)
 467                         return -EINVAL;
 468
 469                 rxdesc->callback = rockchip_spi_dma_rxcb;
 470                 rxdesc->callback_param = ctlr;
 471         }
 472
 473         txdesc = NULL;
 474         if (xfer->tx_buf) {
 475                 struct dma_slave_config txconf = {
 476                         .direction = DMA_MEM_TO_DEV,
 477                         .dst_addr = rs->dma_addr_tx,
 478                         .dst_addr_width = rs->n_bytes,
 479                         .dst_maxburst = rs->fifo_len / 4,
 480                 };
 481
 482                 dmaengine_slave_config(ctlr->dma_tx, &txconf);
 483
 484                 txdesc = dmaengine_prep_slave_sg(
 485                                 ctlr->dma_tx,
 486                                 xfer->tx_sg.sgl, xfer->tx_sg.nents,
 487                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 488                 if (!txdesc) {
 489                         if (rxdesc)
 490                                 dmaengine_terminate_sync(ctlr->dma_rx);
 491                         return -EINVAL;
 492                 }
 493
 494                 txdesc->callback = rockchip_spi_dma_txcb;
 495                 txdesc->callback_param = ctlr;
 496         }
 497
 498         /* rx must be started before tx due to spi instinct */
 499         if (rxdesc) {
 500                 atomic_or(RXDMA, &rs->state);
 501                 ctlr->dma_rx->cookie = dmaengine_submit(rxdesc);
 502                 dma_async_issue_pending(ctlr->dma_rx);
 503         }
 504
 505         if (rs->cs_inactive)
 506                 writel_relaxed(INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
 507
 508         spi_enable_chip(rs, true);
 509
 510         if (txdesc) {
 511                 atomic_or(TXDMA, &rs->state);
 512                 dmaengine_submit(txdesc);
 513                 dma_async_issue_pending(ctlr->dma_tx);
 514         }
 515
 516         /* 1 means the transfer is in progress */
 517         return 1;
 518 }
 519
 520 static int rockchip_spi_config(struct rockchip_spi *rs,
 521                 struct spi_device *spi, struct spi_transfer *xfer,
 522                 bool use_dma, bool slave_mode)
 523 {
 524         u32 cr0 = CR0_FRF_SPI  << CR0_FRF_OFFSET
 525                 | CR0_BHT_8BIT << CR0_BHT_OFFSET
 526                 | CR0_SSD_ONE  << CR0_SSD_OFFSET
 527                 | CR0_EM_BIG   << CR0_EM_OFFSET;
 528         u32 cr1;
 529         u32 dmacr = 0;
 530
 531         if (slave_mode)
 532                 cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET;
 533         rs->slave_abort = false;
 534
 535         cr0 |= rs->rsd << CR0_RSD_OFFSET;
 536         cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
 537         if (spi->mode & SPI_LSB_FIRST)
 538                 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
 539         if (spi->mode & SPI_CS_HIGH)
 540                 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
 541
 542         if (xfer->rx_buf && xfer->tx_buf)
 543                 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
 544         else if (xfer->rx_buf)
 545                 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;
 546         else if (use_dma)
 547                 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
 548
 549         switch (xfer->bits_per_word) {
 550         case 4:
 551                 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET;
 552                 cr1 = xfer->len - 1;
 553                 break;
 554         case 8:
 555                 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET;
 556                 cr1 = xfer->len - 1;
 557                 break;
 558         case 16:
 559                 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET;
 560                 cr1 = xfer->len / 2 - 1;
 561                 break;
 562         default:
 563                 /* we only whitelist 4, 8 and 16 bit words in
 564                  * ctlr->bits_per_word_mask, so this shouldn't
 565                  * happen
 566                  */
 567                 dev_err(rs->dev, "unknown bits per word: %d\n",
 568                         xfer->bits_per_word);
 569                 return -EINVAL;
 570         }
 571
 572         if (use_dma) {
 573                 if (xfer->tx_buf)
 574                         dmacr |= TF_DMA_EN;
 575                 if (xfer->rx_buf)
 576                         dmacr |= RF_DMA_EN;
 577         }
 578
 579         writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
 580         writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 581
 582         /* unfortunately setting the fifo threshold level to generate an
 583          * interrupt exactly when the fifo is full doesn't seem to work,
 584          * so we need the strict inequality here
 585          */
 586         if ((xfer->len / rs->n_bytes) < rs->fifo_len)
 587                 writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 588         else
 589                 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 590
 591         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
 592         writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1,
 593                        rs->regs + ROCKCHIP_SPI_DMARDLR);
 594         writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
 595
 596         /* the hardware only supports an even clock divisor, so
 597          * round divisor = spiclk / speed up to nearest even number
 598          * so that the resulting speed is <= the requested speed
 599          */
 600         writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz),
 601                         rs->regs + ROCKCHIP_SPI_BAUDR);
 602
 603         return 0;
 604 }
 605
 606 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
 607 {
 608         return ROCKCHIP_SPI_MAX_TRANLEN;
 609 }
 610
 611 static int rockchip_spi_slave_abort(struct spi_controller *ctlr)
 612 {
 613         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 614         u32 rx_fifo_left;
 615         struct dma_tx_state state;
 616         enum dma_status status;
 617
 618         /* Get current dma rx point */
 619         if (atomic_read(&rs->state) & RXDMA) {
 620                 dmaengine_pause(ctlr->dma_rx);
 621                 status = dmaengine_tx_status(ctlr->dma_rx, ctlr->dma_rx->cookie, &state);
 622                 if (status == DMA_ERROR) {
 623                         rs->rx = rs->xfer->rx_buf;
 624                         rs->xfer->len = 0;
 625                         rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 626                         for (; rx_fifo_left; rx_fifo_left--)
 627                                 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 628                         goto out;
 629                 } else {
 630                         rs->rx += rs->xfer->len - rs->n_bytes * state.residue;
 631                 }
 632         }
 633
 634         /* Get the valid data left in rx fifo and set rs->xfer->len real rx size */
 635         if (rs->rx) {
 636                 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 637                 for (; rx_fifo_left; rx_fifo_left--) {
 638                         u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 639
 640                         if (rs->n_bytes == 1)
 641                                 *(u8 *)rs->rx = (u8)rxw;
 642                         else
 643                                 *(u16 *)rs->rx = (u16)rxw;
 644                         rs->rx += rs->n_bytes;
 645                 }
 646                 rs->xfer->len = (unsigned int)(rs->rx - rs->xfer->rx_buf);
 647         }
 648
 649 out:
 650         if (atomic_read(&rs->state) & RXDMA)
 651                 dmaengine_terminate_sync(ctlr->dma_rx);
 652         if (atomic_read(&rs->state) & TXDMA)
 653                 dmaengine_terminate_sync(ctlr->dma_tx);
 654         atomic_set(&rs->state, 0);
 655         spi_enable_chip(rs, false);
 656         rs->slave_abort = true;
 657         spi_finalize_current_transfer(ctlr);
 658
 659         return 0;
 660 }
 661
 662 static int rockchip_spi_transfer_one(
 663                 struct spi_controller *ctlr,
 664                 struct spi_device *spi,
 665                 struct spi_transfer *xfer)
 666 {
 667         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 668         int ret;
 669         bool use_dma;
 670
 671         /* Zero length transfers won't trigger an interrupt on completion */
 672         if (!xfer->len) {
 673                 spi_finalize_current_transfer(ctlr);
 674                 return 1;
 675         }
 676
 677         WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
 678                 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
 679
 680         if (!xfer->tx_buf && !xfer->rx_buf) {
 681                 dev_err(rs->dev, "No buffer for transfer\n");
 682                 return -EINVAL;
 683         }
 684
 685         if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
 686                 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
 687                 return -EINVAL;
 688         }
 689
 690         rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
 691         rs->xfer = xfer;
 692         use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
 693
 694         ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave);
 695         if (ret)
 696                 return ret;
 697
 698         if (use_dma)
 699                 return rockchip_spi_prepare_dma(rs, ctlr, xfer);
 700
 701         return rockchip_spi_prepare_irq(rs, ctlr, xfer);
 702 }
 703
 704 static bool rockchip_spi_can_dma(struct spi_controller *ctlr,
 705                                  struct spi_device *spi,
 706                                  struct spi_transfer *xfer)
 707 {
 708         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 709         unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2;
 710
 711         /* if the numbor of spi words to transfer is less than the fifo
 712          * length we can just fill the fifo and wait for a single irq,
 713          * so don't bother setting up dma
 714          */
 715         return xfer->len / bytes_per_word >= rs->fifo_len;
 716 }
 717
 718 static int rockchip_spi_setup(struct spi_device *spi)
 719 {
 720         struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
 721         u32 cr0;
 722
 723         if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) {
 724                 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
 725                 return -EINVAL;
 726         }
 727
 728         pm_runtime_get_sync(rs->dev);
 729
 730         cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0);
 731
 732         cr0 &= ~(0x3 << CR0_SCPH_OFFSET);
 733         cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET);
 734         if (spi->mode & SPI_CS_HIGH && spi->chip_select <= 1)
 735                 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
 736         else if (spi->chip_select <= 1)
 737                 cr0 &= ~(BIT(spi->chip_select) << CR0_SOI_OFFSET);
 738
 739         writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
 740
 741         pm_runtime_put(rs->dev);
 742
 743         return 0;
 744 }
 745
 746 static int rockchip_spi_probe(struct platform_device *pdev)
 747 {
 748         int ret;
 749         struct rockchip_spi *rs;
 750         struct spi_controller *ctlr;
 751         struct resource *mem;
 752         struct device_node *np = pdev->dev.of_node;
 753         u32 rsd_nsecs, num_cs;
 754         bool slave_mode;
 755
 756         slave_mode = of_property_read_bool(np, "spi-slave");
 757
 758         if (slave_mode)
 759                 ctlr = spi_alloc_slave(&pdev->dev,
 760                                 sizeof(struct rockchip_spi));
 761         else
 762                 ctlr = spi_alloc_master(&pdev->dev,
 763                                 sizeof(struct rockchip_spi));
 764
 765         if (!ctlr)
 766                 return -ENOMEM;
 767
 768         platform_set_drvdata(pdev, ctlr);
 769
 770         rs = spi_controller_get_devdata(ctlr);
 771         ctlr->slave = slave_mode;
 772
 773         /* Get basic io resource and map it */
 774         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 775         rs->regs = devm_ioremap_resource(&pdev->dev, mem);
 776         if (IS_ERR(rs->regs)) {
 777                 ret =  PTR_ERR(rs->regs);
 778                 goto err_put_ctlr;
 779         }
 780
 781         rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
 782         if (IS_ERR(rs->apb_pclk)) {
 783                 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
 784                 ret = PTR_ERR(rs->apb_pclk);
 785                 goto err_put_ctlr;
 786         }
 787
 788         rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
 789         if (IS_ERR(rs->spiclk)) {
 790                 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
 791                 ret = PTR_ERR(rs->spiclk);
 792                 goto err_put_ctlr;
 793         }
 794
 795         ret = clk_prepare_enable(rs->apb_pclk);
 796         if (ret < 0) {
 797                 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
 798                 goto err_put_ctlr;
 799         }
 800
 801         ret = clk_prepare_enable(rs->spiclk);
 802         if (ret < 0) {
 803                 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
 804                 goto err_disable_apbclk;
 805         }
 806
 807         spi_enable_chip(rs, false);
 808
 809         ret = platform_get_irq(pdev, 0);
 810         if (ret < 0)
 811                 goto err_disable_spiclk;
 812
 813         ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
 814                         IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
 815         if (ret)
 816                 goto err_disable_spiclk;
 817
 818         rs->dev = &pdev->dev;
 819         rs->freq = clk_get_rate(rs->spiclk);
 820
 821         if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
 822                                   &rsd_nsecs)) {
 823                 /* rx sample delay is expressed in parent clock cycles (max 3) */
 824                 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8),
 825                                 1000000000 >> 8);
 826                 if (!rsd) {
 827                         dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n",
 828                                         rs->freq, rsd_nsecs);
 829                 } else if (rsd > CR0_RSD_MAX) {
 830                         rsd = CR0_RSD_MAX;
 831                         dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n",
 832                                         rs->freq, rsd_nsecs,
 833                                         CR0_RSD_MAX * 1000000000U / rs->freq);
 834                 }
 835                 rs->rsd = rsd;
 836         }
 837
 838         rs->fifo_len = get_fifo_len(rs);
 839         if (!rs->fifo_len) {
 840                 dev_err(&pdev->dev, "Failed to get fifo length\n");
 841                 ret = -EINVAL;
 842                 goto err_disable_spiclk;
 843         }
 844
 845         pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT);
 846         pm_runtime_use_autosuspend(&pdev->dev);
 847         pm_runtime_set_active(&pdev->dev);
 848         pm_runtime_enable(&pdev->dev);
 849
 850         ctlr->auto_runtime_pm = true;
 851         ctlr->bus_num = pdev->id;
 852         ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
 853         if (slave_mode) {
 854                 ctlr->mode_bits |= SPI_NO_CS;
 855                 ctlr->slave_abort = rockchip_spi_slave_abort;
 856         } else {
 857                 ctlr->flags = SPI_MASTER_GPIO_SS;
 858                 ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM;
 859                 /*
 860                  * rk spi0 has two native cs, spi1..5 one cs only
 861                  * if num-cs is missing in the dts, default to 1
 862                  */
 863                 if (of_property_read_u32(np, "num-cs", &num_cs))
 864                         num_cs = 1;
 865                 ctlr->num_chipselect = num_cs;
 866                 ctlr->use_gpio_descriptors = true;
 867         }
 868         ctlr->dev.of_node = pdev->dev.of_node;
 869         ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
 870         ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
 871         ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
 872
 873         ctlr->setup = rockchip_spi_setup;
 874         ctlr->set_cs = rockchip_spi_set_cs;
 875         ctlr->transfer_one = rockchip_spi_transfer_one;
 876         ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
 877         ctlr->handle_err = rockchip_spi_handle_err;
 878
 879         ctlr->dma_tx = dma_request_chan(rs->dev, "tx");
 880         if (IS_ERR(ctlr->dma_tx)) {
 881                 /* Check tx to see if we need defer probing driver */
 882                 if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) {
 883                         ret = -EPROBE_DEFER;
 884                         goto err_disable_pm_runtime;
 885                 }
 886                 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
 887                 ctlr->dma_tx = NULL;
 888         }
 889
 890         ctlr->dma_rx = dma_request_chan(rs->dev, "rx");
 891         if (IS_ERR(ctlr->dma_rx)) {
 892                 if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) {
 893                         ret = -EPROBE_DEFER;
 894                         goto err_free_dma_tx;
 895                 }
 896                 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
 897                 ctlr->dma_rx = NULL;
 898         }
 899
 900         if (ctlr->dma_tx && ctlr->dma_rx) {
 901                 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR;
 902                 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR;
 903                 ctlr->can_dma = rockchip_spi_can_dma;
 904         }
 905
 906         switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) {
 907         case ROCKCHIP_SPI_VER2_TYPE2:
 908                 rs->cs_high_supported = true;
 909                 ctlr->mode_bits |= SPI_CS_HIGH;
 910                 if (ctlr->can_dma && slave_mode)
 911                         rs->cs_inactive = true;
 912                 else
 913                         rs->cs_inactive = false;
 914                 break;
 915         default:
 916                 rs->cs_inactive = false;
 917                 break;
 918         }
 919
 920         ret = devm_spi_register_controller(&pdev->dev, ctlr);
 921         if (ret < 0) {
 922                 dev_err(&pdev->dev, "Failed to register controller\n");
 923                 goto err_free_dma_rx;
 924         }
 925
 926         return 0;
 927
 928 err_free_dma_rx:
 929         if (ctlr->dma_rx)
 930                 dma_release_channel(ctlr->dma_rx);
 931 err_free_dma_tx:
 932         if (ctlr->dma_tx)
 933                 dma_release_channel(ctlr->dma_tx);
 934 err_disable_pm_runtime:
 935         pm_runtime_disable(&pdev->dev);
 936 err_disable_spiclk:
 937         clk_disable_unprepare(rs->spiclk);
 938 err_disable_apbclk:
 939         clk_disable_unprepare(rs->apb_pclk);
 940 err_put_ctlr:
 941         spi_controller_put(ctlr);
 942
 943         return ret;
 944 }
 945
 946 static int rockchip_spi_remove(struct platform_device *pdev)
 947 {
 948         struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev));
 949         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 950
 951         pm_runtime_get_sync(&pdev->dev);
 952
 953         clk_disable_unprepare(rs->spiclk);
 954         clk_disable_unprepare(rs->apb_pclk);
 955
 956         pm_runtime_put_noidle(&pdev->dev);
 957         pm_runtime_disable(&pdev->dev);
 958         pm_runtime_set_suspended(&pdev->dev);
 959
 960         if (ctlr->dma_tx)
 961                 dma_release_channel(ctlr->dma_tx);
 962         if (ctlr->dma_rx)
 963                 dma_release_channel(ctlr->dma_rx);
 964
 965         spi_controller_put(ctlr);
 966
 967         return 0;
 968 }
 969
 970 #ifdef CONFIG_PM_SLEEP
 971 static int rockchip_spi_suspend(struct device *dev)
 972 {
 973         int ret;
 974         struct spi_controller *ctlr = dev_get_drvdata(dev);
 975
 976         ret = spi_controller_suspend(ctlr);
 977         if (ret < 0)
 978                 return ret;
 979
 980         ret = pm_runtime_force_suspend(dev);
 981         if (ret < 0)
 982                 return ret;
 983
 984         pinctrl_pm_select_sleep_state(dev);
 985
 986         return 0;
 987 }
 988
 989 static int rockchip_spi_resume(struct device *dev)
 990 {
 991         int ret;
 992         struct spi_controller *ctlr = dev_get_drvdata(dev);
 993         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 994
 995         pinctrl_pm_select_default_state(dev);
 996
 997         ret = pm_runtime_force_resume(dev);
 998         if (ret < 0)
 999                 return ret;
1000
1001         ret = spi_controller_resume(ctlr);
1002         if (ret < 0) {
1003                 clk_disable_unprepare(rs->spiclk);
1004                 clk_disable_unprepare(rs->apb_pclk);
1005         }
1006
1007         return 0;
1008 }
1009 #endif /* CONFIG_PM_SLEEP */
1010
1011 #ifdef CONFIG_PM
1012 static int rockchip_spi_runtime_suspend(struct device *dev)
1013 {
1014         struct spi_controller *ctlr = dev_get_drvdata(dev);
1015         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1016
1017         clk_disable_unprepare(rs->spiclk);
1018         clk_disable_unprepare(rs->apb_pclk);
1019
1020         return 0;
1021 }
1022
1023 static int rockchip_spi_runtime_resume(struct device *dev)
1024 {
1025         int ret;
1026         struct spi_controller *ctlr = dev_get_drvdata(dev);
1027         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1028
1029         ret = clk_prepare_enable(rs->apb_pclk);
1030         if (ret < 0)
1031                 return ret;
1032
1033         ret = clk_prepare_enable(rs->spiclk);
1034         if (ret < 0)
1035                 clk_disable_unprepare(rs->apb_pclk);
1036
1037         return 0;
1038 }
1039 #endif /* CONFIG_PM */
1040
1041 static const struct dev_pm_ops rockchip_spi_pm = {
1042         SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
1043         SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
1044                            rockchip_spi_runtime_resume, NULL)
1045 };
1046
1047 static const struct of_device_id rockchip_spi_dt_match[] = {
1048         { .compatible = "rockchip,px30-spi", },
1049         { .compatible = "rockchip,rk3036-spi", },
1050         { .compatible = "rockchip,rk3066-spi", },
1051         { .compatible = "rockchip,rk3188-spi", },
1052         { .compatible = "rockchip,rk3228-spi", },
1053         { .compatible = "rockchip,rk3288-spi", },
1054         { .compatible = "rockchip,rk3308-spi", },
1055         { .compatible = "rockchip,rk3328-spi", },
1056         { .compatible = "rockchip,rk3368-spi", },
1057         { .compatible = "rockchip,rk3399-spi", },
1058         { .compatible = "rockchip,rv1108-spi", },
1059         { .compatible = "rockchip,rv1126-spi", },
1060         { },
1061 };
1062 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
1063
1064 static struct platform_driver rockchip_spi_driver = {
1065         .driver = {
1066                 .name   = DRIVER_NAME,
1067                 .pm = &rockchip_spi_pm,
1068                 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
1069         },
1070         .probe = rockchip_spi_probe,
1071         .remove = rockchip_spi_remove,
1072 };
1073
1074 module_platform_driver(rockchip_spi_driver);
1075
1076 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
1077 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
1078 MODULE_LICENSE("GPL v2");