drivers/spi/spi-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   4  * Author: Addy Ke <addy.ke@rock-chips.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/dmaengine.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/pinctrl/consumer.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/scatterlist.h>
  17
  18 #define DRIVER_NAME "rockchip-spi"
  19
  20 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
  21                 writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
  22 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \
  23                 writel_relaxed(readl_relaxed(reg) | (bits), reg)
  24
  25 /* SPI register offsets */
  26 #define ROCKCHIP_SPI_CTRLR0                     0x0000
  27 #define ROCKCHIP_SPI_CTRLR1                     0x0004
  28 #define ROCKCHIP_SPI_SSIENR                     0x0008
  29 #define ROCKCHIP_SPI_SER                        0x000c
  30 #define ROCKCHIP_SPI_BAUDR                      0x0010
  31 #define ROCKCHIP_SPI_TXFTLR                     0x0014
  32 #define ROCKCHIP_SPI_RXFTLR                     0x0018
  33 #define ROCKCHIP_SPI_TXFLR                      0x001c
  34 #define ROCKCHIP_SPI_RXFLR                      0x0020
  35 #define ROCKCHIP_SPI_SR                         0x0024
  36 #define ROCKCHIP_SPI_IPR                        0x0028
  37 #define ROCKCHIP_SPI_IMR                        0x002c
  38 #define ROCKCHIP_SPI_ISR                        0x0030
  39 #define ROCKCHIP_SPI_RISR                       0x0034
  40 #define ROCKCHIP_SPI_ICR                        0x0038
  41 #define ROCKCHIP_SPI_DMACR                      0x003c
  42 #define ROCKCHIP_SPI_DMATDLR                    0x0040
  43 #define ROCKCHIP_SPI_DMARDLR                    0x0044
  44 #define ROCKCHIP_SPI_VERSION                    0x0048
  45 #define ROCKCHIP_SPI_TXDR                       0x0400
  46 #define ROCKCHIP_SPI_RXDR                       0x0800
  47
  48 /* Bit fields in CTRLR0 */
  49 #define CR0_DFS_OFFSET                          0
  50 #define CR0_DFS_4BIT                            0x0
  51 #define CR0_DFS_8BIT                            0x1
  52 #define CR0_DFS_16BIT                           0x2
  53
  54 #define CR0_CFS_OFFSET                          2
  55
  56 #define CR0_SCPH_OFFSET                         6
  57
  58 #define CR0_SCPOL_OFFSET                        7
  59
  60 #define CR0_CSM_OFFSET                          8
  61 #define CR0_CSM_KEEP                            0x0
  62 /* ss_n be high for half sclk_out cycles */
  63 #define CR0_CSM_HALF                            0X1
  64 /* ss_n be high for one sclk_out cycle */
  65 #define CR0_CSM_ONE                                     0x2
  66
  67 /* ss_n to sclk_out delay */
  68 #define CR0_SSD_OFFSET                          10
  69 /*
  70  * The period between ss_n active and
  71  * sclk_out active is half sclk_out cycles
  72  */
  73 #define CR0_SSD_HALF                            0x0
  74 /*
  75  * The period between ss_n active and
  76  * sclk_out active is one sclk_out cycle
  77  */
  78 #define CR0_SSD_ONE                                     0x1
  79
  80 #define CR0_EM_OFFSET                           11
  81 #define CR0_EM_LITTLE                           0x0
  82 #define CR0_EM_BIG                                      0x1
  83
  84 #define CR0_FBM_OFFSET                          12
  85 #define CR0_FBM_MSB                                     0x0
  86 #define CR0_FBM_LSB                                     0x1
  87
  88 #define CR0_BHT_OFFSET                          13
  89 #define CR0_BHT_16BIT                           0x0
  90 #define CR0_BHT_8BIT                            0x1
  91
  92 #define CR0_RSD_OFFSET                          14
  93 #define CR0_RSD_MAX                             0x3
  94
  95 #define CR0_FRF_OFFSET                          16
  96 #define CR0_FRF_SPI                                     0x0
  97 #define CR0_FRF_SSP                                     0x1
  98 #define CR0_FRF_MICROWIRE                       0x2
  99
 100 #define CR0_XFM_OFFSET                          18
 101 #define CR0_XFM_MASK                            (0x03 << SPI_XFM_OFFSET)
 102 #define CR0_XFM_TR                                      0x0
 103 #define CR0_XFM_TO                                      0x1
 104 #define CR0_XFM_RO                                      0x2
 105
 106 #define CR0_OPM_OFFSET                          20
 107 #define CR0_OPM_MASTER                          0x0
 108 #define CR0_OPM_SLAVE                           0x1
 109
 110 #define CR0_SOI_OFFSET                          23
 111
 112 #define CR0_MTM_OFFSET                          0x21
 113
 114 /* Bit fields in SER, 2bit */
 115 #define SER_MASK                                        0x3
 116
 117 /* Bit fields in BAUDR */
 118 #define BAUDR_SCKDV_MIN                         2
 119 #define BAUDR_SCKDV_MAX                         65534
 120
 121 /* Bit fields in SR, 6bit */
 122 #define SR_MASK                                         0x3f
 123 #define SR_BUSY                                         (1 << 0)
 124 #define SR_TF_FULL                                      (1 << 1)
 125 #define SR_TF_EMPTY                                     (1 << 2)
 126 #define SR_RF_EMPTY                                     (1 << 3)
 127 #define SR_RF_FULL                                      (1 << 4)
 128 #define SR_SLAVE_TX_BUSY                                (1 << 5)
 129
 130 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
 131 #define INT_MASK                                        0x1f
 132 #define INT_TF_EMPTY                            (1 << 0)
 133 #define INT_TF_OVERFLOW                         (1 << 1)
 134 #define INT_RF_UNDERFLOW                        (1 << 2)
 135 #define INT_RF_OVERFLOW                         (1 << 3)
 136 #define INT_RF_FULL                             (1 << 4)
 137 #define INT_CS_INACTIVE                         (1 << 6)
 138
 139 /* Bit fields in ICR, 4bit */
 140 #define ICR_MASK                                        0x0f
 141 #define ICR_ALL                                         (1 << 0)
 142 #define ICR_RF_UNDERFLOW                        (1 << 1)
 143 #define ICR_RF_OVERFLOW                         (1 << 2)
 144 #define ICR_TF_OVERFLOW                         (1 << 3)
 145
 146 /* Bit fields in DMACR */
 147 #define RF_DMA_EN                                       (1 << 0)
 148 #define TF_DMA_EN                                       (1 << 1)
 149
 150 /* Driver state flags */
 151 #define RXDMA                                   (1 << 0)
 152 #define TXDMA                                   (1 << 1)
 153
 154 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
 155 #define MAX_SCLK_OUT                            50000000U
 156
 157 /*
 158  * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
 159  * the controller seems to hang when given 0x10000, so stick with this for now.
 160  */
 161 #define ROCKCHIP_SPI_MAX_TRANLEN                0xffff
 162
 163 /* 2 for native cs, 2 for cs-gpio */
 164 #define ROCKCHIP_SPI_MAX_CS_NUM                 4
 165 #define ROCKCHIP_SPI_VER2_TYPE1                 0x05EC0002
 166 #define ROCKCHIP_SPI_VER2_TYPE2                 0x00110002
 167
 168 #define ROCKCHIP_AUTOSUSPEND_TIMEOUT            2000
 169
 170 struct rockchip_spi {
 171         struct device *dev;
 172
 173         struct clk *spiclk;
 174         struct clk *apb_pclk;
 175
 176         void __iomem *regs;
 177         dma_addr_t dma_addr_rx;
 178         dma_addr_t dma_addr_tx;
 179
 180         const void *tx;
 181         void *rx;
 182         unsigned int tx_left;
 183         unsigned int rx_left;
 184
 185         atomic_t state;
 186
 187         /*depth of the FIFO buffer */
 188         u32 fifo_len;
 189         /* frequency of spiclk */
 190         u32 freq;
 191
 192         u8 n_bytes;
 193         u8 rsd;
 194
 195         bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
 196
 197         bool slave_abort;
 198         bool cs_inactive; /* spi slave tansmition stop when cs inactive */
 199         struct spi_transfer *xfer; /* Store xfer temporarily */
 200 };
 201
 202 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
 203 {
 204         writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
 205 }
 206
 207 static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool slave_mode)
 208 {
 209         unsigned long timeout = jiffies + msecs_to_jiffies(5);
 210
 211         do {
 212                 if (slave_mode) {
 213                         if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_SLAVE_TX_BUSY) &&
 214                             !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)))
 215                                 return;
 216                 } else {
 217                         if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
 218                                 return;
 219                 }
 220         } while (!time_after(jiffies, timeout));
 221
 222         dev_warn(rs->dev, "spi controller is in busy state!\n");
 223 }
 224
 225 static u32 get_fifo_len(struct rockchip_spi *rs)
 226 {
 227         u32 ver;
 228
 229         ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
 230
 231         switch (ver) {
 232         case ROCKCHIP_SPI_VER2_TYPE1:
 233         case ROCKCHIP_SPI_VER2_TYPE2:
 234                 return 64;
 235         default:
 236                 return 32;
 237         }
 238 }
 239
 240 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
 241 {
 242         struct spi_controller *ctlr = spi->controller;
 243         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 244         bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable;
 245
 246         /* Return immediately for no-op */
 247         if (cs_asserted == rs->cs_asserted[spi->chip_select])
 248                 return;
 249
 250         if (cs_asserted) {
 251                 /* Keep things powered as long as CS is asserted */
 252                 pm_runtime_get_sync(rs->dev);
 253
 254                 if (spi->cs_gpiod)
 255                         ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
 256                 else
 257                         ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
 258         } else {
 259                 if (spi->cs_gpiod)
 260                         ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
 261                 else
 262                         ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
 263
 264                 /* Drop reference from when we first asserted CS */
 265                 pm_runtime_put(rs->dev);
 266         }
 267
 268         rs->cs_asserted[spi->chip_select] = cs_asserted;
 269 }
 270
 271 static void rockchip_spi_handle_err(struct spi_controller *ctlr,
 272                                     struct spi_message *msg)
 273 {
 274         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 275
 276         /* stop running spi transfer
 277          * this also flushes both rx and tx fifos
 278          */
 279         spi_enable_chip(rs, false);
 280
 281         /* make sure all interrupts are masked */
 282         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 283
 284         if (atomic_read(&rs->state) & TXDMA)
 285                 dmaengine_terminate_async(ctlr->dma_tx);
 286
 287         if (atomic_read(&rs->state) & RXDMA)
 288                 dmaengine_terminate_async(ctlr->dma_rx);
 289 }
 290
 291 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
 292 {
 293         u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
 294         u32 words = min(rs->tx_left, tx_free);
 295
 296         rs->tx_left -= words;
 297         for (; words; words--) {
 298                 u32 txw;
 299
 300                 if (rs->n_bytes == 1)
 301                         txw = *(u8 *)rs->tx;
 302                 else
 303                         txw = *(u16 *)rs->tx;
 304
 305                 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
 306                 rs->tx += rs->n_bytes;
 307         }
 308 }
 309
 310 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
 311 {
 312         u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 313         u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0;
 314
 315         /* the hardware doesn't allow us to change fifo threshold
 316          * level while spi is enabled, so instead make sure to leave
 317          * enough words in the rx fifo to get the last interrupt
 318          * exactly when all words have been received
 319          */
 320         if (rx_left) {
 321                 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1;
 322
 323                 if (rx_left < ftl) {
 324                         rx_left = ftl;
 325                         words = rs->rx_left - rx_left;
 326                 }
 327         }
 328
 329         rs->rx_left = rx_left;
 330         for (; words; words--) {
 331                 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 332
 333                 if (!rs->rx)
 334                         continue;
 335
 336                 if (rs->n_bytes == 1)
 337                         *(u8 *)rs->rx = (u8)rxw;
 338                 else
 339                         *(u16 *)rs->rx = (u16)rxw;
 340                 rs->rx += rs->n_bytes;
 341         }
 342 }
 343
 344 static irqreturn_t rockchip_spi_isr(int irq, void *dev_id)
 345 {
 346         struct spi_controller *ctlr = dev_id;
 347         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 348
 349         /* When int_cs_inactive comes, spi slave abort */
 350         if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_IMR) & INT_CS_INACTIVE) {
 351                 ctlr->slave_abort(ctlr);
 352                 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 353                 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
 354
 355                 return IRQ_HANDLED;
 356         }
 357
 358         if (rs->tx_left)
 359                 rockchip_spi_pio_writer(rs);
 360
 361         rockchip_spi_pio_reader(rs);
 362         if (!rs->rx_left) {
 363                 spi_enable_chip(rs, false);
 364                 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 365                 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
 366                 spi_finalize_current_transfer(ctlr);
 367         }
 368
 369         return IRQ_HANDLED;
 370 }
 371
 372 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs,
 373                                     struct spi_controller *ctlr,
 374                                     struct spi_transfer *xfer)
 375 {
 376         rs->tx = xfer->tx_buf;
 377         rs->rx = xfer->rx_buf;
 378         rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
 379         rs->rx_left = xfer->len / rs->n_bytes;
 380
 381         if (rs->cs_inactive)
 382                 writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
 383         else
 384                 writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
 385         spi_enable_chip(rs, true);
 386
 387         if (rs->tx_left)
 388                 rockchip_spi_pio_writer(rs);
 389
 390         /* 1 means the transfer is in progress */
 391         return 1;
 392 }
 393
 394 static void rockchip_spi_dma_rxcb(void *data)
 395 {
 396         struct spi_controller *ctlr = data;
 397         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 398         int state = atomic_fetch_andnot(RXDMA, &rs->state);
 399
 400         if (state & TXDMA && !rs->slave_abort)
 401                 return;
 402
 403         if (rs->cs_inactive)
 404                 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 405
 406         spi_enable_chip(rs, false);
 407         spi_finalize_current_transfer(ctlr);
 408 }
 409
 410 static void rockchip_spi_dma_txcb(void *data)
 411 {
 412         struct spi_controller *ctlr = data;
 413         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 414         int state = atomic_fetch_andnot(TXDMA, &rs->state);
 415
 416         if (state & RXDMA && !rs->slave_abort)
 417                 return;
 418
 419         /* Wait until the FIFO data completely. */
 420         wait_for_tx_idle(rs, ctlr->slave);
 421
 422         spi_enable_chip(rs, false);
 423         spi_finalize_current_transfer(ctlr);
 424 }
 425
 426 static u32 rockchip_spi_calc_burst_size(u32 data_len)
 427 {
 428         u32 i;
 429
 430         /* burst size: 1, 2, 4, 8 */
 431         for (i = 1; i < 8; i <<= 1) {
 432                 if (data_len & i)
 433                         break;
 434         }
 435
 436         return i;
 437 }
 438
 439 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs,
 440                 struct spi_controller *ctlr, struct spi_transfer *xfer)
 441 {
 442         struct dma_async_tx_descriptor *rxdesc, *txdesc;
 443
 444         atomic_set(&rs->state, 0);
 445
 446         rs->tx = xfer->tx_buf;
 447         rs->rx = xfer->rx_buf;
 448
 449         rxdesc = NULL;
 450         if (xfer->rx_buf) {
 451                 struct dma_slave_config rxconf = {
 452                         .direction = DMA_DEV_TO_MEM,
 453                         .src_addr = rs->dma_addr_rx,
 454                         .src_addr_width = rs->n_bytes,
 455                         .src_maxburst = rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes),
 456                 };
 457
 458                 dmaengine_slave_config(ctlr->dma_rx, &rxconf);
 459
 460                 rxdesc = dmaengine_prep_slave_sg(
 461                                 ctlr->dma_rx,
 462                                 xfer->rx_sg.sgl, xfer->rx_sg.nents,
 463                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
 464                 if (!rxdesc)
 465                         return -EINVAL;
 466
 467                 rxdesc->callback = rockchip_spi_dma_rxcb;
 468                 rxdesc->callback_param = ctlr;
 469         }
 470
 471         txdesc = NULL;
 472         if (xfer->tx_buf) {
 473                 struct dma_slave_config txconf = {
 474                         .direction = DMA_MEM_TO_DEV,
 475                         .dst_addr = rs->dma_addr_tx,
 476                         .dst_addr_width = rs->n_bytes,
 477                         .dst_maxburst = rs->fifo_len / 4,
 478                 };
 479
 480                 dmaengine_slave_config(ctlr->dma_tx, &txconf);
 481
 482                 txdesc = dmaengine_prep_slave_sg(
 483                                 ctlr->dma_tx,
 484                                 xfer->tx_sg.sgl, xfer->tx_sg.nents,
 485                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 486                 if (!txdesc) {
 487                         if (rxdesc)
 488                                 dmaengine_terminate_sync(ctlr->dma_rx);
 489                         return -EINVAL;
 490                 }
 491
 492                 txdesc->callback = rockchip_spi_dma_txcb;
 493                 txdesc->callback_param = ctlr;
 494         }
 495
 496         /* rx must be started before tx due to spi instinct */
 497         if (rxdesc) {
 498                 atomic_or(RXDMA, &rs->state);
 499                 ctlr->dma_rx->cookie = dmaengine_submit(rxdesc);
 500                 dma_async_issue_pending(ctlr->dma_rx);
 501         }
 502
 503         if (rs->cs_inactive)
 504                 writel_relaxed(INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
 505
 506         spi_enable_chip(rs, true);
 507
 508         if (txdesc) {
 509                 atomic_or(TXDMA, &rs->state);
 510                 dmaengine_submit(txdesc);
 511                 dma_async_issue_pending(ctlr->dma_tx);
 512         }
 513
 514         /* 1 means the transfer is in progress */
 515         return 1;
 516 }
 517
 518 static int rockchip_spi_config(struct rockchip_spi *rs,
 519                 struct spi_device *spi, struct spi_transfer *xfer,
 520                 bool use_dma, bool slave_mode)
 521 {
 522         u32 cr0 = CR0_FRF_SPI  << CR0_FRF_OFFSET
 523                 | CR0_BHT_8BIT << CR0_BHT_OFFSET
 524                 | CR0_SSD_ONE  << CR0_SSD_OFFSET
 525                 | CR0_EM_BIG   << CR0_EM_OFFSET;
 526         u32 cr1;
 527         u32 dmacr = 0;
 528
 529         if (slave_mode)
 530                 cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET;
 531         rs->slave_abort = false;
 532
 533         cr0 |= rs->rsd << CR0_RSD_OFFSET;
 534         cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
 535         if (spi->mode & SPI_LSB_FIRST)
 536                 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
 537         if (spi->mode & SPI_CS_HIGH)
 538                 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
 539
 540         if (xfer->rx_buf && xfer->tx_buf)
 541                 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
 542         else if (xfer->rx_buf)
 543                 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;
 544         else if (use_dma)
 545                 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
 546
 547         switch (xfer->bits_per_word) {
 548         case 4:
 549                 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET;
 550                 cr1 = xfer->len - 1;
 551                 break;
 552         case 8:
 553                 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET;
 554                 cr1 = xfer->len - 1;
 555                 break;
 556         case 16:
 557                 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET;
 558                 cr1 = xfer->len / 2 - 1;
 559                 break;
 560         default:
 561                 /* we only whitelist 4, 8 and 16 bit words in
 562                  * ctlr->bits_per_word_mask, so this shouldn't
 563                  * happen
 564                  */
 565                 dev_err(rs->dev, "unknown bits per word: %d\n",
 566                         xfer->bits_per_word);
 567                 return -EINVAL;
 568         }
 569
 570         if (use_dma) {
 571                 if (xfer->tx_buf)
 572                         dmacr |= TF_DMA_EN;
 573                 if (xfer->rx_buf)
 574                         dmacr |= RF_DMA_EN;
 575         }
 576
 577         writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
 578         writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 579
 580         /* unfortunately setting the fifo threshold level to generate an
 581          * interrupt exactly when the fifo is full doesn't seem to work,
 582          * so we need the strict inequality here
 583          */
 584         if ((xfer->len / rs->n_bytes) < rs->fifo_len)
 585                 writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 586         else
 587                 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 588
 589         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
 590         writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1,
 591                        rs->regs + ROCKCHIP_SPI_DMARDLR);
 592         writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
 593
 594         /* the hardware only supports an even clock divisor, so
 595          * round divisor = spiclk / speed up to nearest even number
 596          * so that the resulting speed is <= the requested speed
 597          */
 598         writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz),
 599                         rs->regs + ROCKCHIP_SPI_BAUDR);
 600
 601         return 0;
 602 }
 603
 604 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
 605 {
 606         return ROCKCHIP_SPI_MAX_TRANLEN;
 607 }
 608
 609 static int rockchip_spi_slave_abort(struct spi_controller *ctlr)
 610 {
 611         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 612         u32 rx_fifo_left;
 613         struct dma_tx_state state;
 614         enum dma_status status;
 615
 616         /* Get current dma rx point */
 617         if (atomic_read(&rs->state) & RXDMA) {
 618                 dmaengine_pause(ctlr->dma_rx);
 619                 status = dmaengine_tx_status(ctlr->dma_rx, ctlr->dma_rx->cookie, &state);
 620                 if (status == DMA_ERROR) {
 621                         rs->rx = rs->xfer->rx_buf;
 622                         rs->xfer->len = 0;
 623                         rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 624                         for (; rx_fifo_left; rx_fifo_left--)
 625                                 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 626                         goto out;
 627                 } else {
 628                         rs->rx += rs->xfer->len - rs->n_bytes * state.residue;
 629                 }
 630         }
 631
 632         /* Get the valid data left in rx fifo and set rs->xfer->len real rx size */
 633         if (rs->rx) {
 634                 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 635                 for (; rx_fifo_left; rx_fifo_left--) {
 636                         u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 637
 638                         if (rs->n_bytes == 1)
 639                                 *(u8 *)rs->rx = (u8)rxw;
 640                         else
 641                                 *(u16 *)rs->rx = (u16)rxw;
 642                         rs->rx += rs->n_bytes;
 643                 }
 644                 rs->xfer->len = (unsigned int)(rs->rx - rs->xfer->rx_buf);
 645         }
 646
 647 out:
 648         if (atomic_read(&rs->state) & RXDMA)
 649                 dmaengine_terminate_sync(ctlr->dma_rx);
 650         if (atomic_read(&rs->state) & TXDMA)
 651                 dmaengine_terminate_sync(ctlr->dma_tx);
 652         atomic_set(&rs->state, 0);
 653         spi_enable_chip(rs, false);
 654         rs->slave_abort = true;
 655         spi_finalize_current_transfer(ctlr);
 656
 657         return 0;
 658 }
 659
 660 static int rockchip_spi_transfer_one(
 661                 struct spi_controller *ctlr,
 662                 struct spi_device *spi,
 663                 struct spi_transfer *xfer)
 664 {
 665         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 666         int ret;
 667         bool use_dma;
 668
 669         /* Zero length transfers won't trigger an interrupt on completion */
 670         if (!xfer->len) {
 671                 spi_finalize_current_transfer(ctlr);
 672                 return 1;
 673         }
 674
 675         WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
 676                 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
 677
 678         if (!xfer->tx_buf && !xfer->rx_buf) {
 679                 dev_err(rs->dev, "No buffer for transfer\n");
 680                 return -EINVAL;
 681         }
 682
 683         if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
 684                 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
 685                 return -EINVAL;
 686         }
 687
 688         rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
 689         rs->xfer = xfer;
 690         use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
 691
 692         ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave);
 693         if (ret)
 694                 return ret;
 695
 696         if (use_dma)
 697                 return rockchip_spi_prepare_dma(rs, ctlr, xfer);
 698
 699         return rockchip_spi_prepare_irq(rs, ctlr, xfer);
 700 }
 701
 702 static bool rockchip_spi_can_dma(struct spi_controller *ctlr,
 703                                  struct spi_device *spi,
 704                                  struct spi_transfer *xfer)
 705 {
 706         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 707         unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2;
 708
 709         /* if the numbor of spi words to transfer is less than the fifo
 710          * length we can just fill the fifo and wait for a single irq,
 711          * so don't bother setting up dma
 712          */
 713         return xfer->len / bytes_per_word >= rs->fifo_len;
 714 }
 715
 716 static int rockchip_spi_setup(struct spi_device *spi)
 717 {
 718         struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
 719         u32 cr0;
 720
 721         pm_runtime_get_sync(rs->dev);
 722
 723         cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0);
 724
 725         cr0 &= ~(0x3 << CR0_SCPH_OFFSET);
 726         cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET);
 727         if (spi->mode & SPI_CS_HIGH && spi->chip_select <= 1)
 728                 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
 729         else if (spi->chip_select <= 1)
 730                 cr0 &= ~(BIT(spi->chip_select) << CR0_SOI_OFFSET);
 731
 732         writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
 733
 734         pm_runtime_put(rs->dev);
 735
 736         return 0;
 737 }
 738
 739 static int rockchip_spi_probe(struct platform_device *pdev)
 740 {
 741         int ret;
 742         struct rockchip_spi *rs;
 743         struct spi_controller *ctlr;
 744         struct resource *mem;
 745         struct device_node *np = pdev->dev.of_node;
 746         u32 rsd_nsecs, num_cs;
 747         bool slave_mode;
 748
 749         slave_mode = of_property_read_bool(np, "spi-slave");
 750
 751         if (slave_mode)
 752                 ctlr = spi_alloc_slave(&pdev->dev,
 753                                 sizeof(struct rockchip_spi));
 754         else
 755                 ctlr = spi_alloc_master(&pdev->dev,
 756                                 sizeof(struct rockchip_spi));
 757
 758         if (!ctlr)
 759                 return -ENOMEM;
 760
 761         platform_set_drvdata(pdev, ctlr);
 762
 763         rs = spi_controller_get_devdata(ctlr);
 764         ctlr->slave = slave_mode;
 765
 766         /* Get basic io resource and map it */
 767         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 768         rs->regs = devm_ioremap_resource(&pdev->dev, mem);
 769         if (IS_ERR(rs->regs)) {
 770                 ret =  PTR_ERR(rs->regs);
 771                 goto err_put_ctlr;
 772         }
 773
 774         rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
 775         if (IS_ERR(rs->apb_pclk)) {
 776                 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
 777                 ret = PTR_ERR(rs->apb_pclk);
 778                 goto err_put_ctlr;
 779         }
 780
 781         rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
 782         if (IS_ERR(rs->spiclk)) {
 783                 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
 784                 ret = PTR_ERR(rs->spiclk);
 785                 goto err_put_ctlr;
 786         }
 787
 788         ret = clk_prepare_enable(rs->apb_pclk);
 789         if (ret < 0) {
 790                 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
 791                 goto err_put_ctlr;
 792         }
 793
 794         ret = clk_prepare_enable(rs->spiclk);
 795         if (ret < 0) {
 796                 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
 797                 goto err_disable_apbclk;
 798         }
 799
 800         spi_enable_chip(rs, false);
 801
 802         ret = platform_get_irq(pdev, 0);
 803         if (ret < 0)
 804                 goto err_disable_spiclk;
 805
 806         ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
 807                         IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
 808         if (ret)
 809                 goto err_disable_spiclk;
 810
 811         rs->dev = &pdev->dev;
 812         rs->freq = clk_get_rate(rs->spiclk);
 813
 814         if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
 815                                   &rsd_nsecs)) {
 816                 /* rx sample delay is expressed in parent clock cycles (max 3) */
 817                 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8),
 818                                 1000000000 >> 8);
 819                 if (!rsd) {
 820                         dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n",
 821                                         rs->freq, rsd_nsecs);
 822                 } else if (rsd > CR0_RSD_MAX) {
 823                         rsd = CR0_RSD_MAX;
 824                         dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n",
 825                                         rs->freq, rsd_nsecs,
 826                                         CR0_RSD_MAX * 1000000000U / rs->freq);
 827                 }
 828                 rs->rsd = rsd;
 829         }
 830
 831         rs->fifo_len = get_fifo_len(rs);
 832         if (!rs->fifo_len) {
 833                 dev_err(&pdev->dev, "Failed to get fifo length\n");
 834                 ret = -EINVAL;
 835                 goto err_disable_spiclk;
 836         }
 837
 838         pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT);
 839         pm_runtime_use_autosuspend(&pdev->dev);
 840         pm_runtime_set_active(&pdev->dev);
 841         pm_runtime_enable(&pdev->dev);
 842
 843         ctlr->auto_runtime_pm = true;
 844         ctlr->bus_num = pdev->id;
 845         ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
 846         if (slave_mode) {
 847                 ctlr->mode_bits |= SPI_NO_CS;
 848                 ctlr->slave_abort = rockchip_spi_slave_abort;
 849         } else {
 850                 ctlr->flags = SPI_MASTER_GPIO_SS;
 851                 ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM;
 852                 /*
 853                  * rk spi0 has two native cs, spi1..5 one cs only
 854                  * if num-cs is missing in the dts, default to 1
 855                  */
 856                 if (of_property_read_u32(np, "num-cs", &num_cs))
 857                         num_cs = 1;
 858                 ctlr->num_chipselect = num_cs;
 859                 ctlr->use_gpio_descriptors = true;
 860         }
 861         ctlr->dev.of_node = pdev->dev.of_node;
 862         ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
 863         ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
 864         ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
 865
 866         ctlr->setup = rockchip_spi_setup;
 867         ctlr->set_cs = rockchip_spi_set_cs;
 868         ctlr->transfer_one = rockchip_spi_transfer_one;
 869         ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
 870         ctlr->handle_err = rockchip_spi_handle_err;
 871
 872         ctlr->dma_tx = dma_request_chan(rs->dev, "tx");
 873         if (IS_ERR(ctlr->dma_tx)) {
 874                 /* Check tx to see if we need defer probing driver */
 875                 if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) {
 876                         ret = -EPROBE_DEFER;
 877                         goto err_disable_pm_runtime;
 878                 }
 879                 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
 880                 ctlr->dma_tx = NULL;
 881         }
 882
 883         ctlr->dma_rx = dma_request_chan(rs->dev, "rx");
 884         if (IS_ERR(ctlr->dma_rx)) {
 885                 if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) {
 886                         ret = -EPROBE_DEFER;
 887                         goto err_free_dma_tx;
 888                 }
 889                 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
 890                 ctlr->dma_rx = NULL;
 891         }
 892
 893         if (ctlr->dma_tx && ctlr->dma_rx) {
 894                 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR;
 895                 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR;
 896                 ctlr->can_dma = rockchip_spi_can_dma;
 897         }
 898
 899         switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) {
 900         case ROCKCHIP_SPI_VER2_TYPE2:
 901                 ctlr->mode_bits |= SPI_CS_HIGH;
 902                 if (ctlr->can_dma && slave_mode)
 903                         rs->cs_inactive = true;
 904                 else
 905                         rs->cs_inactive = false;
 906                 break;
 907         default:
 908                 rs->cs_inactive = false;
 909                 break;
 910         }
 911
 912         ret = devm_spi_register_controller(&pdev->dev, ctlr);
 913         if (ret < 0) {
 914                 dev_err(&pdev->dev, "Failed to register controller\n");
 915                 goto err_free_dma_rx;
 916         }
 917
 918         return 0;
 919
 920 err_free_dma_rx:
 921         if (ctlr->dma_rx)
 922                 dma_release_channel(ctlr->dma_rx);
 923 err_free_dma_tx:
 924         if (ctlr->dma_tx)
 925                 dma_release_channel(ctlr->dma_tx);
 926 err_disable_pm_runtime:
 927         pm_runtime_disable(&pdev->dev);
 928 err_disable_spiclk:
 929         clk_disable_unprepare(rs->spiclk);
 930 err_disable_apbclk:
 931         clk_disable_unprepare(rs->apb_pclk);
 932 err_put_ctlr:
 933         spi_controller_put(ctlr);
 934
 935         return ret;
 936 }
 937
 938 static int rockchip_spi_remove(struct platform_device *pdev)
 939 {
 940         struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev));
 941         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 942
 943         pm_runtime_get_sync(&pdev->dev);
 944
 945         clk_disable_unprepare(rs->spiclk);
 946         clk_disable_unprepare(rs->apb_pclk);
 947
 948         pm_runtime_put_noidle(&pdev->dev);
 949         pm_runtime_disable(&pdev->dev);
 950         pm_runtime_set_suspended(&pdev->dev);
 951
 952         if (ctlr->dma_tx)
 953                 dma_release_channel(ctlr->dma_tx);
 954         if (ctlr->dma_rx)
 955                 dma_release_channel(ctlr->dma_rx);
 956
 957         spi_controller_put(ctlr);
 958
 959         return 0;
 960 }
 961
 962 #ifdef CONFIG_PM_SLEEP
 963 static int rockchip_spi_suspend(struct device *dev)
 964 {
 965         int ret;
 966         struct spi_controller *ctlr = dev_get_drvdata(dev);
 967
 968         ret = spi_controller_suspend(ctlr);
 969         if (ret < 0)
 970                 return ret;
 971
 972         ret = pm_runtime_force_suspend(dev);
 973         if (ret < 0)
 974                 return ret;
 975
 976         pinctrl_pm_select_sleep_state(dev);
 977
 978         return 0;
 979 }
 980
 981 static int rockchip_spi_resume(struct device *dev)
 982 {
 983         int ret;
 984         struct spi_controller *ctlr = dev_get_drvdata(dev);
 985         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 986
 987         pinctrl_pm_select_default_state(dev);
 988
 989         ret = pm_runtime_force_resume(dev);
 990         if (ret < 0)
 991                 return ret;
 992
 993         ret = spi_controller_resume(ctlr);
 994         if (ret < 0) {
 995                 clk_disable_unprepare(rs->spiclk);
 996                 clk_disable_unprepare(rs->apb_pclk);
 997         }
 998
 999         return 0;
1000 }
1001 #endif /* CONFIG_PM_SLEEP */
1002
1003 #ifdef CONFIG_PM
1004 static int rockchip_spi_runtime_suspend(struct device *dev)
1005 {
1006         struct spi_controller *ctlr = dev_get_drvdata(dev);
1007         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1008
1009         clk_disable_unprepare(rs->spiclk);
1010         clk_disable_unprepare(rs->apb_pclk);
1011
1012         return 0;
1013 }
1014
1015 static int rockchip_spi_runtime_resume(struct device *dev)
1016 {
1017         int ret;
1018         struct spi_controller *ctlr = dev_get_drvdata(dev);
1019         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1020
1021         ret = clk_prepare_enable(rs->apb_pclk);
1022         if (ret < 0)
1023                 return ret;
1024
1025         ret = clk_prepare_enable(rs->spiclk);
1026         if (ret < 0)
1027                 clk_disable_unprepare(rs->apb_pclk);
1028
1029         return 0;
1030 }
1031 #endif /* CONFIG_PM */
1032
1033 static const struct dev_pm_ops rockchip_spi_pm = {
1034         SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
1035         SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
1036                            rockchip_spi_runtime_resume, NULL)
1037 };
1038
1039 static const struct of_device_id rockchip_spi_dt_match[] = {
1040         { .compatible = "rockchip,px30-spi", },
1041         { .compatible = "rockchip,rk3036-spi", },
1042         { .compatible = "rockchip,rk3066-spi", },
1043         { .compatible = "rockchip,rk3188-spi", },
1044         { .compatible = "rockchip,rk3228-spi", },
1045         { .compatible = "rockchip,rk3288-spi", },
1046         { .compatible = "rockchip,rk3308-spi", },
1047         { .compatible = "rockchip,rk3328-spi", },
1048         { .compatible = "rockchip,rk3368-spi", },
1049         { .compatible = "rockchip,rk3399-spi", },
1050         { .compatible = "rockchip,rv1108-spi", },
1051         { .compatible = "rockchip,rv1126-spi", },
1052         { },
1053 };
1054 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
1055
1056 static struct platform_driver rockchip_spi_driver = {
1057         .driver = {
1058                 .name   = DRIVER_NAME,
1059                 .pm = &rockchip_spi_pm,
1060                 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
1061         },
1062         .probe = rockchip_spi_probe,
1063         .remove = rockchip_spi_remove,
1064 };
1065
1066 module_platform_driver(rockchip_spi_driver);
1067
1068 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
1069 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
1070 MODULE_LICENSE("GPL v2");