drivers/spi/spi-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   4  * Author: Addy Ke <addy.ke@rock-chips.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/dmaengine.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/pinctrl/consumer.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/scatterlist.h>
  17
  18 #define DRIVER_NAME "rockchip-spi"
  19
  20 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
  21                 writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
  22 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \
  23                 writel_relaxed(readl_relaxed(reg) | (bits), reg)
  24
  25 /* SPI register offsets */
  26 #define ROCKCHIP_SPI_CTRLR0                     0x0000
  27 #define ROCKCHIP_SPI_CTRLR1                     0x0004
  28 #define ROCKCHIP_SPI_SSIENR                     0x0008
  29 #define ROCKCHIP_SPI_SER                        0x000c
  30 #define ROCKCHIP_SPI_BAUDR                      0x0010
  31 #define ROCKCHIP_SPI_TXFTLR                     0x0014
  32 #define ROCKCHIP_SPI_RXFTLR                     0x0018
  33 #define ROCKCHIP_SPI_TXFLR                      0x001c
  34 #define ROCKCHIP_SPI_RXFLR                      0x0020
  35 #define ROCKCHIP_SPI_SR                         0x0024
  36 #define ROCKCHIP_SPI_IPR                        0x0028
  37 #define ROCKCHIP_SPI_IMR                        0x002c
  38 #define ROCKCHIP_SPI_ISR                        0x0030
  39 #define ROCKCHIP_SPI_RISR                       0x0034
  40 #define ROCKCHIP_SPI_ICR                        0x0038
  41 #define ROCKCHIP_SPI_DMACR                      0x003c
  42 #define ROCKCHIP_SPI_DMATDLR                    0x0040
  43 #define ROCKCHIP_SPI_DMARDLR                    0x0044
  44 #define ROCKCHIP_SPI_VERSION                    0x0048
  45 #define ROCKCHIP_SPI_TXDR                       0x0400
  46 #define ROCKCHIP_SPI_RXDR                       0x0800
  47
  48 /* Bit fields in CTRLR0 */
  49 #define CR0_DFS_OFFSET                          0
  50 #define CR0_DFS_4BIT                            0x0
  51 #define CR0_DFS_8BIT                            0x1
  52 #define CR0_DFS_16BIT                           0x2
  53
  54 #define CR0_CFS_OFFSET                          2
  55
  56 #define CR0_SCPH_OFFSET                         6
  57
  58 #define CR0_SCPOL_OFFSET                        7
  59
  60 #define CR0_CSM_OFFSET                          8
  61 #define CR0_CSM_KEEP                            0x0
  62 /* ss_n be high for half sclk_out cycles */
  63 #define CR0_CSM_HALF                            0X1
  64 /* ss_n be high for one sclk_out cycle */
  65 #define CR0_CSM_ONE                                     0x2
  66
  67 /* ss_n to sclk_out delay */
  68 #define CR0_SSD_OFFSET                          10
  69 /*
  70  * The period between ss_n active and
  71  * sclk_out active is half sclk_out cycles
  72  */
  73 #define CR0_SSD_HALF                            0x0
  74 /*
  75  * The period between ss_n active and
  76  * sclk_out active is one sclk_out cycle
  77  */
  78 #define CR0_SSD_ONE                                     0x1
  79
  80 #define CR0_EM_OFFSET                           11
  81 #define CR0_EM_LITTLE                           0x0
  82 #define CR0_EM_BIG                                      0x1
  83
  84 #define CR0_FBM_OFFSET                          12
  85 #define CR0_FBM_MSB                                     0x0
  86 #define CR0_FBM_LSB                                     0x1
  87
  88 #define CR0_BHT_OFFSET                          13
  89 #define CR0_BHT_16BIT                           0x0
  90 #define CR0_BHT_8BIT                            0x1
  91
  92 #define CR0_RSD_OFFSET                          14
  93 #define CR0_RSD_MAX                             0x3
  94
  95 #define CR0_FRF_OFFSET                          16
  96 #define CR0_FRF_SPI                                     0x0
  97 #define CR0_FRF_SSP                                     0x1
  98 #define CR0_FRF_MICROWIRE                       0x2
  99
 100 #define CR0_XFM_OFFSET                          18
 101 #define CR0_XFM_MASK                            (0x03 << SPI_XFM_OFFSET)
 102 #define CR0_XFM_TR                                      0x0
 103 #define CR0_XFM_TO                                      0x1
 104 #define CR0_XFM_RO                                      0x2
 105
 106 #define CR0_OPM_OFFSET                          20
 107 #define CR0_OPM_MASTER                          0x0
 108 #define CR0_OPM_SLAVE                           0x1
 109
 110 #define CR0_SOI_OFFSET                          23
 111
 112 #define CR0_MTM_OFFSET                          0x21
 113
 114 /* Bit fields in SER, 2bit */
 115 #define SER_MASK                                        0x3
 116
 117 /* Bit fields in BAUDR */
 118 #define BAUDR_SCKDV_MIN                         2
 119 #define BAUDR_SCKDV_MAX                         65534
 120
 121 /* Bit fields in SR, 6bit */
 122 #define SR_MASK                                         0x3f
 123 #define SR_BUSY                                         (1 << 0)
 124 #define SR_TF_FULL                                      (1 << 1)
 125 #define SR_TF_EMPTY                                     (1 << 2)
 126 #define SR_RF_EMPTY                                     (1 << 3)
 127 #define SR_RF_FULL                                      (1 << 4)
 128 #define SR_SLAVE_TX_BUSY                                (1 << 5)
 129
 130 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
 131 #define INT_MASK                                        0x1f
 132 #define INT_TF_EMPTY                            (1 << 0)
 133 #define INT_TF_OVERFLOW                         (1 << 1)
 134 #define INT_RF_UNDERFLOW                        (1 << 2)
 135 #define INT_RF_OVERFLOW                         (1 << 3)
 136 #define INT_RF_FULL                             (1 << 4)
 137 #define INT_CS_INACTIVE                         (1 << 6)
 138
 139 /* Bit fields in ICR, 4bit */
 140 #define ICR_MASK                                        0x0f
 141 #define ICR_ALL                                         (1 << 0)
 142 #define ICR_RF_UNDERFLOW                        (1 << 1)
 143 #define ICR_RF_OVERFLOW                         (1 << 2)
 144 #define ICR_TF_OVERFLOW                         (1 << 3)
 145
 146 /* Bit fields in DMACR */
 147 #define RF_DMA_EN                                       (1 << 0)
 148 #define TF_DMA_EN                                       (1 << 1)
 149
 150 /* Driver state flags */
 151 #define RXDMA                                   (1 << 0)
 152 #define TXDMA                                   (1 << 1)
 153
 154 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
 155 #define MAX_SCLK_OUT                            50000000U
 156
 157 /*
 158  * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
 159  * the controller seems to hang when given 0x10000, so stick with this for now.
 160  */
 161 #define ROCKCHIP_SPI_MAX_TRANLEN                0xffff
 162
 163 /* 2 for native cs, 2 for cs-gpio */
 164 #define ROCKCHIP_SPI_MAX_CS_NUM                 4
 165 #define ROCKCHIP_SPI_VER2_TYPE1                 0x05EC0002
 166 #define ROCKCHIP_SPI_VER2_TYPE2                 0x00110002
 167
 168 #define ROCKCHIP_AUTOSUSPEND_TIMEOUT            2000
 169
 170 struct rockchip_spi {
 171         struct device *dev;
 172
 173         struct clk *spiclk;
 174         struct clk *apb_pclk;
 175
 176         void __iomem *regs;
 177         dma_addr_t dma_addr_rx;
 178         dma_addr_t dma_addr_tx;
 179
 180         const void *tx;
 181         void *rx;
 182         unsigned int tx_left;
 183         unsigned int rx_left;
 184
 185         atomic_t state;
 186
 187         /*depth of the FIFO buffer */
 188         u32 fifo_len;
 189         /* frequency of spiclk */
 190         u32 freq;
 191
 192         u8 n_bytes;
 193         u8 rsd;
 194
 195         bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
 196
 197         bool slave_abort;
 198         bool cs_inactive; /* spi slave tansmition stop when cs inactive */
 199         bool cs_high_supported; /* native CS supports active-high polarity */
 200
 201         struct spi_transfer *xfer; /* Store xfer temporarily */
 202 };
 203
 204 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
 205 {
 206         writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
 207 }
 208
 209 static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool slave_mode)
 210 {
 211         unsigned long timeout = jiffies + msecs_to_jiffies(5);
 212
 213         do {
 214                 if (slave_mode) {
 215                         if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_SLAVE_TX_BUSY) &&
 216                             !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)))
 217                                 return;
 218                 } else {
 219                         if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
 220                                 return;
 221                 }
 222         } while (!time_after(jiffies, timeout));
 223
 224         dev_warn(rs->dev, "spi controller is in busy state!\n");
 225 }
 226
 227 static u32 get_fifo_len(struct rockchip_spi *rs)
 228 {
 229         u32 ver;
 230
 231         ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
 232
 233         switch (ver) {
 234         case ROCKCHIP_SPI_VER2_TYPE1:
 235         case ROCKCHIP_SPI_VER2_TYPE2:
 236                 return 64;
 237         default:
 238                 return 32;
 239         }
 240 }
 241
 242 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
 243 {
 244         struct spi_controller *ctlr = spi->controller;
 245         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 246         bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable;
 247
 248         /* Return immediately for no-op */
 249         if (cs_asserted == rs->cs_asserted[spi->chip_select])
 250                 return;
 251
 252         if (cs_asserted) {
 253                 /* Keep things powered as long as CS is asserted */
 254                 pm_runtime_get_sync(rs->dev);
 255
 256                 if (spi->cs_gpiod)
 257                         ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
 258                 else
 259                         ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
 260         } else {
 261                 if (spi->cs_gpiod)
 262                         ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
 263                 else
 264                         ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
 265
 266                 /* Drop reference from when we first asserted CS */
 267                 pm_runtime_put(rs->dev);
 268         }
 269
 270         rs->cs_asserted[spi->chip_select] = cs_asserted;
 271 }
 272
 273 static void rockchip_spi_handle_err(struct spi_controller *ctlr,
 274                                     struct spi_message *msg)
 275 {
 276         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 277
 278         /* stop running spi transfer
 279          * this also flushes both rx and tx fifos
 280          */
 281         spi_enable_chip(rs, false);
 282
 283         /* make sure all interrupts are masked and status cleared */
 284         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 285         writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
 286
 287         if (atomic_read(&rs->state) & TXDMA)
 288                 dmaengine_terminate_async(ctlr->dma_tx);
 289
 290         if (atomic_read(&rs->state) & RXDMA)
 291                 dmaengine_terminate_async(ctlr->dma_rx);
 292 }
 293
 294 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
 295 {
 296         u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
 297         u32 words = min(rs->tx_left, tx_free);
 298
 299         rs->tx_left -= words;
 300         for (; words; words--) {
 301                 u32 txw;
 302
 303                 if (rs->n_bytes == 1)
 304                         txw = *(u8 *)rs->tx;
 305                 else
 306                         txw = *(u16 *)rs->tx;
 307
 308                 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
 309                 rs->tx += rs->n_bytes;
 310         }
 311 }
 312
 313 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
 314 {
 315         u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 316         u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0;
 317
 318         /* the hardware doesn't allow us to change fifo threshold
 319          * level while spi is enabled, so instead make sure to leave
 320          * enough words in the rx fifo to get the last interrupt
 321          * exactly when all words have been received
 322          */
 323         if (rx_left) {
 324                 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1;
 325
 326                 if (rx_left < ftl) {
 327                         rx_left = ftl;
 328                         words = rs->rx_left - rx_left;
 329                 }
 330         }
 331
 332         rs->rx_left = rx_left;
 333         for (; words; words--) {
 334                 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 335
 336                 if (!rs->rx)
 337                         continue;
 338
 339                 if (rs->n_bytes == 1)
 340                         *(u8 *)rs->rx = (u8)rxw;
 341                 else
 342                         *(u16 *)rs->rx = (u16)rxw;
 343                 rs->rx += rs->n_bytes;
 344         }
 345 }
 346
 347 static irqreturn_t rockchip_spi_isr(int irq, void *dev_id)
 348 {
 349         struct spi_controller *ctlr = dev_id;
 350         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 351
 352         /* When int_cs_inactive comes, spi slave abort */
 353         if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_IMR) & INT_CS_INACTIVE) {
 354                 ctlr->slave_abort(ctlr);
 355                 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 356                 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
 357
 358                 return IRQ_HANDLED;
 359         }
 360
 361         if (rs->tx_left)
 362                 rockchip_spi_pio_writer(rs);
 363
 364         rockchip_spi_pio_reader(rs);
 365         if (!rs->rx_left) {
 366                 spi_enable_chip(rs, false);
 367                 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 368                 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
 369                 spi_finalize_current_transfer(ctlr);
 370         }
 371
 372         return IRQ_HANDLED;
 373 }
 374
 375 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs,
 376                                     struct spi_controller *ctlr,
 377                                     struct spi_transfer *xfer)
 378 {
 379         rs->tx = xfer->tx_buf;
 380         rs->rx = xfer->rx_buf;
 381         rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
 382         rs->rx_left = xfer->len / rs->n_bytes;
 383
 384         writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
 385
 386         spi_enable_chip(rs, true);
 387
 388         if (rs->tx_left)
 389                 rockchip_spi_pio_writer(rs);
 390
 391         if (rs->cs_inactive)
 392                 writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
 393         else
 394                 writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
 395
 396         /* 1 means the transfer is in progress */
 397         return 1;
 398 }
 399
 400 static void rockchip_spi_dma_rxcb(void *data)
 401 {
 402         struct spi_controller *ctlr = data;
 403         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 404         int state = atomic_fetch_andnot(RXDMA, &rs->state);
 405
 406         if (state & TXDMA && !rs->slave_abort)
 407                 return;
 408
 409         if (rs->cs_inactive)
 410                 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 411
 412         spi_enable_chip(rs, false);
 413         spi_finalize_current_transfer(ctlr);
 414 }
 415
 416 static void rockchip_spi_dma_txcb(void *data)
 417 {
 418         struct spi_controller *ctlr = data;
 419         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 420         int state = atomic_fetch_andnot(TXDMA, &rs->state);
 421
 422         if (state & RXDMA && !rs->slave_abort)
 423                 return;
 424
 425         /* Wait until the FIFO data completely. */
 426         wait_for_tx_idle(rs, ctlr->slave);
 427
 428         spi_enable_chip(rs, false);
 429         spi_finalize_current_transfer(ctlr);
 430 }
 431
 432 static u32 rockchip_spi_calc_burst_size(u32 data_len)
 433 {
 434         u32 i;
 435
 436         /* burst size: 1, 2, 4, 8 */
 437         for (i = 1; i < 8; i <<= 1) {
 438                 if (data_len & i)
 439                         break;
 440         }
 441
 442         return i;
 443 }
 444
 445 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs,
 446                 struct spi_controller *ctlr, struct spi_transfer *xfer)
 447 {
 448         struct dma_async_tx_descriptor *rxdesc, *txdesc;
 449
 450         atomic_set(&rs->state, 0);
 451
 452         rs->tx = xfer->tx_buf;
 453         rs->rx = xfer->rx_buf;
 454
 455         rxdesc = NULL;
 456         if (xfer->rx_buf) {
 457                 struct dma_slave_config rxconf = {
 458                         .direction = DMA_DEV_TO_MEM,
 459                         .src_addr = rs->dma_addr_rx,
 460                         .src_addr_width = rs->n_bytes,
 461                         .src_maxburst = rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes),
 462                 };
 463
 464                 dmaengine_slave_config(ctlr->dma_rx, &rxconf);
 465
 466                 rxdesc = dmaengine_prep_slave_sg(
 467                                 ctlr->dma_rx,
 468                                 xfer->rx_sg.sgl, xfer->rx_sg.nents,
 469                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
 470                 if (!rxdesc)
 471                         return -EINVAL;
 472
 473                 rxdesc->callback = rockchip_spi_dma_rxcb;
 474                 rxdesc->callback_param = ctlr;
 475         }
 476
 477         txdesc = NULL;
 478         if (xfer->tx_buf) {
 479                 struct dma_slave_config txconf = {
 480                         .direction = DMA_MEM_TO_DEV,
 481                         .dst_addr = rs->dma_addr_tx,
 482                         .dst_addr_width = rs->n_bytes,
 483                         .dst_maxburst = rs->fifo_len / 4,
 484                 };
 485
 486                 dmaengine_slave_config(ctlr->dma_tx, &txconf);
 487
 488                 txdesc = dmaengine_prep_slave_sg(
 489                                 ctlr->dma_tx,
 490                                 xfer->tx_sg.sgl, xfer->tx_sg.nents,
 491                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 492                 if (!txdesc) {
 493                         if (rxdesc)
 494                                 dmaengine_terminate_sync(ctlr->dma_rx);
 495                         return -EINVAL;
 496                 }
 497
 498                 txdesc->callback = rockchip_spi_dma_txcb;
 499                 txdesc->callback_param = ctlr;
 500         }
 501
 502         /* rx must be started before tx due to spi instinct */
 503         if (rxdesc) {
 504                 atomic_or(RXDMA, &rs->state);
 505                 ctlr->dma_rx->cookie = dmaengine_submit(rxdesc);
 506                 dma_async_issue_pending(ctlr->dma_rx);
 507         }
 508
 509         if (rs->cs_inactive)
 510                 writel_relaxed(INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
 511
 512         spi_enable_chip(rs, true);
 513
 514         if (txdesc) {
 515                 atomic_or(TXDMA, &rs->state);
 516                 dmaengine_submit(txdesc);
 517                 dma_async_issue_pending(ctlr->dma_tx);
 518         }
 519
 520         /* 1 means the transfer is in progress */
 521         return 1;
 522 }
 523
 524 static int rockchip_spi_config(struct rockchip_spi *rs,
 525                 struct spi_device *spi, struct spi_transfer *xfer,
 526                 bool use_dma, bool slave_mode)
 527 {
 528         u32 cr0 = CR0_FRF_SPI  << CR0_FRF_OFFSET
 529                 | CR0_BHT_8BIT << CR0_BHT_OFFSET
 530                 | CR0_SSD_ONE  << CR0_SSD_OFFSET
 531                 | CR0_EM_BIG   << CR0_EM_OFFSET;
 532         u32 cr1;
 533         u32 dmacr = 0;
 534
 535         if (slave_mode)
 536                 cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET;
 537         rs->slave_abort = false;
 538
 539         cr0 |= rs->rsd << CR0_RSD_OFFSET;
 540         cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
 541         if (spi->mode & SPI_LSB_FIRST)
 542                 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
 543         if (spi->mode & SPI_CS_HIGH)
 544                 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
 545
 546         if (xfer->rx_buf && xfer->tx_buf)
 547                 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
 548         else if (xfer->rx_buf)
 549                 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;
 550         else if (use_dma)
 551                 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
 552
 553         switch (xfer->bits_per_word) {
 554         case 4:
 555                 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET;
 556                 cr1 = xfer->len - 1;
 557                 break;
 558         case 8:
 559                 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET;
 560                 cr1 = xfer->len - 1;
 561                 break;
 562         case 16:
 563                 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET;
 564                 cr1 = xfer->len / 2 - 1;
 565                 break;
 566         default:
 567                 /* we only whitelist 4, 8 and 16 bit words in
 568                  * ctlr->bits_per_word_mask, so this shouldn't
 569                  * happen
 570                  */
 571                 dev_err(rs->dev, "unknown bits per word: %d\n",
 572                         xfer->bits_per_word);
 573                 return -EINVAL;
 574         }
 575
 576         if (use_dma) {
 577                 if (xfer->tx_buf)
 578                         dmacr |= TF_DMA_EN;
 579                 if (xfer->rx_buf)
 580                         dmacr |= RF_DMA_EN;
 581         }
 582
 583         writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
 584         writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 585
 586         /* unfortunately setting the fifo threshold level to generate an
 587          * interrupt exactly when the fifo is full doesn't seem to work,
 588          * so we need the strict inequality here
 589          */
 590         if ((xfer->len / rs->n_bytes) < rs->fifo_len)
 591                 writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 592         else
 593                 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 594
 595         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
 596         writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1,
 597                        rs->regs + ROCKCHIP_SPI_DMARDLR);
 598         writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
 599
 600         /* the hardware only supports an even clock divisor, so
 601          * round divisor = spiclk / speed up to nearest even number
 602          * so that the resulting speed is <= the requested speed
 603          */
 604         writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz),
 605                         rs->regs + ROCKCHIP_SPI_BAUDR);
 606
 607         return 0;
 608 }
 609
 610 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
 611 {
 612         return ROCKCHIP_SPI_MAX_TRANLEN;
 613 }
 614
 615 static int rockchip_spi_slave_abort(struct spi_controller *ctlr)
 616 {
 617         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 618         u32 rx_fifo_left;
 619         struct dma_tx_state state;
 620         enum dma_status status;
 621
 622         /* Get current dma rx point */
 623         if (atomic_read(&rs->state) & RXDMA) {
 624                 dmaengine_pause(ctlr->dma_rx);
 625                 status = dmaengine_tx_status(ctlr->dma_rx, ctlr->dma_rx->cookie, &state);
 626                 if (status == DMA_ERROR) {
 627                         rs->rx = rs->xfer->rx_buf;
 628                         rs->xfer->len = 0;
 629                         rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 630                         for (; rx_fifo_left; rx_fifo_left--)
 631                                 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 632                         goto out;
 633                 } else {
 634                         rs->rx += rs->xfer->len - rs->n_bytes * state.residue;
 635                 }
 636         }
 637
 638         /* Get the valid data left in rx fifo and set rs->xfer->len real rx size */
 639         if (rs->rx) {
 640                 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 641                 for (; rx_fifo_left; rx_fifo_left--) {
 642                         u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 643
 644                         if (rs->n_bytes == 1)
 645                                 *(u8 *)rs->rx = (u8)rxw;
 646                         else
 647                                 *(u16 *)rs->rx = (u16)rxw;
 648                         rs->rx += rs->n_bytes;
 649                 }
 650                 rs->xfer->len = (unsigned int)(rs->rx - rs->xfer->rx_buf);
 651         }
 652
 653 out:
 654         if (atomic_read(&rs->state) & RXDMA)
 655                 dmaengine_terminate_sync(ctlr->dma_rx);
 656         if (atomic_read(&rs->state) & TXDMA)
 657                 dmaengine_terminate_sync(ctlr->dma_tx);
 658         atomic_set(&rs->state, 0);
 659         spi_enable_chip(rs, false);
 660         rs->slave_abort = true;
 661         spi_finalize_current_transfer(ctlr);
 662
 663         return 0;
 664 }
 665
 666 static int rockchip_spi_transfer_one(
 667                 struct spi_controller *ctlr,
 668                 struct spi_device *spi,
 669                 struct spi_transfer *xfer)
 670 {
 671         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 672         int ret;
 673         bool use_dma;
 674
 675         /* Zero length transfers won't trigger an interrupt on completion */
 676         if (!xfer->len) {
 677                 spi_finalize_current_transfer(ctlr);
 678                 return 1;
 679         }
 680
 681         WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
 682                 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
 683
 684         if (!xfer->tx_buf && !xfer->rx_buf) {
 685                 dev_err(rs->dev, "No buffer for transfer\n");
 686                 return -EINVAL;
 687         }
 688
 689         if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
 690                 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
 691                 return -EINVAL;
 692         }
 693
 694         rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
 695         rs->xfer = xfer;
 696         use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
 697
 698         ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave);
 699         if (ret)
 700                 return ret;
 701
 702         if (use_dma)
 703                 return rockchip_spi_prepare_dma(rs, ctlr, xfer);
 704
 705         return rockchip_spi_prepare_irq(rs, ctlr, xfer);
 706 }
 707
 708 static bool rockchip_spi_can_dma(struct spi_controller *ctlr,
 709                                  struct spi_device *spi,
 710                                  struct spi_transfer *xfer)
 711 {
 712         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 713         unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2;
 714
 715         /* if the numbor of spi words to transfer is less than the fifo
 716          * length we can just fill the fifo and wait for a single irq,
 717          * so don't bother setting up dma
 718          */
 719         return xfer->len / bytes_per_word >= rs->fifo_len;
 720 }
 721
 722 static int rockchip_spi_setup(struct spi_device *spi)
 723 {
 724         struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
 725         u32 cr0;
 726
 727         if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) {
 728                 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
 729                 return -EINVAL;
 730         }
 731
 732         pm_runtime_get_sync(rs->dev);
 733
 734         cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0);
 735
 736         cr0 &= ~(0x3 << CR0_SCPH_OFFSET);
 737         cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET);
 738         if (spi->mode & SPI_CS_HIGH && spi->chip_select <= 1)
 739                 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
 740         else if (spi->chip_select <= 1)
 741                 cr0 &= ~(BIT(spi->chip_select) << CR0_SOI_OFFSET);
 742
 743         writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
 744
 745         pm_runtime_put(rs->dev);
 746
 747         return 0;
 748 }
 749
 750 static int rockchip_spi_probe(struct platform_device *pdev)
 751 {
 752         int ret;
 753         struct rockchip_spi *rs;
 754         struct spi_controller *ctlr;
 755         struct resource *mem;
 756         struct device_node *np = pdev->dev.of_node;
 757         u32 rsd_nsecs, num_cs;
 758         bool slave_mode;
 759
 760         slave_mode = of_property_read_bool(np, "spi-slave");
 761
 762         if (slave_mode)
 763                 ctlr = spi_alloc_slave(&pdev->dev,
 764                                 sizeof(struct rockchip_spi));
 765         else
 766                 ctlr = spi_alloc_master(&pdev->dev,
 767                                 sizeof(struct rockchip_spi));
 768
 769         if (!ctlr)
 770                 return -ENOMEM;
 771
 772         platform_set_drvdata(pdev, ctlr);
 773
 774         rs = spi_controller_get_devdata(ctlr);
 775         ctlr->slave = slave_mode;
 776
 777         /* Get basic io resource and map it */
 778         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 779         rs->regs = devm_ioremap_resource(&pdev->dev, mem);
 780         if (IS_ERR(rs->regs)) {
 781                 ret =  PTR_ERR(rs->regs);
 782                 goto err_put_ctlr;
 783         }
 784
 785         rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
 786         if (IS_ERR(rs->apb_pclk)) {
 787                 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
 788                 ret = PTR_ERR(rs->apb_pclk);
 789                 goto err_put_ctlr;
 790         }
 791
 792         rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
 793         if (IS_ERR(rs->spiclk)) {
 794                 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
 795                 ret = PTR_ERR(rs->spiclk);
 796                 goto err_put_ctlr;
 797         }
 798
 799         ret = clk_prepare_enable(rs->apb_pclk);
 800         if (ret < 0) {
 801                 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
 802                 goto err_put_ctlr;
 803         }
 804
 805         ret = clk_prepare_enable(rs->spiclk);
 806         if (ret < 0) {
 807                 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
 808                 goto err_disable_apbclk;
 809         }
 810
 811         spi_enable_chip(rs, false);
 812
 813         ret = platform_get_irq(pdev, 0);
 814         if (ret < 0)
 815                 goto err_disable_spiclk;
 816
 817         ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
 818                         IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
 819         if (ret)
 820                 goto err_disable_spiclk;
 821
 822         rs->dev = &pdev->dev;
 823         rs->freq = clk_get_rate(rs->spiclk);
 824
 825         if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
 826                                   &rsd_nsecs)) {
 827                 /* rx sample delay is expressed in parent clock cycles (max 3) */
 828                 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8),
 829                                 1000000000 >> 8);
 830                 if (!rsd) {
 831                         dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n",
 832                                         rs->freq, rsd_nsecs);
 833                 } else if (rsd > CR0_RSD_MAX) {
 834                         rsd = CR0_RSD_MAX;
 835                         dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n",
 836                                         rs->freq, rsd_nsecs,
 837                                         CR0_RSD_MAX * 1000000000U / rs->freq);
 838                 }
 839                 rs->rsd = rsd;
 840         }
 841
 842         rs->fifo_len = get_fifo_len(rs);
 843         if (!rs->fifo_len) {
 844                 dev_err(&pdev->dev, "Failed to get fifo length\n");
 845                 ret = -EINVAL;
 846                 goto err_disable_spiclk;
 847         }
 848
 849         pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT);
 850         pm_runtime_use_autosuspend(&pdev->dev);
 851         pm_runtime_set_active(&pdev->dev);
 852         pm_runtime_enable(&pdev->dev);
 853
 854         ctlr->auto_runtime_pm = true;
 855         ctlr->bus_num = pdev->id;
 856         ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
 857         if (slave_mode) {
 858                 ctlr->mode_bits |= SPI_NO_CS;
 859                 ctlr->slave_abort = rockchip_spi_slave_abort;
 860         } else {
 861                 ctlr->flags = SPI_MASTER_GPIO_SS;
 862                 ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM;
 863                 /*
 864                  * rk spi0 has two native cs, spi1..5 one cs only
 865                  * if num-cs is missing in the dts, default to 1
 866                  */
 867                 if (of_property_read_u32(np, "num-cs", &num_cs))
 868                         num_cs = 1;
 869                 ctlr->num_chipselect = num_cs;
 870                 ctlr->use_gpio_descriptors = true;
 871         }
 872         ctlr->dev.of_node = pdev->dev.of_node;
 873         ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
 874         ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
 875         ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
 876
 877         ctlr->setup = rockchip_spi_setup;
 878         ctlr->set_cs = rockchip_spi_set_cs;
 879         ctlr->transfer_one = rockchip_spi_transfer_one;
 880         ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
 881         ctlr->handle_err = rockchip_spi_handle_err;
 882
 883         ctlr->dma_tx = dma_request_chan(rs->dev, "tx");
 884         if (IS_ERR(ctlr->dma_tx)) {
 885                 /* Check tx to see if we need defer probing driver */
 886                 if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) {
 887                         ret = -EPROBE_DEFER;
 888                         goto err_disable_pm_runtime;
 889                 }
 890                 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
 891                 ctlr->dma_tx = NULL;
 892         }
 893
 894         ctlr->dma_rx = dma_request_chan(rs->dev, "rx");
 895         if (IS_ERR(ctlr->dma_rx)) {
 896                 if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) {
 897                         ret = -EPROBE_DEFER;
 898                         goto err_free_dma_tx;
 899                 }
 900                 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
 901                 ctlr->dma_rx = NULL;
 902         }
 903
 904         if (ctlr->dma_tx && ctlr->dma_rx) {
 905                 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR;
 906                 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR;
 907                 ctlr->can_dma = rockchip_spi_can_dma;
 908         }
 909
 910         switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) {
 911         case ROCKCHIP_SPI_VER2_TYPE2:
 912                 rs->cs_high_supported = true;
 913                 ctlr->mode_bits |= SPI_CS_HIGH;
 914                 if (ctlr->can_dma && slave_mode)
 915                         rs->cs_inactive = true;
 916                 else
 917                         rs->cs_inactive = false;
 918                 break;
 919         default:
 920                 rs->cs_inactive = false;
 921                 break;
 922         }
 923
 924         ret = devm_spi_register_controller(&pdev->dev, ctlr);
 925         if (ret < 0) {
 926                 dev_err(&pdev->dev, "Failed to register controller\n");
 927                 goto err_free_dma_rx;
 928         }
 929
 930         return 0;
 931
 932 err_free_dma_rx:
 933         if (ctlr->dma_rx)
 934                 dma_release_channel(ctlr->dma_rx);
 935 err_free_dma_tx:
 936         if (ctlr->dma_tx)
 937                 dma_release_channel(ctlr->dma_tx);
 938 err_disable_pm_runtime:
 939         pm_runtime_disable(&pdev->dev);
 940 err_disable_spiclk:
 941         clk_disable_unprepare(rs->spiclk);
 942 err_disable_apbclk:
 943         clk_disable_unprepare(rs->apb_pclk);
 944 err_put_ctlr:
 945         spi_controller_put(ctlr);
 946
 947         return ret;
 948 }
 949
 950 static int rockchip_spi_remove(struct platform_device *pdev)
 951 {
 952         struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev));
 953         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 954
 955         pm_runtime_get_sync(&pdev->dev);
 956
 957         clk_disable_unprepare(rs->spiclk);
 958         clk_disable_unprepare(rs->apb_pclk);
 959
 960         pm_runtime_put_noidle(&pdev->dev);
 961         pm_runtime_disable(&pdev->dev);
 962         pm_runtime_set_suspended(&pdev->dev);
 963
 964         if (ctlr->dma_tx)
 965                 dma_release_channel(ctlr->dma_tx);
 966         if (ctlr->dma_rx)
 967                 dma_release_channel(ctlr->dma_rx);
 968
 969         spi_controller_put(ctlr);
 970
 971         return 0;
 972 }
 973
 974 #ifdef CONFIG_PM_SLEEP
 975 static int rockchip_spi_suspend(struct device *dev)
 976 {
 977         int ret;
 978         struct spi_controller *ctlr = dev_get_drvdata(dev);
 979         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 980
 981         ret = spi_controller_suspend(ctlr);
 982         if (ret < 0)
 983                 return ret;
 984
 985         clk_disable_unprepare(rs->spiclk);
 986         clk_disable_unprepare(rs->apb_pclk);
 987
 988         pinctrl_pm_select_sleep_state(dev);
 989
 990         return 0;
 991 }
 992
 993 static int rockchip_spi_resume(struct device *dev)
 994 {
 995         int ret;
 996         struct spi_controller *ctlr = dev_get_drvdata(dev);
 997         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 998
 999         pinctrl_pm_select_default_state(dev);
1000
1001         ret = clk_prepare_enable(rs->apb_pclk);
1002         if (ret < 0)
1003                 return ret;
1004
1005         ret = clk_prepare_enable(rs->spiclk);
1006         if (ret < 0)
1007                 clk_disable_unprepare(rs->apb_pclk);
1008
1009         ret = spi_controller_resume(ctlr);
1010         if (ret < 0) {
1011                 clk_disable_unprepare(rs->spiclk);
1012                 clk_disable_unprepare(rs->apb_pclk);
1013         }
1014
1015         return 0;
1016 }
1017 #endif /* CONFIG_PM_SLEEP */
1018
1019 #ifdef CONFIG_PM
1020 static int rockchip_spi_runtime_suspend(struct device *dev)
1021 {
1022         struct spi_controller *ctlr = dev_get_drvdata(dev);
1023         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1024
1025         clk_disable_unprepare(rs->spiclk);
1026         clk_disable_unprepare(rs->apb_pclk);
1027
1028         return 0;
1029 }
1030
1031 static int rockchip_spi_runtime_resume(struct device *dev)
1032 {
1033         int ret;
1034         struct spi_controller *ctlr = dev_get_drvdata(dev);
1035         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1036
1037         ret = clk_prepare_enable(rs->apb_pclk);
1038         if (ret < 0)
1039                 return ret;
1040
1041         ret = clk_prepare_enable(rs->spiclk);
1042         if (ret < 0)
1043                 clk_disable_unprepare(rs->apb_pclk);
1044
1045         return 0;
1046 }
1047 #endif /* CONFIG_PM */
1048
1049 static const struct dev_pm_ops rockchip_spi_pm = {
1050         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
1051         SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
1052                            rockchip_spi_runtime_resume, NULL)
1053 };
1054
1055 static const struct of_device_id rockchip_spi_dt_match[] = {
1056         { .compatible = "rockchip,px30-spi", },
1057         { .compatible = "rockchip,rk3036-spi", },
1058         { .compatible = "rockchip,rk3066-spi", },
1059         { .compatible = "rockchip,rk3188-spi", },
1060         { .compatible = "rockchip,rk3228-spi", },
1061         { .compatible = "rockchip,rk3288-spi", },
1062         { .compatible = "rockchip,rk3308-spi", },
1063         { .compatible = "rockchip,rk3328-spi", },
1064         { .compatible = "rockchip,rk3368-spi", },
1065         { .compatible = "rockchip,rk3399-spi", },
1066         { .compatible = "rockchip,rv1108-spi", },
1067         { .compatible = "rockchip,rv1126-spi", },
1068         { },
1069 };
1070 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
1071
1072 static struct platform_driver rockchip_spi_driver = {
1073         .driver = {
1074                 .name   = DRIVER_NAME,
1075                 .pm = &rockchip_spi_pm,
1076                 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
1077         },
1078         .probe = rockchip_spi_probe,
1079         .remove = rockchip_spi_remove,
1080 };
1081
1082 module_platform_driver(rockchip_spi_driver);
1083
1084 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
1085 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
1086 MODULE_LICENSE("GPL v2");