drivers/spi/spi-rockchip.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  * Author: Addy Ke <addy.ke@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/dmaengine.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/pinctrl/consumer.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/scatterlist.h>
  25
  26 #define DRIVER_NAME "rockchip-spi"
  27
  28 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
  29                 writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
  30 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \
  31                 writel_relaxed(readl_relaxed(reg) | (bits), reg)
  32
  33 /* SPI register offsets */
  34 #define ROCKCHIP_SPI_CTRLR0                     0x0000
  35 #define ROCKCHIP_SPI_CTRLR1                     0x0004
  36 #define ROCKCHIP_SPI_SSIENR                     0x0008
  37 #define ROCKCHIP_SPI_SER                        0x000c
  38 #define ROCKCHIP_SPI_BAUDR                      0x0010
  39 #define ROCKCHIP_SPI_TXFTLR                     0x0014
  40 #define ROCKCHIP_SPI_RXFTLR                     0x0018
  41 #define ROCKCHIP_SPI_TXFLR                      0x001c
  42 #define ROCKCHIP_SPI_RXFLR                      0x0020
  43 #define ROCKCHIP_SPI_SR                         0x0024
  44 #define ROCKCHIP_SPI_IPR                        0x0028
  45 #define ROCKCHIP_SPI_IMR                        0x002c
  46 #define ROCKCHIP_SPI_ISR                        0x0030
  47 #define ROCKCHIP_SPI_RISR                       0x0034
  48 #define ROCKCHIP_SPI_ICR                        0x0038
  49 #define ROCKCHIP_SPI_DMACR                      0x003c
  50 #define ROCKCHIP_SPI_DMATDLR            0x0040
  51 #define ROCKCHIP_SPI_DMARDLR            0x0044
  52 #define ROCKCHIP_SPI_TXDR                       0x0400
  53 #define ROCKCHIP_SPI_RXDR                       0x0800
  54
  55 /* Bit fields in CTRLR0 */
  56 #define CR0_DFS_OFFSET                          0
  57
  58 #define CR0_CFS_OFFSET                          2
  59
  60 #define CR0_SCPH_OFFSET                         6
  61
  62 #define CR0_SCPOL_OFFSET                        7
  63
  64 #define CR0_CSM_OFFSET                          8
  65 #define CR0_CSM_KEEP                            0x0
  66 /* ss_n be high for half sclk_out cycles */
  67 #define CR0_CSM_HALF                            0X1
  68 /* ss_n be high for one sclk_out cycle */
  69 #define CR0_CSM_ONE                                     0x2
  70
  71 /* ss_n to sclk_out delay */
  72 #define CR0_SSD_OFFSET                          10
  73 /*
  74  * The period between ss_n active and
  75  * sclk_out active is half sclk_out cycles
  76  */
  77 #define CR0_SSD_HALF                            0x0
  78 /*
  79  * The period between ss_n active and
  80  * sclk_out active is one sclk_out cycle
  81  */
  82 #define CR0_SSD_ONE                                     0x1
  83
  84 #define CR0_EM_OFFSET                           11
  85 #define CR0_EM_LITTLE                           0x0
  86 #define CR0_EM_BIG                                      0x1
  87
  88 #define CR0_FBM_OFFSET                          12
  89 #define CR0_FBM_MSB                                     0x0
  90 #define CR0_FBM_LSB                                     0x1
  91
  92 #define CR0_BHT_OFFSET                          13
  93 #define CR0_BHT_16BIT                           0x0
  94 #define CR0_BHT_8BIT                            0x1
  95
  96 #define CR0_RSD_OFFSET                          14
  97
  98 #define CR0_FRF_OFFSET                          16
  99 #define CR0_FRF_SPI                                     0x0
 100 #define CR0_FRF_SSP                                     0x1
 101 #define CR0_FRF_MICROWIRE                       0x2
 102
 103 #define CR0_XFM_OFFSET                          18
 104 #define CR0_XFM_MASK                            (0x03 << SPI_XFM_OFFSET)
 105 #define CR0_XFM_TR                                      0x0
 106 #define CR0_XFM_TO                                      0x1
 107 #define CR0_XFM_RO                                      0x2
 108
 109 #define CR0_OPM_OFFSET                          20
 110 #define CR0_OPM_MASTER                          0x0
 111 #define CR0_OPM_SLAVE                           0x1
 112
 113 #define CR0_MTM_OFFSET                          0x21
 114
 115 /* Bit fields in SER, 2bit */
 116 #define SER_MASK                                        0x3
 117
 118 /* Bit fields in SR, 5bit */
 119 #define SR_MASK                                         0x1f
 120 #define SR_BUSY                                         (1 << 0)
 121 #define SR_TF_FULL                                      (1 << 1)
 122 #define SR_TF_EMPTY                                     (1 << 2)
 123 #define SR_RF_EMPTY                                     (1 << 3)
 124 #define SR_RF_FULL                                      (1 << 4)
 125
 126 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
 127 #define INT_MASK                                        0x1f
 128 #define INT_TF_EMPTY                            (1 << 0)
 129 #define INT_TF_OVERFLOW                         (1 << 1)
 130 #define INT_RF_UNDERFLOW                        (1 << 2)
 131 #define INT_RF_OVERFLOW                         (1 << 3)
 132 #define INT_RF_FULL                                     (1 << 4)
 133
 134 /* Bit fields in ICR, 4bit */
 135 #define ICR_MASK                                        0x0f
 136 #define ICR_ALL                                         (1 << 0)
 137 #define ICR_RF_UNDERFLOW                        (1 << 1)
 138 #define ICR_RF_OVERFLOW                         (1 << 2)
 139 #define ICR_TF_OVERFLOW                         (1 << 3)
 140
 141 /* Bit fields in DMACR */
 142 #define RF_DMA_EN                                       (1 << 0)
 143 #define TF_DMA_EN                                       (1 << 1)
 144
 145 /* Driver state flags */
 146 #define RXDMA                                   (1 << 0)
 147 #define TXDMA                                   (1 << 1)
 148
 149 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
 150 #define MAX_SCLK_OUT            50000000
 151
 152 /*
 153  * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
 154  * the controller seems to hang when given 0x10000, so stick with this for now.
 155  */
 156 #define ROCKCHIP_SPI_MAX_TRANLEN                0xffff
 157
 158 #define ROCKCHIP_SPI_MAX_CS_NUM                 2
 159
 160 struct rockchip_spi_dma_data {
 161         struct dma_chan *ch;
 162         dma_addr_t addr;
 163 };
 164
 165 struct rockchip_spi {
 166         struct device *dev;
 167         struct spi_master *master;
 168
 169         struct clk *spiclk;
 170         struct clk *apb_pclk;
 171
 172         void __iomem *regs;
 173
 174         atomic_t state;
 175
 176         /*depth of the FIFO buffer */
 177         u32 fifo_len;
 178         /* max bus freq supported */
 179         u32 max_freq;
 180
 181         u8 n_bytes;
 182         u32 rsd_nsecs;
 183         u32 speed;
 184
 185         const void *tx;
 186         const void *tx_end;
 187         void *rx;
 188         void *rx_end;
 189
 190         bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
 191
 192         bool use_dma;
 193         struct rockchip_spi_dma_data dma_rx;
 194         struct rockchip_spi_dma_data dma_tx;
 195 };
 196
 197 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
 198 {
 199         writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
 200 }
 201
 202 static inline void spi_set_clk(struct rockchip_spi *rs, u16 div)
 203 {
 204         writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR);
 205 }
 206
 207 static inline void wait_for_idle(struct rockchip_spi *rs)
 208 {
 209         unsigned long timeout = jiffies + msecs_to_jiffies(5);
 210
 211         do {
 212                 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
 213                         return;
 214         } while (!time_after(jiffies, timeout));
 215
 216         dev_warn(rs->dev, "spi controller is in busy state!\n");
 217 }
 218
 219 static u32 get_fifo_len(struct rockchip_spi *rs)
 220 {
 221         u32 fifo;
 222
 223         for (fifo = 2; fifo < 32; fifo++) {
 224                 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
 225                 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
 226                         break;
 227         }
 228
 229         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
 230
 231         return (fifo == 31) ? 0 : fifo;
 232 }
 233
 234 static inline u32 tx_max(struct rockchip_spi *rs)
 235 {
 236         u32 tx_left, tx_room;
 237
 238         tx_left = (rs->tx_end - rs->tx) / rs->n_bytes;
 239         tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
 240
 241         return min(tx_left, tx_room);
 242 }
 243
 244 static inline u32 rx_max(struct rockchip_spi *rs)
 245 {
 246         u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes;
 247         u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 248
 249         return min(rx_left, rx_room);
 250 }
 251
 252 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
 253 {
 254         struct spi_master *master = spi->master;
 255         struct rockchip_spi *rs = spi_master_get_devdata(master);
 256         bool cs_asserted = !enable;
 257
 258         /* Return immediately for no-op */
 259         if (cs_asserted == rs->cs_asserted[spi->chip_select])
 260                 return;
 261
 262         if (cs_asserted) {
 263                 /* Keep things powered as long as CS is asserted */
 264                 pm_runtime_get_sync(rs->dev);
 265
 266                 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER,
 267                                       BIT(spi->chip_select));
 268         } else {
 269                 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER,
 270                                       BIT(spi->chip_select));
 271
 272                 /* Drop reference from when we first asserted CS */
 273                 pm_runtime_put(rs->dev);
 274         }
 275
 276         rs->cs_asserted[spi->chip_select] = cs_asserted;
 277 }
 278
 279 static void rockchip_spi_handle_err(struct spi_master *master,
 280                                     struct spi_message *msg)
 281 {
 282         struct rockchip_spi *rs = spi_master_get_devdata(master);
 283
 284         /* stop running spi transfer
 285          * this also flushes both rx and tx fifos
 286          */
 287         spi_enable_chip(rs, false);
 288
 289         if (atomic_read(&rs->state) & TXDMA)
 290                 dmaengine_terminate_async(rs->dma_tx.ch);
 291
 292         if (atomic_read(&rs->state) & RXDMA)
 293                 dmaengine_terminate_async(rs->dma_rx.ch);
 294 }
 295
 296 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
 297 {
 298         u32 max = tx_max(rs);
 299         u32 txw = 0;
 300
 301         while (max--) {
 302                 if (rs->n_bytes == 1)
 303                         txw = *(u8 *)(rs->tx);
 304                 else
 305                         txw = *(u16 *)(rs->tx);
 306
 307                 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
 308                 rs->tx += rs->n_bytes;
 309         }
 310 }
 311
 312 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
 313 {
 314         u32 max = rx_max(rs);
 315         u32 rxw;
 316
 317         while (max--) {
 318                 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 319                 if (rs->n_bytes == 1)
 320                         *(u8 *)(rs->rx) = (u8)rxw;
 321                 else
 322                         *(u16 *)(rs->rx) = (u16)rxw;
 323                 rs->rx += rs->n_bytes;
 324         }
 325 }
 326
 327 static int rockchip_spi_pio_transfer(struct rockchip_spi *rs)
 328 {
 329         int remain = 0;
 330
 331         spi_enable_chip(rs, true);
 332
 333         do {
 334                 if (rs->tx) {
 335                         remain = rs->tx_end - rs->tx;
 336                         rockchip_spi_pio_writer(rs);
 337                 }
 338
 339                 if (rs->rx) {
 340                         remain = rs->rx_end - rs->rx;
 341                         rockchip_spi_pio_reader(rs);
 342                 }
 343
 344                 cpu_relax();
 345         } while (remain);
 346
 347         /* If tx, wait until the FIFO data completely. */
 348         if (rs->tx)
 349                 wait_for_idle(rs);
 350
 351         spi_enable_chip(rs, false);
 352
 353         return 0;
 354 }
 355
 356 static void rockchip_spi_dma_rxcb(void *data)
 357 {
 358         struct rockchip_spi *rs = data;
 359         int state = atomic_fetch_andnot(RXDMA, &rs->state);
 360
 361         if (state & TXDMA)
 362                 return;
 363
 364         spi_enable_chip(rs, false);
 365         spi_finalize_current_transfer(rs->master);
 366 }
 367
 368 static void rockchip_spi_dma_txcb(void *data)
 369 {
 370         struct rockchip_spi *rs = data;
 371         int state = atomic_fetch_andnot(TXDMA, &rs->state);
 372
 373         if (state & RXDMA)
 374                 return;
 375
 376         /* Wait until the FIFO data completely. */
 377         wait_for_idle(rs);
 378
 379         spi_enable_chip(rs, false);
 380         spi_finalize_current_transfer(rs->master);
 381 }
 382
 383 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs,
 384                 struct spi_transfer *xfer)
 385 {
 386         struct dma_async_tx_descriptor *rxdesc, *txdesc;
 387
 388         atomic_set(&rs->state, 0);
 389
 390         rxdesc = NULL;
 391         if (xfer->rx_buf) {
 392                 struct dma_slave_config rxconf = {
 393                         .direction = DMA_DEV_TO_MEM,
 394                         .src_addr = rs->dma_rx.addr,
 395                         .src_addr_width = rs->n_bytes,
 396                         .src_maxburst = 1,
 397                 };
 398
 399                 dmaengine_slave_config(rs->dma_rx.ch, &rxconf);
 400
 401                 rxdesc = dmaengine_prep_slave_sg(
 402                                 rs->dma_rx.ch,
 403                                 xfer->rx_sg.sgl, xfer->rx_sg.nents,
 404                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
 405                 if (!rxdesc)
 406                         return -EINVAL;
 407
 408                 rxdesc->callback = rockchip_spi_dma_rxcb;
 409                 rxdesc->callback_param = rs;
 410         }
 411
 412         txdesc = NULL;
 413         if (xfer->tx_buf) {
 414                 struct dma_slave_config txconf = {
 415                         .direction = DMA_MEM_TO_DEV,
 416                         .dst_addr = rs->dma_tx.addr,
 417                         .dst_addr_width = rs->n_bytes,
 418                         .dst_maxburst = rs->fifo_len / 2,
 419                 };
 420
 421                 dmaengine_slave_config(rs->dma_tx.ch, &txconf);
 422
 423                 txdesc = dmaengine_prep_slave_sg(
 424                                 rs->dma_tx.ch,
 425                                 xfer->tx_sg.sgl, xfer->tx_sg.nents,
 426                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 427                 if (!txdesc) {
 428                         if (rxdesc)
 429                                 dmaengine_terminate_sync(rs->dma_rx.ch);
 430                         return -EINVAL;
 431                 }
 432
 433                 txdesc->callback = rockchip_spi_dma_txcb;
 434                 txdesc->callback_param = rs;
 435         }
 436
 437         /* rx must be started before tx due to spi instinct */
 438         if (rxdesc) {
 439                 atomic_or(RXDMA, &rs->state);
 440                 dmaengine_submit(rxdesc);
 441                 dma_async_issue_pending(rs->dma_rx.ch);
 442         }
 443
 444         spi_enable_chip(rs, true);
 445
 446         if (txdesc) {
 447                 atomic_or(TXDMA, &rs->state);
 448                 dmaengine_submit(txdesc);
 449                 dma_async_issue_pending(rs->dma_tx.ch);
 450         }
 451
 452         /* 1 means the transfer is in progress */
 453         return 1;
 454 }
 455
 456 static void rockchip_spi_config(struct rockchip_spi *rs,
 457                 struct spi_device *spi, struct spi_transfer *xfer)
 458 {
 459         u32 div = 0;
 460         u32 dmacr = 0;
 461         int rsd = 0;
 462
 463         u32 cr0 = CR0_FRF_SPI  << CR0_FRF_OFFSET
 464                 | CR0_BHT_8BIT << CR0_BHT_OFFSET
 465                 | CR0_SSD_ONE  << CR0_SSD_OFFSET
 466                 | CR0_EM_BIG   << CR0_EM_OFFSET;
 467
 468         cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
 469         cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
 470
 471         if (xfer->rx_buf && xfer->tx_buf)
 472                 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
 473         else if (xfer->rx_buf)
 474                 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;
 475         else
 476                 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
 477
 478         if (rs->use_dma) {
 479                 if (xfer->tx_buf)
 480                         dmacr |= TF_DMA_EN;
 481                 if (xfer->rx_buf)
 482                         dmacr |= RF_DMA_EN;
 483         }
 484
 485         if (WARN_ON(rs->speed > MAX_SCLK_OUT))
 486                 rs->speed = MAX_SCLK_OUT;
 487
 488         /* the minimum divisor is 2 */
 489         if (rs->max_freq < 2 * rs->speed) {
 490                 clk_set_rate(rs->spiclk, 2 * rs->speed);
 491                 rs->max_freq = clk_get_rate(rs->spiclk);
 492         }
 493
 494         /* div doesn't support odd number */
 495         div = DIV_ROUND_UP(rs->max_freq, rs->speed);
 496         div = (div + 1) & 0xfffe;
 497
 498         /* Rx sample delay is expressed in parent clock cycles (max 3) */
 499         rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8),
 500                                 1000000000 >> 8);
 501         if (!rsd && rs->rsd_nsecs) {
 502                 pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n",
 503                              rs->max_freq, rs->rsd_nsecs);
 504         } else if (rsd > 3) {
 505                 rsd = 3;
 506                 pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n",
 507                              rs->max_freq, rs->rsd_nsecs,
 508                              rsd * 1000000000U / rs->max_freq);
 509         }
 510         cr0 |= rsd << CR0_RSD_OFFSET;
 511
 512         writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
 513
 514         if (rs->n_bytes == 1)
 515                 writel_relaxed(xfer->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 516         else if (rs->n_bytes == 2)
 517                 writel_relaxed((xfer->len / 2) - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 518         else
 519                 writel_relaxed((xfer->len * 2) - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 520
 521         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
 522         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 523
 524         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
 525         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
 526         writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
 527
 528         spi_set_clk(rs, div);
 529
 530         dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
 531 }
 532
 533 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
 534 {
 535         return ROCKCHIP_SPI_MAX_TRANLEN;
 536 }
 537
 538 static int rockchip_spi_transfer_one(
 539                 struct spi_master *master,
 540                 struct spi_device *spi,
 541                 struct spi_transfer *xfer)
 542 {
 543         struct rockchip_spi *rs = spi_master_get_devdata(master);
 544
 545         WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
 546                 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
 547
 548         if (!xfer->tx_buf && !xfer->rx_buf) {
 549                 dev_err(rs->dev, "No buffer for transfer\n");
 550                 return -EINVAL;
 551         }
 552
 553         if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
 554                 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
 555                 return -EINVAL;
 556         }
 557
 558         rs->speed = xfer->speed_hz;
 559         rs->n_bytes = xfer->bits_per_word >> 3;
 560
 561         rs->tx = xfer->tx_buf;
 562         rs->tx_end = rs->tx + xfer->len;
 563         rs->rx = xfer->rx_buf;
 564         rs->rx_end = rs->rx + xfer->len;
 565
 566         /* we need prepare dma before spi was enabled */
 567         if (master->can_dma && master->can_dma(master, spi, xfer))
 568                 rs->use_dma = true;
 569         else
 570                 rs->use_dma = false;
 571
 572         rockchip_spi_config(rs, spi, xfer);
 573
 574         if (rs->use_dma)
 575                 return rockchip_spi_prepare_dma(rs, xfer);
 576
 577         return rockchip_spi_pio_transfer(rs);
 578 }
 579
 580 static bool rockchip_spi_can_dma(struct spi_master *master,
 581                                  struct spi_device *spi,
 582                                  struct spi_transfer *xfer)
 583 {
 584         struct rockchip_spi *rs = spi_master_get_devdata(master);
 585
 586         return (xfer->len > rs->fifo_len);
 587 }
 588
 589 static int rockchip_spi_probe(struct platform_device *pdev)
 590 {
 591         int ret;
 592         struct rockchip_spi *rs;
 593         struct spi_master *master;
 594         struct resource *mem;
 595         u32 rsd_nsecs;
 596
 597         master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
 598         if (!master)
 599                 return -ENOMEM;
 600
 601         platform_set_drvdata(pdev, master);
 602
 603         rs = spi_master_get_devdata(master);
 604
 605         /* Get basic io resource and map it */
 606         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 607         rs->regs = devm_ioremap_resource(&pdev->dev, mem);
 608         if (IS_ERR(rs->regs)) {
 609                 ret =  PTR_ERR(rs->regs);
 610                 goto err_put_master;
 611         }
 612
 613         rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
 614         if (IS_ERR(rs->apb_pclk)) {
 615                 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
 616                 ret = PTR_ERR(rs->apb_pclk);
 617                 goto err_put_master;
 618         }
 619
 620         rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
 621         if (IS_ERR(rs->spiclk)) {
 622                 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
 623                 ret = PTR_ERR(rs->spiclk);
 624                 goto err_put_master;
 625         }
 626
 627         ret = clk_prepare_enable(rs->apb_pclk);
 628         if (ret < 0) {
 629                 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
 630                 goto err_put_master;
 631         }
 632
 633         ret = clk_prepare_enable(rs->spiclk);
 634         if (ret < 0) {
 635                 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
 636                 goto err_disable_apbclk;
 637         }
 638
 639         spi_enable_chip(rs, false);
 640
 641         rs->master = master;
 642         rs->dev = &pdev->dev;
 643         rs->max_freq = clk_get_rate(rs->spiclk);
 644
 645         if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
 646                                   &rsd_nsecs))
 647                 rs->rsd_nsecs = rsd_nsecs;
 648
 649         rs->fifo_len = get_fifo_len(rs);
 650         if (!rs->fifo_len) {
 651                 dev_err(&pdev->dev, "Failed to get fifo length\n");
 652                 ret = -EINVAL;
 653                 goto err_disable_spiclk;
 654         }
 655
 656         pm_runtime_set_active(&pdev->dev);
 657         pm_runtime_enable(&pdev->dev);
 658
 659         master->auto_runtime_pm = true;
 660         master->bus_num = pdev->id;
 661         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
 662         master->num_chipselect = ROCKCHIP_SPI_MAX_CS_NUM;
 663         master->dev.of_node = pdev->dev.of_node;
 664         master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
 665
 666         master->set_cs = rockchip_spi_set_cs;
 667         master->transfer_one = rockchip_spi_transfer_one;
 668         master->max_transfer_size = rockchip_spi_max_transfer_size;
 669         master->handle_err = rockchip_spi_handle_err;
 670         master->flags = SPI_MASTER_GPIO_SS;
 671
 672         rs->dma_tx.ch = dma_request_chan(rs->dev, "tx");
 673         if (IS_ERR(rs->dma_tx.ch)) {
 674                 /* Check tx to see if we need defer probing driver */
 675                 if (PTR_ERR(rs->dma_tx.ch) == -EPROBE_DEFER) {
 676                         ret = -EPROBE_DEFER;
 677                         goto err_disable_pm_runtime;
 678                 }
 679                 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
 680                 rs->dma_tx.ch = NULL;
 681         }
 682
 683         rs->dma_rx.ch = dma_request_chan(rs->dev, "rx");
 684         if (IS_ERR(rs->dma_rx.ch)) {
 685                 if (PTR_ERR(rs->dma_rx.ch) == -EPROBE_DEFER) {
 686                         ret = -EPROBE_DEFER;
 687                         goto err_free_dma_tx;
 688                 }
 689                 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
 690                 rs->dma_rx.ch = NULL;
 691         }
 692
 693         if (rs->dma_tx.ch && rs->dma_rx.ch) {
 694                 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR);
 695                 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR);
 696
 697                 master->can_dma = rockchip_spi_can_dma;
 698                 master->dma_tx = rs->dma_tx.ch;
 699                 master->dma_rx = rs->dma_rx.ch;
 700         }
 701
 702         ret = devm_spi_register_master(&pdev->dev, master);
 703         if (ret < 0) {
 704                 dev_err(&pdev->dev, "Failed to register master\n");
 705                 goto err_free_dma_rx;
 706         }
 707
 708         return 0;
 709
 710 err_free_dma_rx:
 711         if (rs->dma_rx.ch)
 712                 dma_release_channel(rs->dma_rx.ch);
 713 err_free_dma_tx:
 714         if (rs->dma_tx.ch)
 715                 dma_release_channel(rs->dma_tx.ch);
 716 err_disable_pm_runtime:
 717         pm_runtime_disable(&pdev->dev);
 718 err_disable_spiclk:
 719         clk_disable_unprepare(rs->spiclk);
 720 err_disable_apbclk:
 721         clk_disable_unprepare(rs->apb_pclk);
 722 err_put_master:
 723         spi_master_put(master);
 724
 725         return ret;
 726 }
 727
 728 static int rockchip_spi_remove(struct platform_device *pdev)
 729 {
 730         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
 731         struct rockchip_spi *rs = spi_master_get_devdata(master);
 732
 733         pm_runtime_get_sync(&pdev->dev);
 734
 735         clk_disable_unprepare(rs->spiclk);
 736         clk_disable_unprepare(rs->apb_pclk);
 737
 738         pm_runtime_put_noidle(&pdev->dev);
 739         pm_runtime_disable(&pdev->dev);
 740         pm_runtime_set_suspended(&pdev->dev);
 741
 742         if (rs->dma_tx.ch)
 743                 dma_release_channel(rs->dma_tx.ch);
 744         if (rs->dma_rx.ch)
 745                 dma_release_channel(rs->dma_rx.ch);
 746
 747         spi_master_put(master);
 748
 749         return 0;
 750 }
 751
 752 #ifdef CONFIG_PM_SLEEP
 753 static int rockchip_spi_suspend(struct device *dev)
 754 {
 755         int ret;
 756         struct spi_master *master = dev_get_drvdata(dev);
 757         struct rockchip_spi *rs = spi_master_get_devdata(master);
 758
 759         ret = spi_master_suspend(rs->master);
 760         if (ret < 0)
 761                 return ret;
 762
 763         ret = pm_runtime_force_suspend(dev);
 764         if (ret < 0)
 765                 return ret;
 766
 767         pinctrl_pm_select_sleep_state(dev);
 768
 769         return 0;
 770 }
 771
 772 static int rockchip_spi_resume(struct device *dev)
 773 {
 774         int ret;
 775         struct spi_master *master = dev_get_drvdata(dev);
 776         struct rockchip_spi *rs = spi_master_get_devdata(master);
 777
 778         pinctrl_pm_select_default_state(dev);
 779
 780         ret = pm_runtime_force_resume(dev);
 781         if (ret < 0)
 782                 return ret;
 783
 784         ret = spi_master_resume(rs->master);
 785         if (ret < 0) {
 786                 clk_disable_unprepare(rs->spiclk);
 787                 clk_disable_unprepare(rs->apb_pclk);
 788         }
 789
 790         return 0;
 791 }
 792 #endif /* CONFIG_PM_SLEEP */
 793
 794 #ifdef CONFIG_PM
 795 static int rockchip_spi_runtime_suspend(struct device *dev)
 796 {
 797         struct spi_master *master = dev_get_drvdata(dev);
 798         struct rockchip_spi *rs = spi_master_get_devdata(master);
 799
 800         clk_disable_unprepare(rs->spiclk);
 801         clk_disable_unprepare(rs->apb_pclk);
 802
 803         return 0;
 804 }
 805
 806 static int rockchip_spi_runtime_resume(struct device *dev)
 807 {
 808         int ret;
 809         struct spi_master *master = dev_get_drvdata(dev);
 810         struct rockchip_spi *rs = spi_master_get_devdata(master);
 811
 812         ret = clk_prepare_enable(rs->apb_pclk);
 813         if (ret < 0)
 814                 return ret;
 815
 816         ret = clk_prepare_enable(rs->spiclk);
 817         if (ret < 0)
 818                 clk_disable_unprepare(rs->apb_pclk);
 819
 820         return 0;
 821 }
 822 #endif /* CONFIG_PM */
 823
 824 static const struct dev_pm_ops rockchip_spi_pm = {
 825         SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
 826         SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
 827                            rockchip_spi_runtime_resume, NULL)
 828 };
 829
 830 static const struct of_device_id rockchip_spi_dt_match[] = {
 831         { .compatible = "rockchip,rv1108-spi", },
 832         { .compatible = "rockchip,rk3036-spi", },
 833         { .compatible = "rockchip,rk3066-spi", },
 834         { .compatible = "rockchip,rk3188-spi", },
 835         { .compatible = "rockchip,rk3228-spi", },
 836         { .compatible = "rockchip,rk3288-spi", },
 837         { .compatible = "rockchip,rk3368-spi", },
 838         { .compatible = "rockchip,rk3399-spi", },
 839         { },
 840 };
 841 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
 842
 843 static struct platform_driver rockchip_spi_driver = {
 844         .driver = {
 845                 .name   = DRIVER_NAME,
 846                 .pm = &rockchip_spi_pm,
 847                 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
 848         },
 849         .probe = rockchip_spi_probe,
 850         .remove = rockchip_spi_remove,
 851 };
 852
 853 module_platform_driver(rockchip_spi_driver);
 854
 855 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
 856 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
 857 MODULE_LICENSE("GPL v2");