drivers/spi/spi-rockchip.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  * Author: Addy Ke <addy.ke@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/dmaengine.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/pinctrl/consumer.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/scatterlist.h>
  25
  26 #define DRIVER_NAME "rockchip-spi"
  27
  28 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
  29                 writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
  30 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \
  31                 writel_relaxed(readl_relaxed(reg) | (bits), reg)
  32
  33 /* SPI register offsets */
  34 #define ROCKCHIP_SPI_CTRLR0                     0x0000
  35 #define ROCKCHIP_SPI_CTRLR1                     0x0004
  36 #define ROCKCHIP_SPI_SSIENR                     0x0008
  37 #define ROCKCHIP_SPI_SER                        0x000c
  38 #define ROCKCHIP_SPI_BAUDR                      0x0010
  39 #define ROCKCHIP_SPI_TXFTLR                     0x0014
  40 #define ROCKCHIP_SPI_RXFTLR                     0x0018
  41 #define ROCKCHIP_SPI_TXFLR                      0x001c
  42 #define ROCKCHIP_SPI_RXFLR                      0x0020
  43 #define ROCKCHIP_SPI_SR                         0x0024
  44 #define ROCKCHIP_SPI_IPR                        0x0028
  45 #define ROCKCHIP_SPI_IMR                        0x002c
  46 #define ROCKCHIP_SPI_ISR                        0x0030
  47 #define ROCKCHIP_SPI_RISR                       0x0034
  48 #define ROCKCHIP_SPI_ICR                        0x0038
  49 #define ROCKCHIP_SPI_DMACR                      0x003c
  50 #define ROCKCHIP_SPI_DMATDLR            0x0040
  51 #define ROCKCHIP_SPI_DMARDLR            0x0044
  52 #define ROCKCHIP_SPI_TXDR                       0x0400
  53 #define ROCKCHIP_SPI_RXDR                       0x0800
  54
  55 /* Bit fields in CTRLR0 */
  56 #define CR0_DFS_OFFSET                          0
  57
  58 #define CR0_CFS_OFFSET                          2
  59
  60 #define CR0_SCPH_OFFSET                         6
  61
  62 #define CR0_SCPOL_OFFSET                        7
  63
  64 #define CR0_CSM_OFFSET                          8
  65 #define CR0_CSM_KEEP                            0x0
  66 /* ss_n be high for half sclk_out cycles */
  67 #define CR0_CSM_HALF                            0X1
  68 /* ss_n be high for one sclk_out cycle */
  69 #define CR0_CSM_ONE                                     0x2
  70
  71 /* ss_n to sclk_out delay */
  72 #define CR0_SSD_OFFSET                          10
  73 /*
  74  * The period between ss_n active and
  75  * sclk_out active is half sclk_out cycles
  76  */
  77 #define CR0_SSD_HALF                            0x0
  78 /*
  79  * The period between ss_n active and
  80  * sclk_out active is one sclk_out cycle
  81  */
  82 #define CR0_SSD_ONE                                     0x1
  83
  84 #define CR0_EM_OFFSET                           11
  85 #define CR0_EM_LITTLE                           0x0
  86 #define CR0_EM_BIG                                      0x1
  87
  88 #define CR0_FBM_OFFSET                          12
  89 #define CR0_FBM_MSB                                     0x0
  90 #define CR0_FBM_LSB                                     0x1
  91
  92 #define CR0_BHT_OFFSET                          13
  93 #define CR0_BHT_16BIT                           0x0
  94 #define CR0_BHT_8BIT                            0x1
  95
  96 #define CR0_RSD_OFFSET                          14
  97
  98 #define CR0_FRF_OFFSET                          16
  99 #define CR0_FRF_SPI                                     0x0
 100 #define CR0_FRF_SSP                                     0x1
 101 #define CR0_FRF_MICROWIRE                       0x2
 102
 103 #define CR0_XFM_OFFSET                          18
 104 #define CR0_XFM_MASK                            (0x03 << SPI_XFM_OFFSET)
 105 #define CR0_XFM_TR                                      0x0
 106 #define CR0_XFM_TO                                      0x1
 107 #define CR0_XFM_RO                                      0x2
 108
 109 #define CR0_OPM_OFFSET                          20
 110 #define CR0_OPM_MASTER                          0x0
 111 #define CR0_OPM_SLAVE                           0x1
 112
 113 #define CR0_MTM_OFFSET                          0x21
 114
 115 /* Bit fields in SER, 2bit */
 116 #define SER_MASK                                        0x3
 117
 118 /* Bit fields in SR, 5bit */
 119 #define SR_MASK                                         0x1f
 120 #define SR_BUSY                                         (1 << 0)
 121 #define SR_TF_FULL                                      (1 << 1)
 122 #define SR_TF_EMPTY                                     (1 << 2)
 123 #define SR_RF_EMPTY                                     (1 << 3)
 124 #define SR_RF_FULL                                      (1 << 4)
 125
 126 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
 127 #define INT_MASK                                        0x1f
 128 #define INT_TF_EMPTY                            (1 << 0)
 129 #define INT_TF_OVERFLOW                         (1 << 1)
 130 #define INT_RF_UNDERFLOW                        (1 << 2)
 131 #define INT_RF_OVERFLOW                         (1 << 3)
 132 #define INT_RF_FULL                                     (1 << 4)
 133
 134 /* Bit fields in ICR, 4bit */
 135 #define ICR_MASK                                        0x0f
 136 #define ICR_ALL                                         (1 << 0)
 137 #define ICR_RF_UNDERFLOW                        (1 << 1)
 138 #define ICR_RF_OVERFLOW                         (1 << 2)
 139 #define ICR_TF_OVERFLOW                         (1 << 3)
 140
 141 /* Bit fields in DMACR */
 142 #define RF_DMA_EN                                       (1 << 0)
 143 #define TF_DMA_EN                                       (1 << 1)
 144
 145 /* Driver state flags */
 146 #define RXDMA                                   (1 << 0)
 147 #define TXDMA                                   (1 << 1)
 148
 149 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
 150 #define MAX_SCLK_OUT            50000000
 151
 152 /*
 153  * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
 154  * the controller seems to hang when given 0x10000, so stick with this for now.
 155  */
 156 #define ROCKCHIP_SPI_MAX_TRANLEN                0xffff
 157
 158 #define ROCKCHIP_SPI_MAX_CS_NUM                 2
 159
 160 struct rockchip_spi_dma_data {
 161         struct dma_chan *ch;
 162         dma_addr_t addr;
 163 };
 164
 165 struct rockchip_spi {
 166         struct device *dev;
 167         struct spi_master *master;
 168
 169         struct clk *spiclk;
 170         struct clk *apb_pclk;
 171
 172         void __iomem *regs;
 173
 174         atomic_t state;
 175
 176         /*depth of the FIFO buffer */
 177         u32 fifo_len;
 178         /* max bus freq supported */
 179         u32 max_freq;
 180
 181         u16 mode;
 182         u8 tmode;
 183         u8 bpw;
 184         u8 n_bytes;
 185         u32 rsd_nsecs;
 186         unsigned len;
 187         u32 speed;
 188
 189         const void *tx;
 190         const void *tx_end;
 191         void *rx;
 192         void *rx_end;
 193
 194         bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
 195
 196         bool use_dma;
 197         struct sg_table tx_sg;
 198         struct sg_table rx_sg;
 199         struct rockchip_spi_dma_data dma_rx;
 200         struct rockchip_spi_dma_data dma_tx;
 201 };
 202
 203 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
 204 {
 205         writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
 206 }
 207
 208 static inline void spi_set_clk(struct rockchip_spi *rs, u16 div)
 209 {
 210         writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR);
 211 }
 212
 213 static inline void wait_for_idle(struct rockchip_spi *rs)
 214 {
 215         unsigned long timeout = jiffies + msecs_to_jiffies(5);
 216
 217         do {
 218                 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
 219                         return;
 220         } while (!time_after(jiffies, timeout));
 221
 222         dev_warn(rs->dev, "spi controller is in busy state!\n");
 223 }
 224
 225 static u32 get_fifo_len(struct rockchip_spi *rs)
 226 {
 227         u32 fifo;
 228
 229         for (fifo = 2; fifo < 32; fifo++) {
 230                 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
 231                 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
 232                         break;
 233         }
 234
 235         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
 236
 237         return (fifo == 31) ? 0 : fifo;
 238 }
 239
 240 static inline u32 tx_max(struct rockchip_spi *rs)
 241 {
 242         u32 tx_left, tx_room;
 243
 244         tx_left = (rs->tx_end - rs->tx) / rs->n_bytes;
 245         tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
 246
 247         return min(tx_left, tx_room);
 248 }
 249
 250 static inline u32 rx_max(struct rockchip_spi *rs)
 251 {
 252         u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes;
 253         u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 254
 255         return min(rx_left, rx_room);
 256 }
 257
 258 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
 259 {
 260         struct spi_master *master = spi->master;
 261         struct rockchip_spi *rs = spi_master_get_devdata(master);
 262         bool cs_asserted = !enable;
 263
 264         /* Return immediately for no-op */
 265         if (cs_asserted == rs->cs_asserted[spi->chip_select])
 266                 return;
 267
 268         if (cs_asserted) {
 269                 /* Keep things powered as long as CS is asserted */
 270                 pm_runtime_get_sync(rs->dev);
 271
 272                 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER,
 273                                       BIT(spi->chip_select));
 274         } else {
 275                 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER,
 276                                       BIT(spi->chip_select));
 277
 278                 /* Drop reference from when we first asserted CS */
 279                 pm_runtime_put(rs->dev);
 280         }
 281
 282         rs->cs_asserted[spi->chip_select] = cs_asserted;
 283 }
 284
 285 static int rockchip_spi_prepare_message(struct spi_master *master,
 286                                         struct spi_message *msg)
 287 {
 288         struct rockchip_spi *rs = spi_master_get_devdata(master);
 289         struct spi_device *spi = msg->spi;
 290
 291         rs->mode = spi->mode;
 292
 293         return 0;
 294 }
 295
 296 static void rockchip_spi_handle_err(struct spi_master *master,
 297                                     struct spi_message *msg)
 298 {
 299         struct rockchip_spi *rs = spi_master_get_devdata(master);
 300
 301         /* stop running spi transfer
 302          * this also flushes both rx and tx fifos
 303          */
 304         spi_enable_chip(rs, false);
 305
 306         if (atomic_read(&rs->state) & TXDMA)
 307                 dmaengine_terminate_async(rs->dma_tx.ch);
 308
 309         if (atomic_read(&rs->state) & RXDMA)
 310                 dmaengine_terminate_async(rs->dma_rx.ch);
 311 }
 312
 313 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
 314 {
 315         u32 max = tx_max(rs);
 316         u32 txw = 0;
 317
 318         while (max--) {
 319                 if (rs->n_bytes == 1)
 320                         txw = *(u8 *)(rs->tx);
 321                 else
 322                         txw = *(u16 *)(rs->tx);
 323
 324                 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
 325                 rs->tx += rs->n_bytes;
 326         }
 327 }
 328
 329 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
 330 {
 331         u32 max = rx_max(rs);
 332         u32 rxw;
 333
 334         while (max--) {
 335                 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 336                 if (rs->n_bytes == 1)
 337                         *(u8 *)(rs->rx) = (u8)rxw;
 338                 else
 339                         *(u16 *)(rs->rx) = (u16)rxw;
 340                 rs->rx += rs->n_bytes;
 341         }
 342 }
 343
 344 static int rockchip_spi_pio_transfer(struct rockchip_spi *rs)
 345 {
 346         int remain = 0;
 347
 348         spi_enable_chip(rs, true);
 349
 350         do {
 351                 if (rs->tx) {
 352                         remain = rs->tx_end - rs->tx;
 353                         rockchip_spi_pio_writer(rs);
 354                 }
 355
 356                 if (rs->rx) {
 357                         remain = rs->rx_end - rs->rx;
 358                         rockchip_spi_pio_reader(rs);
 359                 }
 360
 361                 cpu_relax();
 362         } while (remain);
 363
 364         /* If tx, wait until the FIFO data completely. */
 365         if (rs->tx)
 366                 wait_for_idle(rs);
 367
 368         spi_enable_chip(rs, false);
 369
 370         return 0;
 371 }
 372
 373 static void rockchip_spi_dma_rxcb(void *data)
 374 {
 375         struct rockchip_spi *rs = data;
 376         int state = atomic_fetch_andnot(RXDMA, &rs->state);
 377
 378         if (state & TXDMA)
 379                 return;
 380
 381         spi_enable_chip(rs, false);
 382         spi_finalize_current_transfer(rs->master);
 383 }
 384
 385 static void rockchip_spi_dma_txcb(void *data)
 386 {
 387         struct rockchip_spi *rs = data;
 388         int state = atomic_fetch_andnot(TXDMA, &rs->state);
 389
 390         if (state & RXDMA)
 391                 return;
 392
 393         /* Wait until the FIFO data completely. */
 394         wait_for_idle(rs);
 395
 396         spi_enable_chip(rs, false);
 397         spi_finalize_current_transfer(rs->master);
 398 }
 399
 400 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs)
 401 {
 402         struct dma_async_tx_descriptor *rxdesc, *txdesc;
 403
 404         atomic_set(&rs->state, 0);
 405
 406         rxdesc = NULL;
 407         if (rs->rx) {
 408                 struct dma_slave_config rxconf = {
 409                         .direction = DMA_DEV_TO_MEM,
 410                         .src_addr = rs->dma_rx.addr,
 411                         .src_addr_width = rs->n_bytes,
 412                         .src_maxburst = 1,
 413                 };
 414
 415                 dmaengine_slave_config(rs->dma_rx.ch, &rxconf);
 416
 417                 rxdesc = dmaengine_prep_slave_sg(
 418                                 rs->dma_rx.ch,
 419                                 rs->rx_sg.sgl, rs->rx_sg.nents,
 420                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
 421                 if (!rxdesc)
 422                         return -EINVAL;
 423
 424                 rxdesc->callback = rockchip_spi_dma_rxcb;
 425                 rxdesc->callback_param = rs;
 426         }
 427
 428         txdesc = NULL;
 429         if (rs->tx) {
 430                 struct dma_slave_config txconf = {
 431                         .direction = DMA_MEM_TO_DEV,
 432                         .dst_addr = rs->dma_tx.addr,
 433                         .dst_addr_width = rs->n_bytes,
 434                         .dst_maxburst = rs->fifo_len / 2,
 435                 };
 436
 437                 dmaengine_slave_config(rs->dma_tx.ch, &txconf);
 438
 439                 txdesc = dmaengine_prep_slave_sg(
 440                                 rs->dma_tx.ch,
 441                                 rs->tx_sg.sgl, rs->tx_sg.nents,
 442                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 443                 if (!txdesc) {
 444                         if (rxdesc)
 445                                 dmaengine_terminate_sync(rs->dma_rx.ch);
 446                         return -EINVAL;
 447                 }
 448
 449                 txdesc->callback = rockchip_spi_dma_txcb;
 450                 txdesc->callback_param = rs;
 451         }
 452
 453         /* rx must be started before tx due to spi instinct */
 454         if (rxdesc) {
 455                 atomic_or(RXDMA, &rs->state);
 456                 dmaengine_submit(rxdesc);
 457                 dma_async_issue_pending(rs->dma_rx.ch);
 458         }
 459
 460         spi_enable_chip(rs, true);
 461
 462         if (txdesc) {
 463                 atomic_or(TXDMA, &rs->state);
 464                 dmaengine_submit(txdesc);
 465                 dma_async_issue_pending(rs->dma_tx.ch);
 466         }
 467
 468         /* 1 means the transfer is in progress */
 469         return 1;
 470 }
 471
 472 static void rockchip_spi_config(struct rockchip_spi *rs)
 473 {
 474         u32 div = 0;
 475         u32 dmacr = 0;
 476         int rsd = 0;
 477
 478         u32 cr0 = CR0_FRF_SPI  << CR0_FRF_OFFSET
 479                 | CR0_BHT_8BIT << CR0_BHT_OFFSET
 480                 | CR0_SSD_ONE  << CR0_SSD_OFFSET
 481                 | CR0_EM_BIG   << CR0_EM_OFFSET;
 482
 483         cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
 484         cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
 485         cr0 |= (rs->tmode << CR0_XFM_OFFSET);
 486
 487         if (rs->use_dma) {
 488                 if (rs->tx)
 489                         dmacr |= TF_DMA_EN;
 490                 if (rs->rx)
 491                         dmacr |= RF_DMA_EN;
 492         }
 493
 494         if (WARN_ON(rs->speed > MAX_SCLK_OUT))
 495                 rs->speed = MAX_SCLK_OUT;
 496
 497         /* the minimum divisor is 2 */
 498         if (rs->max_freq < 2 * rs->speed) {
 499                 clk_set_rate(rs->spiclk, 2 * rs->speed);
 500                 rs->max_freq = clk_get_rate(rs->spiclk);
 501         }
 502
 503         /* div doesn't support odd number */
 504         div = DIV_ROUND_UP(rs->max_freq, rs->speed);
 505         div = (div + 1) & 0xfffe;
 506
 507         /* Rx sample delay is expressed in parent clock cycles (max 3) */
 508         rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8),
 509                                 1000000000 >> 8);
 510         if (!rsd && rs->rsd_nsecs) {
 511                 pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n",
 512                              rs->max_freq, rs->rsd_nsecs);
 513         } else if (rsd > 3) {
 514                 rsd = 3;
 515                 pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n",
 516                              rs->max_freq, rs->rsd_nsecs,
 517                              rsd * 1000000000U / rs->max_freq);
 518         }
 519         cr0 |= rsd << CR0_RSD_OFFSET;
 520
 521         writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
 522
 523         if (rs->n_bytes == 1)
 524                 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 525         else if (rs->n_bytes == 2)
 526                 writel_relaxed((rs->len / 2) - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 527         else
 528                 writel_relaxed((rs->len * 2) - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 529
 530         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
 531         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 532
 533         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
 534         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
 535         writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
 536
 537         spi_set_clk(rs, div);
 538
 539         dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
 540 }
 541
 542 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
 543 {
 544         return ROCKCHIP_SPI_MAX_TRANLEN;
 545 }
 546
 547 static int rockchip_spi_transfer_one(
 548                 struct spi_master *master,
 549                 struct spi_device *spi,
 550                 struct spi_transfer *xfer)
 551 {
 552         struct rockchip_spi *rs = spi_master_get_devdata(master);
 553
 554         WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
 555                 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
 556
 557         if (!xfer->tx_buf && !xfer->rx_buf) {
 558                 dev_err(rs->dev, "No buffer for transfer\n");
 559                 return -EINVAL;
 560         }
 561
 562         if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
 563                 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
 564                 return -EINVAL;
 565         }
 566
 567         rs->speed = xfer->speed_hz;
 568         rs->bpw = xfer->bits_per_word;
 569         rs->n_bytes = rs->bpw >> 3;
 570
 571         rs->tx = xfer->tx_buf;
 572         rs->tx_end = rs->tx + xfer->len;
 573         rs->rx = xfer->rx_buf;
 574         rs->rx_end = rs->rx + xfer->len;
 575         rs->len = xfer->len;
 576
 577         rs->tx_sg = xfer->tx_sg;
 578         rs->rx_sg = xfer->rx_sg;
 579
 580         if (rs->tx && rs->rx)
 581                 rs->tmode = CR0_XFM_TR;
 582         else if (rs->tx)
 583                 rs->tmode = CR0_XFM_TO;
 584         else if (rs->rx)
 585                 rs->tmode = CR0_XFM_RO;
 586
 587         /* we need prepare dma before spi was enabled */
 588         if (master->can_dma && master->can_dma(master, spi, xfer))
 589                 rs->use_dma = true;
 590         else
 591                 rs->use_dma = false;
 592
 593         rockchip_spi_config(rs);
 594
 595         if (rs->use_dma)
 596                 return rockchip_spi_prepare_dma(rs);
 597
 598         return rockchip_spi_pio_transfer(rs);
 599 }
 600
 601 static bool rockchip_spi_can_dma(struct spi_master *master,
 602                                  struct spi_device *spi,
 603                                  struct spi_transfer *xfer)
 604 {
 605         struct rockchip_spi *rs = spi_master_get_devdata(master);
 606
 607         return (xfer->len > rs->fifo_len);
 608 }
 609
 610 static int rockchip_spi_probe(struct platform_device *pdev)
 611 {
 612         int ret;
 613         struct rockchip_spi *rs;
 614         struct spi_master *master;
 615         struct resource *mem;
 616         u32 rsd_nsecs;
 617
 618         master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
 619         if (!master)
 620                 return -ENOMEM;
 621
 622         platform_set_drvdata(pdev, master);
 623
 624         rs = spi_master_get_devdata(master);
 625
 626         /* Get basic io resource and map it */
 627         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 628         rs->regs = devm_ioremap_resource(&pdev->dev, mem);
 629         if (IS_ERR(rs->regs)) {
 630                 ret =  PTR_ERR(rs->regs);
 631                 goto err_put_master;
 632         }
 633
 634         rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
 635         if (IS_ERR(rs->apb_pclk)) {
 636                 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
 637                 ret = PTR_ERR(rs->apb_pclk);
 638                 goto err_put_master;
 639         }
 640
 641         rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
 642         if (IS_ERR(rs->spiclk)) {
 643                 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
 644                 ret = PTR_ERR(rs->spiclk);
 645                 goto err_put_master;
 646         }
 647
 648         ret = clk_prepare_enable(rs->apb_pclk);
 649         if (ret < 0) {
 650                 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
 651                 goto err_put_master;
 652         }
 653
 654         ret = clk_prepare_enable(rs->spiclk);
 655         if (ret < 0) {
 656                 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
 657                 goto err_disable_apbclk;
 658         }
 659
 660         spi_enable_chip(rs, false);
 661
 662         rs->master = master;
 663         rs->dev = &pdev->dev;
 664         rs->max_freq = clk_get_rate(rs->spiclk);
 665
 666         if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
 667                                   &rsd_nsecs))
 668                 rs->rsd_nsecs = rsd_nsecs;
 669
 670         rs->fifo_len = get_fifo_len(rs);
 671         if (!rs->fifo_len) {
 672                 dev_err(&pdev->dev, "Failed to get fifo length\n");
 673                 ret = -EINVAL;
 674                 goto err_disable_spiclk;
 675         }
 676
 677         pm_runtime_set_active(&pdev->dev);
 678         pm_runtime_enable(&pdev->dev);
 679
 680         master->auto_runtime_pm = true;
 681         master->bus_num = pdev->id;
 682         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
 683         master->num_chipselect = ROCKCHIP_SPI_MAX_CS_NUM;
 684         master->dev.of_node = pdev->dev.of_node;
 685         master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
 686
 687         master->set_cs = rockchip_spi_set_cs;
 688         master->prepare_message = rockchip_spi_prepare_message;
 689         master->transfer_one = rockchip_spi_transfer_one;
 690         master->max_transfer_size = rockchip_spi_max_transfer_size;
 691         master->handle_err = rockchip_spi_handle_err;
 692         master->flags = SPI_MASTER_GPIO_SS;
 693
 694         rs->dma_tx.ch = dma_request_chan(rs->dev, "tx");
 695         if (IS_ERR(rs->dma_tx.ch)) {
 696                 /* Check tx to see if we need defer probing driver */
 697                 if (PTR_ERR(rs->dma_tx.ch) == -EPROBE_DEFER) {
 698                         ret = -EPROBE_DEFER;
 699                         goto err_disable_pm_runtime;
 700                 }
 701                 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
 702                 rs->dma_tx.ch = NULL;
 703         }
 704
 705         rs->dma_rx.ch = dma_request_chan(rs->dev, "rx");
 706         if (IS_ERR(rs->dma_rx.ch)) {
 707                 if (PTR_ERR(rs->dma_rx.ch) == -EPROBE_DEFER) {
 708                         ret = -EPROBE_DEFER;
 709                         goto err_free_dma_tx;
 710                 }
 711                 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
 712                 rs->dma_rx.ch = NULL;
 713         }
 714
 715         if (rs->dma_tx.ch && rs->dma_rx.ch) {
 716                 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR);
 717                 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR);
 718
 719                 master->can_dma = rockchip_spi_can_dma;
 720                 master->dma_tx = rs->dma_tx.ch;
 721                 master->dma_rx = rs->dma_rx.ch;
 722         }
 723
 724         ret = devm_spi_register_master(&pdev->dev, master);
 725         if (ret < 0) {
 726                 dev_err(&pdev->dev, "Failed to register master\n");
 727                 goto err_free_dma_rx;
 728         }
 729
 730         return 0;
 731
 732 err_free_dma_rx:
 733         if (rs->dma_rx.ch)
 734                 dma_release_channel(rs->dma_rx.ch);
 735 err_free_dma_tx:
 736         if (rs->dma_tx.ch)
 737                 dma_release_channel(rs->dma_tx.ch);
 738 err_disable_pm_runtime:
 739         pm_runtime_disable(&pdev->dev);
 740 err_disable_spiclk:
 741         clk_disable_unprepare(rs->spiclk);
 742 err_disable_apbclk:
 743         clk_disable_unprepare(rs->apb_pclk);
 744 err_put_master:
 745         spi_master_put(master);
 746
 747         return ret;
 748 }
 749
 750 static int rockchip_spi_remove(struct platform_device *pdev)
 751 {
 752         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
 753         struct rockchip_spi *rs = spi_master_get_devdata(master);
 754
 755         pm_runtime_get_sync(&pdev->dev);
 756
 757         clk_disable_unprepare(rs->spiclk);
 758         clk_disable_unprepare(rs->apb_pclk);
 759
 760         pm_runtime_put_noidle(&pdev->dev);
 761         pm_runtime_disable(&pdev->dev);
 762         pm_runtime_set_suspended(&pdev->dev);
 763
 764         if (rs->dma_tx.ch)
 765                 dma_release_channel(rs->dma_tx.ch);
 766         if (rs->dma_rx.ch)
 767                 dma_release_channel(rs->dma_rx.ch);
 768
 769         spi_master_put(master);
 770
 771         return 0;
 772 }
 773
 774 #ifdef CONFIG_PM_SLEEP
 775 static int rockchip_spi_suspend(struct device *dev)
 776 {
 777         int ret;
 778         struct spi_master *master = dev_get_drvdata(dev);
 779         struct rockchip_spi *rs = spi_master_get_devdata(master);
 780
 781         ret = spi_master_suspend(rs->master);
 782         if (ret < 0)
 783                 return ret;
 784
 785         ret = pm_runtime_force_suspend(dev);
 786         if (ret < 0)
 787                 return ret;
 788
 789         pinctrl_pm_select_sleep_state(dev);
 790
 791         return 0;
 792 }
 793
 794 static int rockchip_spi_resume(struct device *dev)
 795 {
 796         int ret;
 797         struct spi_master *master = dev_get_drvdata(dev);
 798         struct rockchip_spi *rs = spi_master_get_devdata(master);
 799
 800         pinctrl_pm_select_default_state(dev);
 801
 802         ret = pm_runtime_force_resume(dev);
 803         if (ret < 0)
 804                 return ret;
 805
 806         ret = spi_master_resume(rs->master);
 807         if (ret < 0) {
 808                 clk_disable_unprepare(rs->spiclk);
 809                 clk_disable_unprepare(rs->apb_pclk);
 810         }
 811
 812         return 0;
 813 }
 814 #endif /* CONFIG_PM_SLEEP */
 815
 816 #ifdef CONFIG_PM
 817 static int rockchip_spi_runtime_suspend(struct device *dev)
 818 {
 819         struct spi_master *master = dev_get_drvdata(dev);
 820         struct rockchip_spi *rs = spi_master_get_devdata(master);
 821
 822         clk_disable_unprepare(rs->spiclk);
 823         clk_disable_unprepare(rs->apb_pclk);
 824
 825         return 0;
 826 }
 827
 828 static int rockchip_spi_runtime_resume(struct device *dev)
 829 {
 830         int ret;
 831         struct spi_master *master = dev_get_drvdata(dev);
 832         struct rockchip_spi *rs = spi_master_get_devdata(master);
 833
 834         ret = clk_prepare_enable(rs->apb_pclk);
 835         if (ret < 0)
 836                 return ret;
 837
 838         ret = clk_prepare_enable(rs->spiclk);
 839         if (ret < 0)
 840                 clk_disable_unprepare(rs->apb_pclk);
 841
 842         return 0;
 843 }
 844 #endif /* CONFIG_PM */
 845
 846 static const struct dev_pm_ops rockchip_spi_pm = {
 847         SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
 848         SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
 849                            rockchip_spi_runtime_resume, NULL)
 850 };
 851
 852 static const struct of_device_id rockchip_spi_dt_match[] = {
 853         { .compatible = "rockchip,rv1108-spi", },
 854         { .compatible = "rockchip,rk3036-spi", },
 855         { .compatible = "rockchip,rk3066-spi", },
 856         { .compatible = "rockchip,rk3188-spi", },
 857         { .compatible = "rockchip,rk3228-spi", },
 858         { .compatible = "rockchip,rk3288-spi", },
 859         { .compatible = "rockchip,rk3368-spi", },
 860         { .compatible = "rockchip,rk3399-spi", },
 861         { },
 862 };
 863 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
 864
 865 static struct platform_driver rockchip_spi_driver = {
 866         .driver = {
 867                 .name   = DRIVER_NAME,
 868                 .pm = &rockchip_spi_pm,
 869                 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
 870         },
 871         .probe = rockchip_spi_probe,
 872         .remove = rockchip_spi_remove,
 873 };
 874
 875 module_platform_driver(rockchip_spi_driver);
 876
 877 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
 878 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
 879 MODULE_LICENSE("GPL v2");