1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Qualcomm QUP SPI controller
4 * FIFO and Block modes supported, no DMA
7 * Copyright (c) 2020 Sartura Ltd.
9 * Author: Robert Marko <robert.marko@sartura.hr>
10 * Author: Luka Kovacic <luka.kovacic@sartura.hr>
12 * Based on stock U-Boot and Linux drivers
21 #include <linux/delay.h>
24 #define QUP_CONFIG 0x0000
25 #define QUP_STATE 0x0004
26 #define QUP_IO_M_MODES 0x0008
27 #define QUP_SW_RESET 0x000c
28 #define QUP_OPERATIONAL 0x0018
29 #define QUP_ERROR_FLAGS 0x001c
30 #define QUP_ERROR_FLAGS_EN 0x0020
31 #define QUP_OPERATIONAL_MASK 0x0028
32 #define QUP_HW_VERSION 0x0030
33 #define QUP_MX_OUTPUT_CNT 0x0100
34 #define QUP_OUTPUT_FIFO 0x0110
35 #define QUP_MX_WRITE_CNT 0x0150
36 #define QUP_MX_INPUT_CNT 0x0200
37 #define QUP_MX_READ_CNT 0x0208
38 #define QUP_INPUT_FIFO 0x0218
40 #define SPI_CONFIG 0x0300
41 #define SPI_IO_CONTROL 0x0304
42 #define SPI_ERROR_FLAGS 0x0308
43 #define SPI_ERROR_FLAGS_EN 0x030c
45 /* QUP_CONFIG fields */
46 #define QUP_CONFIG_SPI_MODE BIT(8)
47 #define QUP_CONFIG_CLOCK_AUTO_GATE BIT(13)
48 #define QUP_CONFIG_NO_INPUT BIT(7)
49 #define QUP_CONFIG_NO_OUTPUT BIT(6)
50 #define QUP_CONFIG_N 0x001f
52 /* QUP_STATE fields */
53 #define QUP_STATE_VALID BIT(2)
54 #define QUP_STATE_RESET 0
55 #define QUP_STATE_RUN 1
56 #define QUP_STATE_PAUSE 3
57 #define QUP_STATE_MASK 3
58 #define QUP_STATE_CLEAR 2
60 /* QUP_IO_M_MODES fields */
61 #define QUP_IO_M_PACK_EN BIT(15)
62 #define QUP_IO_M_UNPACK_EN BIT(14)
63 #define QUP_IO_M_INPUT_MODE_MASK_SHIFT 12
64 #define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT 10
65 #define QUP_IO_M_INPUT_MODE_MASK (3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT)
66 #define QUP_IO_M_OUTPUT_MODE_MASK (3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT)
68 #define QUP_IO_M_OUTPUT_BLOCK_SIZE(x) (((x) & (0x03 << 0)) >> 0)
69 #define QUP_IO_M_OUTPUT_FIFO_SIZE(x) (((x) & (0x07 << 2)) >> 2)
70 #define QUP_IO_M_INPUT_BLOCK_SIZE(x) (((x) & (0x03 << 5)) >> 5)
71 #define QUP_IO_M_INPUT_FIFO_SIZE(x) (((x) & (0x07 << 7)) >> 7)
73 #define QUP_IO_M_MODE_FIFO 0
74 #define QUP_IO_M_MODE_BLOCK 1
75 #define QUP_IO_M_MODE_DMOV 2
76 #define QUP_IO_M_MODE_BAM 3
78 /* QUP_OPERATIONAL fields */
79 #define QUP_OP_IN_BLOCK_READ_REQ BIT(13)
80 #define QUP_OP_OUT_BLOCK_WRITE_REQ BIT(12)
81 #define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11)
82 #define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10)
83 #define QUP_OP_IN_SERVICE_FLAG BIT(9)
84 #define QUP_OP_OUT_SERVICE_FLAG BIT(8)
85 #define QUP_OP_IN_FIFO_FULL BIT(7)
86 #define QUP_OP_OUT_FIFO_FULL BIT(6)
87 #define QUP_OP_IN_FIFO_NOT_EMPTY BIT(5)
88 #define QUP_OP_OUT_FIFO_NOT_EMPTY BIT(4)
90 /* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */
91 #define QUP_ERROR_OUTPUT_OVER_RUN BIT(5)
92 #define QUP_ERROR_INPUT_UNDER_RUN BIT(4)
93 #define QUP_ERROR_OUTPUT_UNDER_RUN BIT(3)
94 #define QUP_ERROR_INPUT_OVER_RUN BIT(2)
96 /* SPI_CONFIG fields */
97 #define SPI_CONFIG_HS_MODE BIT(10)
98 #define SPI_CONFIG_INPUT_FIRST BIT(9)
99 #define SPI_CONFIG_LOOPBACK BIT(8)
101 /* SPI_IO_CONTROL fields */
102 #define SPI_IO_C_FORCE_CS BIT(11)
103 #define SPI_IO_C_CLK_IDLE_HIGH BIT(10)
104 #define SPI_IO_C_MX_CS_MODE BIT(8)
105 #define SPI_IO_C_CS_N_POLARITY_0 BIT(4)
106 #define SPI_IO_C_CS_SELECT(x) (((x) & 3) << 2)
107 #define SPI_IO_C_CS_SELECT_MASK 0x000c
108 #define SPI_IO_C_TRISTATE_CS BIT(1)
109 #define SPI_IO_C_NO_TRI_STATE BIT(0)
111 /* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */
112 #define SPI_ERROR_CLK_OVER_RUN BIT(1)
113 #define SPI_ERROR_CLK_UNDER_RUN BIT(0)
115 #define SPI_NUM_CHIPSELECTS 4
117 #define SPI_DELAY_THRESHOLD 1
118 #define SPI_DELAY_RETRY 10
120 #define SPI_RESET_STATE 0
121 #define SPI_RUN_STATE 1
122 #define SPI_CORE_RESET 0
123 #define SPI_CORE_RUNNING 1
125 #define DUMMY_DATA_VAL 0
126 #define TIMEOUT_CNT 100
128 #define QUP_STATE_VALID_BIT 2
129 #define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8)
130 #define QUP_CONFIG_MINI_CORE_SPI BIT(8)
131 #define QUP_CONF_INPUT_MSK BIT(7)
132 #define QUP_CONF_INPUT_ENA (0 << 7)
133 #define QUP_CONF_NO_INPUT BIT(7)
134 #define QUP_CONF_OUTPUT_MSK BIT(6)
135 #define QUP_CONF_OUTPUT_ENA (0 << 6)
136 #define QUP_CONF_NO_OUTPUT BIT(6)
137 #define QUP_STATE_RUN_STATE 0x1
138 #define QUP_STATE_RESET_STATE 0x0
139 #define QUP_STATE_PAUSE_STATE 0x3
140 #define SPI_BIT_WORD_MSK 0x1F
141 #define SPI_8_BIT_WORD 0x07
142 #define LOOP_BACK_MSK BIT(8)
143 #define NO_LOOP_BACK (0 << 8)
144 #define SLAVE_OPERATION_MSK BIT(5)
145 #define SLAVE_OPERATION (0 << 5)
146 #define CLK_ALWAYS_ON (0 << 9)
147 #define MX_CS_MODE BIT(8)
148 #define CS_POLARITY_MASK BIT(4)
149 #define NO_TRI_STATE BIT(0)
150 #define FORCE_CS_MSK BIT(11)
151 #define FORCE_CS_EN BIT(11)
152 #define FORCE_CS_DIS (0 << 11)
153 #define OUTPUT_BIT_SHIFT_MSK BIT(16)
154 #define OUTPUT_BIT_SHIFT_EN BIT(16)
155 #define INPUT_BLOCK_MODE_MSK (0x03 << 12)
156 #define INPUT_BLOCK_MODE (0x01 << 12)
157 #define OUTPUT_BLOCK_MODE_MSK (0x03 << 10)
158 #define OUTPUT_BLOCK_MODE (0x01 << 10)
159 #define INPUT_BAM_MODE (0x3 << 12)
160 #define OUTPUT_BAM_MODE (0x3 << 10)
161 #define PACK_EN (0x1 << 15)
162 #define UNPACK_EN (0x1 << 14)
163 #define PACK_EN_MSK (0x1 << 15)
164 #define UNPACK_EN_MSK (0x1 << 14)
165 #define OUTPUT_SERVICE_MSK (0x1 << 8)
166 #define INPUT_SERVICE_MSK (0x1 << 9)
167 #define OUTPUT_SERVICE_DIS (0x1 << 8)
168 #define INPUT_SERVICE_DIS (0x1 << 9)
169 #define BLSP0_SPI_DEASSERT_WAIT_REG 0x0310
170 #define QUP_DATA_AVAILABLE_FOR_READ BIT(5)
171 #define SPI_INPUT_BLOCK_SIZE 4
172 #define SPI_OUTPUT_BLOCK_SIZE 4
173 #define SPI_BITLEN_MSK 0x07
174 #define MAX_COUNT_SIZE 0xffff
176 struct qup_spi_priv {
180 struct gpio_desc cs_gpios[SPI_NUM_CHIPSELECTS];
185 static int qup_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
187 struct qup_spi_priv *priv = dev_get_priv(dev);
189 debug("%s: cs=%d enable=%d\n", __func__, cs, enable);
191 if (cs >= SPI_NUM_CHIPSELECTS)
194 if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
200 return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
204 * Function to write data to OUTPUT FIFO
206 static void qup_spi_write_byte(struct udevice *dev, unsigned char data)
208 struct udevice *bus = dev_get_parent(dev);
209 struct qup_spi_priv *priv = dev_get_priv(bus);
210 /* Wait for space in the FIFO */
211 while ((readl(priv->base + QUP_OPERATIONAL) & QUP_OP_OUT_FIFO_FULL))
214 /* Write the byte of data */
215 writel(data, priv->base + QUP_OUTPUT_FIFO);
219 * Function to read data from Input FIFO
221 static unsigned char qup_spi_read_byte(struct udevice *dev)
223 struct udevice *bus = dev_get_parent(dev);
224 struct qup_spi_priv *priv = dev_get_priv(bus);
225 /* Wait for Data in FIFO */
226 while (!(readl(priv->base + QUP_OPERATIONAL) & QUP_DATA_AVAILABLE_FOR_READ)) {
227 printf("Stuck at FIFO data wait\n");
231 /* Read a byte of data */
232 return readl(priv->base + QUP_INPUT_FIFO) & 0xff;
236 * Function to check whether Input or Output FIFO
237 * has data to be serviced
239 static int qup_spi_check_fifo_status(struct udevice *dev, u32 reg_addr)
241 struct udevice *bus = dev_get_parent(dev);
242 struct qup_spi_priv *priv = dev_get_priv(bus);
243 unsigned int count = TIMEOUT_CNT;
244 unsigned int status_flag;
248 val = readl(priv->base + reg_addr);
253 status_flag = ((val & QUP_OP_OUT_SERVICE_FLAG) | (val & QUP_OP_IN_SERVICE_FLAG));
254 } while (!status_flag);
260 * Function to configure Input and Output enable/disable
262 static void qup_spi_enable_io_config(struct udevice *dev, u32 write_cnt, u32 read_cnt)
264 struct udevice *bus = dev_get_parent(dev);
265 struct qup_spi_priv *priv = dev_get_priv(bus);
268 clrsetbits_le32(priv->base + QUP_CONFIG,
269 QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA);
271 clrsetbits_le32(priv->base + QUP_CONFIG,
272 QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT);
276 clrsetbits_le32(priv->base + QUP_CONFIG,
277 QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA);
279 clrsetbits_le32(priv->base + QUP_CONFIG,
280 QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT);
284 static int check_bit_state(struct udevice *dev, u32 reg_addr, int bit_num, int val,
287 struct udevice *bus = dev_get_parent(dev);
288 struct qup_spi_priv *priv = dev_get_priv(bus);
289 unsigned int count = TIMEOUT_CNT;
290 unsigned int bit_val = ((readl(priv->base + reg_addr) >> bit_num) & 0x01);
292 while (bit_val != val) {
297 bit_val = ((readl(priv->base + reg_addr) >> bit_num) & 0x01);
304 * Check whether QUPn State is valid
306 static int check_qup_state_valid(struct udevice *dev)
308 return check_bit_state(dev, QUP_STATE, QUP_STATE_VALID, 1, 1);
312 * Configure QUPn Core state
314 static int qup_spi_config_spi_state(struct udevice *dev, unsigned int state)
316 struct udevice *bus = dev_get_parent(dev);
317 struct qup_spi_priv *priv = dev_get_priv(bus);
321 ret = check_qup_state_valid(dev);
327 /* Set the state to RUN */
328 val = ((readl(priv->base + QUP_STATE) & ~QUP_STATE_MASK)
330 writel(val, priv->base + QUP_STATE);
331 ret = check_qup_state_valid(dev);
334 priv->core_state = SPI_CORE_RUNNING;
336 case SPI_RESET_STATE:
337 /* Set the state to RESET */
338 val = ((readl(priv->base + QUP_STATE) & ~QUP_STATE_MASK)
340 writel(val, priv->base + QUP_STATE);
341 ret = check_qup_state_valid(dev);
344 priv->core_state = SPI_CORE_RESET;
347 printf("Unsupported QUP SPI state: %d\n", state);
355 * Function to read bytes number of data from the Input FIFO
357 static int __qup_spi_blsp_spi_read(struct udevice *dev, u8 *data_buffer, unsigned int bytes)
359 struct udevice *bus = dev_get_parent(dev);
360 struct qup_spi_priv *priv = dev_get_priv(bus);
363 unsigned int read_bytes = bytes;
364 unsigned int fifo_count;
368 /* Configure no of bytes to read */
369 state_config = qup_spi_config_spi_state(dev, SPI_RESET_STATE);
373 /* Configure input and output enable */
374 qup_spi_enable_io_config(dev, 0, read_bytes);
376 writel(bytes, priv->base + QUP_MX_INPUT_CNT);
378 state_config = qup_spi_config_spi_state(dev, SPI_RUN_STATE);
383 ret = qup_spi_check_fifo_status(dev, QUP_OPERATIONAL);
387 val = readl(priv->base + QUP_OPERATIONAL);
388 if (val & QUP_OP_IN_SERVICE_FLAG) {
390 * acknowledge to hw that software will
393 val &= QUP_OP_IN_SERVICE_FLAG;
394 writel(val, priv->base + QUP_OPERATIONAL);
396 fifo_count = ((read_bytes > SPI_INPUT_BLOCK_SIZE) ?
397 SPI_INPUT_BLOCK_SIZE : read_bytes);
399 for (i = 0; i < fifo_count; i++) {
400 *data_buffer = qup_spi_read_byte(dev);
409 * Put the SPI Core back in the Reset State
410 * to end the transfer
412 (void)qup_spi_config_spi_state(dev, SPI_RESET_STATE);
417 static int qup_spi_blsp_spi_read(struct udevice *dev, u8 *data_buffer, unsigned int bytes)
422 length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE;
424 ret = __qup_spi_blsp_spi_read(dev, data_buffer, length);
428 data_buffer += length;
436 * Function to write data to the Output FIFO
438 static int __qup_blsp_spi_write(struct udevice *dev, const u8 *cmd_buffer, unsigned int bytes)
440 struct udevice *bus = dev_get_parent(dev);
441 struct qup_spi_priv *priv = dev_get_priv(bus);
444 unsigned int write_len = bytes;
445 unsigned int read_len = bytes;
446 unsigned int fifo_count;
450 state_config = qup_spi_config_spi_state(dev, SPI_RESET_STATE);
454 writel(bytes, priv->base + QUP_MX_OUTPUT_CNT);
455 writel(bytes, priv->base + QUP_MX_INPUT_CNT);
456 state_config = qup_spi_config_spi_state(dev, SPI_RUN_STATE);
460 /* Configure input and output enable */
461 qup_spi_enable_io_config(dev, write_len, read_len);
464 * read_len considered to ensure that we read the dummy data for the
465 * write we performed. This is needed to ensure with WR-RD transaction
466 * to get the actual data on the subsequent read cycle that happens
468 while (write_len || read_len) {
469 ret = qup_spi_check_fifo_status(dev, QUP_OPERATIONAL);
473 val = readl(priv->base + QUP_OPERATIONAL);
474 if (val & QUP_OP_OUT_SERVICE_FLAG) {
476 * acknowledge to hw that software will write
477 * expected output data
479 val &= QUP_OP_OUT_SERVICE_FLAG;
480 writel(val, priv->base + QUP_OPERATIONAL);
482 if (write_len > SPI_OUTPUT_BLOCK_SIZE)
483 fifo_count = SPI_OUTPUT_BLOCK_SIZE;
485 fifo_count = write_len;
487 for (i = 0; i < fifo_count; i++) {
488 /* Write actual data to output FIFO */
489 qup_spi_write_byte(dev, *cmd_buffer);
494 if (val & QUP_OP_IN_SERVICE_FLAG) {
496 * acknowledge to hw that software
497 * will read input data
499 val &= QUP_OP_IN_SERVICE_FLAG;
500 writel(val, priv->base + QUP_OPERATIONAL);
502 if (read_len > SPI_INPUT_BLOCK_SIZE)
503 fifo_count = SPI_INPUT_BLOCK_SIZE;
505 fifo_count = read_len;
507 for (i = 0; i < fifo_count; i++) {
508 /* Read dummy data for the data written */
509 (void)qup_spi_read_byte(dev);
511 /* Decrement the write count after reading the
512 * dummy data from the device. This is to make
513 * sure we read dummy data before we write the
522 * Put the SPI Core back in the Reset State
523 * to end the transfer
525 (void)qup_spi_config_spi_state(dev, SPI_RESET_STATE);
530 static int qup_spi_blsp_spi_write(struct udevice *dev, const u8 *cmd_buffer, unsigned int bytes)
535 length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE;
537 ret = __qup_blsp_spi_write(dev, cmd_buffer, length);
541 cmd_buffer += length;
548 static int qup_spi_set_speed(struct udevice *dev, uint speed)
553 static int qup_spi_set_mode(struct udevice *dev, uint mode)
555 struct qup_spi_priv *priv = dev_get_priv(dev);
556 unsigned int clk_idle_state;
557 unsigned int input_first_mode;
563 input_first_mode = SPI_CONFIG_INPUT_FIRST;
567 input_first_mode = 0;
571 input_first_mode = SPI_CONFIG_INPUT_FIRST;
575 input_first_mode = 0;
578 printf("Unsupported spi mode: %d\n", mode);
582 if (mode & SPI_CS_HIGH)
583 priv->cs_high = true;
585 priv->cs_high = false;
587 val = readl(priv->base + SPI_CONFIG);
588 val |= input_first_mode;
589 writel(val, priv->base + SPI_CONFIG);
591 val = readl(priv->base + SPI_IO_CONTROL);
593 val |= SPI_IO_C_CLK_IDLE_HIGH;
595 val &= ~SPI_IO_C_CLK_IDLE_HIGH;
597 writel(val, priv->base + SPI_IO_CONTROL);
602 static void qup_spi_reset(struct udevice *dev)
604 struct udevice *bus = dev_get_parent(dev);
605 struct qup_spi_priv *priv = dev_get_priv(bus);
607 /* Driver may not be probed yet */
611 writel(0x1, priv->base + QUP_SW_RESET);
615 static int qup_spi_hw_init(struct udevice *dev)
617 struct udevice *bus = dev_get_parent(dev);
618 struct qup_spi_priv *priv = dev_get_priv(bus);
621 /* QUPn module configuration */
624 /* Set the QUPn state */
625 ret = qup_spi_config_spi_state(dev, SPI_RESET_STATE);
630 * Configure Mini core to SPI core with Input Output enabled,
631 * SPI master, N = 8 bits
633 clrsetbits_le32(priv->base + QUP_CONFIG, (QUP_CONFIG_MINI_CORE_MSK |
635 QUP_CONF_OUTPUT_MSK |
637 (QUP_CONFIG_MINI_CORE_SPI |
639 QUP_CONF_OUTPUT_ENA |
643 * Configure Input first SPI protocol,
644 * SPI master mode and no loopback
646 clrsetbits_le32(priv->base + SPI_CONFIG, (LOOP_BACK_MSK |
647 SLAVE_OPERATION_MSK),
652 * Configure SPI IO Control Register
657 writel((CLK_ALWAYS_ON | NO_TRI_STATE), priv->base + SPI_IO_CONTROL);
660 * Configure SPI IO Modes.
661 * OUTPUT_BIT_SHIFT_EN = 1
662 * INPUT_MODE = Block Mode
663 * OUTPUT MODE = Block Mode
666 clrsetbits_le32(priv->base + QUP_IO_M_MODES, (OUTPUT_BIT_SHIFT_MSK |
667 INPUT_BLOCK_MODE_MSK |
668 OUTPUT_BLOCK_MODE_MSK),
669 (OUTPUT_BIT_SHIFT_EN |
673 /* Disable Error mask */
674 writel(0, priv->base + SPI_ERROR_FLAGS_EN);
675 writel(0, priv->base + QUP_ERROR_FLAGS_EN);
676 writel(0, priv->base + BLSP0_SPI_DEASSERT_WAIT_REG);
681 static int qup_spi_claim_bus(struct udevice *dev)
685 ret = qup_spi_hw_init(dev);
692 static int qup_spi_release_bus(struct udevice *dev)
694 /* Reset the SPI hardware */
700 static int qup_spi_xfer(struct udevice *dev, unsigned int bitlen,
701 const void *dout, void *din, unsigned long flags)
703 struct udevice *bus = dev_get_parent(dev);
704 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
706 const u8 *txp = dout;
710 if (bitlen & SPI_BITLEN_MSK) {
711 printf("Invalid bit length\n");
717 if (flags & SPI_XFER_BEGIN) {
718 ret = qup_spi_hw_init(dev);
722 ret = qup_spi_set_cs(bus, slave_plat->cs, false);
728 ret = qup_spi_blsp_spi_write(dev, txp, len);
734 ret = qup_spi_blsp_spi_read(dev, rxp, len);
739 if (flags & SPI_XFER_END) {
740 ret = qup_spi_set_cs(bus, slave_plat->cs, true);
748 static int qup_spi_probe(struct udevice *dev)
750 struct qup_spi_priv *priv = dev_get_priv(dev);
753 priv->base = dev_read_addr(dev);
754 if (priv->base == FDT_ADDR_T_NONE)
757 ret = clk_get_by_index(dev, 0, &priv->clk);
761 ret = clk_enable(&priv->clk);
765 priv->num_cs = dev_read_u32_default(dev, "num-cs", 1);
767 ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
768 priv->num_cs, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
770 printf("Can't get %s cs gpios: %d\n", dev->name, ret);
777 static const struct dm_spi_ops qup_spi_ops = {
778 .claim_bus = qup_spi_claim_bus,
779 .release_bus = qup_spi_release_bus,
780 .xfer = qup_spi_xfer,
781 .set_speed = qup_spi_set_speed,
782 .set_mode = qup_spi_set_mode,
784 * cs_info is not needed, since we require all chip selects to be
785 * in the device tree explicitly
789 static const struct udevice_id qup_spi_ids[] = {
790 { .compatible = "qcom,spi-qup-v1.1.1", },
791 { .compatible = "qcom,spi-qup-v2.1.1", },
792 { .compatible = "qcom,spi-qup-v2.2.1", },
796 U_BOOT_DRIVER(spi_qup) = {
799 .of_match = qup_spi_ids,
801 .priv_auto = sizeof(struct qup_spi_priv),
802 .probe = qup_spi_probe,