drivers/spi/spi-qup.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for Qualcomm QUP SPI controller
   4  * FIFO and Block modes supported, no DMA
   5  * mode support
   6  *
   7  * Copyright (c) 2020 Sartura Ltd.
   8  *
   9  * Author: Robert Marko <robert.marko@sartura.hr>
  10  * Author: Luka Kovacic <luka.kovacic@sartura.hr>
  11  *
  12  * Based on stock U-boot and Linux drivers
  13  */
  14
  15 #include <asm/gpio.h>
  16 #include <asm/io.h>
  17 #include <clk.h>
  18 #include <common.h>
  19 #include <dm.h>
  20 #include <errno.h>
  21 #include <linux/delay.h>
  22 #include <spi.h>
  23
  24 #define QUP_CONFIG                              0x0000
  25 #define QUP_STATE                               0x0004
  26 #define QUP_IO_M_MODES                  0x0008
  27 #define QUP_SW_RESET                    0x000c
  28 #define QUP_OPERATIONAL                 0x0018
  29 #define QUP_ERROR_FLAGS                 0x001c
  30 #define QUP_ERROR_FLAGS_EN              0x0020
  31 #define QUP_OPERATIONAL_MASK    0x0028
  32 #define QUP_HW_VERSION                  0x0030
  33 #define QUP_MX_OUTPUT_CNT               0x0100
  34 #define QUP_OUTPUT_FIFO                 0x0110
  35 #define QUP_MX_WRITE_CNT                0x0150
  36 #define QUP_MX_INPUT_CNT                0x0200
  37 #define QUP_MX_READ_CNT                 0x0208
  38 #define QUP_INPUT_FIFO                  0x0218
  39
  40 #define SPI_CONFIG                              0x0300
  41 #define SPI_IO_CONTROL                  0x0304
  42 #define SPI_ERROR_FLAGS                 0x0308
  43 #define SPI_ERROR_FLAGS_EN              0x030c
  44
  45 /* QUP_CONFIG fields */
  46 #define QUP_CONFIG_SPI_MODE                     BIT(8)
  47 #define QUP_CONFIG_CLOCK_AUTO_GATE      BIT(13)
  48 #define QUP_CONFIG_NO_INPUT                     BIT(7)
  49 #define QUP_CONFIG_NO_OUTPUT            BIT(6)
  50 #define QUP_CONFIG_N                            0x001f
  51
  52 /* QUP_STATE fields */
  53 #define QUP_STATE_VALID                 BIT(2)
  54 #define QUP_STATE_RESET                 0
  55 #define QUP_STATE_RUN                   1
  56 #define QUP_STATE_PAUSE                 3
  57 #define QUP_STATE_MASK                  3
  58 #define QUP_STATE_CLEAR                 2
  59
  60 /* QUP_IO_M_MODES fields */
  61 #define QUP_IO_M_PACK_EN                BIT(15)
  62 #define QUP_IO_M_UNPACK_EN              BIT(14)
  63 #define QUP_IO_M_INPUT_MODE_MASK_SHIFT  12
  64 #define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT 10
  65 #define QUP_IO_M_INPUT_MODE_MASK        (3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT)
  66 #define QUP_IO_M_OUTPUT_MODE_MASK       (3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT)
  67
  68 #define QUP_IO_M_OUTPUT_BLOCK_SIZE(x)   (((x) & (0x03 << 0)) >> 0)
  69 #define QUP_IO_M_OUTPUT_FIFO_SIZE(x)    (((x) & (0x07 << 2)) >> 2)
  70 #define QUP_IO_M_INPUT_BLOCK_SIZE(x)    (((x) & (0x03 << 5)) >> 5)
  71 #define QUP_IO_M_INPUT_FIFO_SIZE(x)     (((x) & (0x07 << 7)) >> 7)
  72
  73 #define QUP_IO_M_MODE_FIFO              0
  74 #define QUP_IO_M_MODE_BLOCK             1
  75 #define QUP_IO_M_MODE_DMOV              2
  76 #define QUP_IO_M_MODE_BAM               3
  77
  78 /* QUP_OPERATIONAL fields */
  79 #define QUP_OP_IN_BLOCK_READ_REQ        BIT(13)
  80 #define QUP_OP_OUT_BLOCK_WRITE_REQ      BIT(12)
  81 #define QUP_OP_MAX_INPUT_DONE_FLAG      BIT(11)
  82 #define QUP_OP_MAX_OUTPUT_DONE_FLAG     BIT(10)
  83 #define QUP_OP_IN_SERVICE_FLAG          BIT(9)
  84 #define QUP_OP_OUT_SERVICE_FLAG         BIT(8)
  85 #define QUP_OP_IN_FIFO_FULL             BIT(7)
  86 #define QUP_OP_OUT_FIFO_FULL            BIT(6)
  87 #define QUP_OP_IN_FIFO_NOT_EMPTY        BIT(5)
  88 #define QUP_OP_OUT_FIFO_NOT_EMPTY       BIT(4)
  89
  90 /* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */
  91 #define QUP_ERROR_OUTPUT_OVER_RUN       BIT(5)
  92 #define QUP_ERROR_INPUT_UNDER_RUN       BIT(4)
  93 #define QUP_ERROR_OUTPUT_UNDER_RUN      BIT(3)
  94 #define QUP_ERROR_INPUT_OVER_RUN        BIT(2)
  95
  96 /* SPI_CONFIG fields */
  97 #define SPI_CONFIG_HS_MODE              BIT(10)
  98 #define SPI_CONFIG_INPUT_FIRST          BIT(9)
  99 #define SPI_CONFIG_LOOPBACK             BIT(8)
 100
 101 /* SPI_IO_CONTROL fields */
 102 #define SPI_IO_C_FORCE_CS               BIT(11)
 103 #define SPI_IO_C_CLK_IDLE_HIGH          BIT(10)
 104 #define SPI_IO_C_MX_CS_MODE             BIT(8)
 105 #define SPI_IO_C_CS_N_POLARITY_0        BIT(4)
 106 #define SPI_IO_C_CS_SELECT(x)           (((x) & 3) << 2)
 107 #define SPI_IO_C_CS_SELECT_MASK         0x000c
 108 #define SPI_IO_C_TRISTATE_CS            BIT(1)
 109 #define SPI_IO_C_NO_TRI_STATE           BIT(0)
 110
 111 /* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */
 112 #define SPI_ERROR_CLK_OVER_RUN          BIT(1)
 113 #define SPI_ERROR_CLK_UNDER_RUN         BIT(0)
 114
 115 #define SPI_NUM_CHIPSELECTS             4
 116
 117 #define SPI_DELAY_THRESHOLD             1
 118 #define SPI_DELAY_RETRY                 10
 119
 120 #define SPI_RESET_STATE                 0
 121 #define SPI_RUN_STATE                   1
 122 #define SPI_CORE_RESET                  0
 123 #define SPI_CORE_RUNNING                1
 124
 125 #define DUMMY_DATA_VAL                  0
 126 #define TIMEOUT_CNT                             100
 127
 128 #define QUP_STATE_VALID_BIT                             2
 129 #define QUP_CONFIG_MINI_CORE_MSK                (0x0F << 8)
 130 #define QUP_CONFIG_MINI_CORE_SPI                BIT(8)
 131 #define QUP_CONF_INPUT_MSK                              BIT(7)
 132 #define QUP_CONF_INPUT_ENA                              (0 << 7)
 133 #define QUP_CONF_NO_INPUT                               BIT(7)
 134 #define QUP_CONF_OUTPUT_MSK                             BIT(6)
 135 #define QUP_CONF_OUTPUT_ENA                             (0 << 6)
 136 #define QUP_CONF_NO_OUTPUT                              BIT(6)
 137 #define QUP_STATE_RUN_STATE                             0x1
 138 #define QUP_STATE_RESET_STATE                   0x0
 139 #define QUP_STATE_PAUSE_STATE                   0x3
 140 #define SPI_BIT_WORD_MSK                                0x1F
 141 #define SPI_8_BIT_WORD                                  0x07
 142 #define LOOP_BACK_MSK                                   BIT(8)
 143 #define NO_LOOP_BACK                                    (0 << 8)
 144 #define SLAVE_OPERATION_MSK                             BIT(5)
 145 #define SLAVE_OPERATION                                 (0 << 5)
 146 #define CLK_ALWAYS_ON                                   (0 << 9)
 147 #define MX_CS_MODE                                              BIT(8)
 148 #define CS_POLARITY_MASK                                BIT(4)
 149 #define NO_TRI_STATE                                    BIT(0)
 150 #define FORCE_CS_MSK                                    BIT(11)
 151 #define FORCE_CS_EN                                             BIT(11)
 152 #define FORCE_CS_DIS                                    (0 << 11)
 153 #define OUTPUT_BIT_SHIFT_MSK                    BIT(16)
 154 #define OUTPUT_BIT_SHIFT_EN                             BIT(16)
 155 #define INPUT_BLOCK_MODE_MSK                    (0x03 << 12)
 156 #define INPUT_BLOCK_MODE                                (0x01 << 12)
 157 #define OUTPUT_BLOCK_MODE_MSK                   (0x03 << 10)
 158 #define OUTPUT_BLOCK_MODE                               (0x01 << 10)
 159 #define INPUT_BAM_MODE                                  (0x3 << 12)
 160 #define OUTPUT_BAM_MODE                                 (0x3 << 10)
 161 #define PACK_EN                                                 (0x1 << 15)
 162 #define UNPACK_EN                                               (0x1 << 14)
 163 #define PACK_EN_MSK                                             (0x1 << 15)
 164 #define UNPACK_EN_MSK                                   (0x1 << 14)
 165 #define OUTPUT_SERVICE_MSK                              (0x1 << 8)
 166 #define INPUT_SERVICE_MSK                               (0x1 << 9)
 167 #define OUTPUT_SERVICE_DIS                              (0x1 << 8)
 168 #define INPUT_SERVICE_DIS                               (0x1 << 9)
 169 #define BLSP0_SPI_DEASSERT_WAIT_REG             0x0310
 170 #define QUP_DATA_AVAILABLE_FOR_READ             BIT(5)
 171 #define SPI_INPUT_BLOCK_SIZE                    4
 172 #define SPI_OUTPUT_BLOCK_SIZE                   4
 173 #define SPI_BITLEN_MSK                                  0x07
 174 #define MAX_COUNT_SIZE                                  0xffff
 175
 176 struct qup_spi_priv {
 177         phys_addr_t base;
 178         struct clk clk;
 179         u32 num_cs;
 180         struct gpio_desc cs_gpios[SPI_NUM_CHIPSELECTS];
 181         bool cs_high;
 182         u32 core_state;
 183 };
 184
 185 static int qup_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
 186 {
 187         struct qup_spi_priv *priv = dev_get_priv(dev);
 188
 189         debug("%s: cs=%d enable=%d\n", __func__, cs, enable);
 190
 191         if (cs >= SPI_NUM_CHIPSELECTS)
 192                 return -ENODEV;
 193
 194         if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
 195                 return -EINVAL;
 196
 197         if (priv->cs_high)
 198                 enable = !enable;
 199
 200         return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
 201 }
 202
 203 /*
 204  * Function to write data to OUTPUT FIFO
 205  */
 206 static void qup_spi_write_byte(struct udevice *dev, unsigned char data)
 207 {
 208         struct udevice *bus = dev_get_parent(dev);
 209         struct qup_spi_priv *priv = dev_get_priv(bus);
 210         /* Wait for space in the FIFO */
 211         while ((readl(priv->base + QUP_OPERATIONAL) & QUP_OP_OUT_FIFO_FULL))
 212                 udelay(1);
 213
 214         /* Write the byte of data */
 215         writel(data, priv->base + QUP_OUTPUT_FIFO);
 216 }
 217
 218 /*
 219  * Function to read data from Input FIFO
 220  */
 221 static unsigned char qup_spi_read_byte(struct udevice *dev)
 222 {
 223         struct udevice *bus = dev_get_parent(dev);
 224         struct qup_spi_priv *priv = dev_get_priv(bus);
 225         /* Wait for Data in FIFO */
 226         while (!(readl(priv->base + QUP_OPERATIONAL) & QUP_DATA_AVAILABLE_FOR_READ)) {
 227                 printf("Stuck at FIFO data wait\n");
 228                 udelay(1);
 229         }
 230
 231         /* Read a byte of data */
 232         return readl(priv->base + QUP_INPUT_FIFO) & 0xff;
 233 }
 234
 235 /*
 236  * Function to check wheather Input or Output FIFO
 237  * has data to be serviced
 238  */
 239 static int qup_spi_check_fifo_status(struct udevice *dev, u32 reg_addr)
 240 {
 241         struct udevice *bus = dev_get_parent(dev);
 242         struct qup_spi_priv *priv = dev_get_priv(bus);
 243         unsigned int count = TIMEOUT_CNT;
 244         unsigned int status_flag;
 245         unsigned int val;
 246
 247         do {
 248                 val = readl(priv->base + reg_addr);
 249                 count--;
 250                 if (count == 0)
 251                         return -ETIMEDOUT;
 252
 253                 status_flag = ((val & QUP_OP_OUT_SERVICE_FLAG) | (val & QUP_OP_IN_SERVICE_FLAG));
 254         } while (!status_flag);
 255
 256         return 0;
 257 }
 258
 259 /*
 260  * Function to configure Input and Output enable/disable
 261  */
 262 static void qup_spi_enable_io_config(struct udevice *dev, u32 write_cnt, u32 read_cnt)
 263 {
 264         struct udevice *bus = dev_get_parent(dev);
 265         struct qup_spi_priv *priv = dev_get_priv(bus);
 266
 267         if (write_cnt) {
 268                 clrsetbits_le32(priv->base + QUP_CONFIG,
 269                                 QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA);
 270         } else {
 271                 clrsetbits_le32(priv->base + QUP_CONFIG,
 272                                 QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT);
 273         }
 274
 275         if (read_cnt) {
 276                 clrsetbits_le32(priv->base + QUP_CONFIG,
 277                                 QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA);
 278         } else {
 279                 clrsetbits_le32(priv->base + QUP_CONFIG,
 280                                 QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT);
 281         }
 282 }
 283
 284 static int check_bit_state(struct udevice *dev, u32 reg_addr, int bit_num, int val,
 285                                                    int us_delay)
 286 {
 287         struct udevice *bus = dev_get_parent(dev);
 288         struct qup_spi_priv *priv = dev_get_priv(bus);
 289         unsigned int count = TIMEOUT_CNT;
 290         unsigned int bit_val = ((readl(priv->base + reg_addr) >> bit_num) & 0x01);
 291
 292         while (bit_val != val) {
 293                 count--;
 294                 if (count == 0)
 295                         return -ETIMEDOUT;
 296                 udelay(us_delay);
 297                 bit_val = ((readl(priv->base + reg_addr) >> bit_num) & 0x01);
 298         }
 299
 300         return 0;
 301 }
 302
 303 /*
 304  * Check whether QUPn State is valid
 305  */
 306 static int check_qup_state_valid(struct udevice *dev)
 307 {
 308         return check_bit_state(dev, QUP_STATE, QUP_STATE_VALID, 1, 1);
 309 }
 310
 311 /*
 312  * Configure QUPn Core state
 313  */
 314 static int qup_spi_config_spi_state(struct udevice *dev, unsigned int state)
 315 {
 316         struct udevice *bus = dev_get_parent(dev);
 317         struct qup_spi_priv *priv = dev_get_priv(bus);
 318         u32 val;
 319         int ret;
 320
 321         ret = check_qup_state_valid(dev);
 322         if (ret != 0)
 323                 return ret;
 324
 325         switch (state) {
 326         case SPI_RUN_STATE:
 327                 /* Set the state to RUN */
 328                 val = ((readl(priv->base + QUP_STATE) & ~QUP_STATE_MASK)
 329                                         | QUP_STATE_RUN);
 330                 writel(val, priv->base + QUP_STATE);
 331                 ret = check_qup_state_valid(dev);
 332                 if (ret != 0)
 333                         return ret;
 334                 priv->core_state = SPI_CORE_RUNNING;
 335                 break;
 336         case SPI_RESET_STATE:
 337                 /* Set the state to RESET */
 338                 val = ((readl(priv->base + QUP_STATE) & ~QUP_STATE_MASK)
 339                                         | QUP_STATE_RESET);
 340                 writel(val, priv->base + QUP_STATE);
 341                 ret = check_qup_state_valid(dev);
 342                 if (ret != 0)
 343                         return ret;
 344                 priv->core_state = SPI_CORE_RESET;
 345                 break;
 346         default:
 347                 printf("Unsupported QUP SPI state: %d\n", state);
 348                 ret = -EINVAL;
 349                 break;
 350         }
 351         return ret;
 352 }
 353
 354 /*
 355  * Function to read bytes number of data from the Input FIFO
 356  */
 357 static int __qup_spi_blsp_spi_read(struct udevice *dev, u8 *data_buffer, unsigned int bytes)
 358 {
 359         struct udevice *bus = dev_get_parent(dev);
 360         struct qup_spi_priv *priv = dev_get_priv(bus);
 361         u32 val;
 362         unsigned int i;
 363         unsigned int read_bytes = bytes;
 364         unsigned int fifo_count;
 365         int ret = 0;
 366         int state_config;
 367
 368         /* Configure no of bytes to read */
 369         state_config = qup_spi_config_spi_state(dev, SPI_RESET_STATE);
 370         if (state_config)
 371                 return state_config;
 372
 373         /* Configure input and output enable */
 374         qup_spi_enable_io_config(dev, 0, read_bytes);
 375
 376         writel(bytes, priv->base + QUP_MX_INPUT_CNT);
 377
 378         state_config = qup_spi_config_spi_state(dev, SPI_RUN_STATE);
 379         if (state_config)
 380                 return state_config;
 381
 382         while (read_bytes) {
 383                 ret = qup_spi_check_fifo_status(dev, QUP_OPERATIONAL);
 384                 if (ret != 0)
 385                         goto out;
 386
 387                 val = readl(priv->base + QUP_OPERATIONAL);
 388                 if (val & QUP_OP_IN_SERVICE_FLAG) {
 389                         /*
 390                          * acknowledge to hw that software will
 391                          * read input data
 392                          */
 393                         val &= QUP_OP_IN_SERVICE_FLAG;
 394                         writel(val, priv->base + QUP_OPERATIONAL);
 395
 396                         fifo_count = ((read_bytes > SPI_INPUT_BLOCK_SIZE) ?
 397                                         SPI_INPUT_BLOCK_SIZE : read_bytes);
 398
 399                         for (i = 0; i < fifo_count; i++) {
 400                                 *data_buffer = qup_spi_read_byte(dev);
 401                                 data_buffer++;
 402                                 read_bytes--;
 403                         }
 404                 }
 405         }
 406
 407 out:
 408         /*
 409          * Put the SPI Core back in the Reset State
 410          * to end the transfer
 411          */
 412         (void)qup_spi_config_spi_state(dev, SPI_RESET_STATE);
 413
 414         return ret;
 415 }
 416
 417 static int qup_spi_blsp_spi_read(struct udevice *dev, u8 *data_buffer, unsigned int bytes)
 418 {
 419         int length, ret;
 420
 421         while (bytes) {
 422                 length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE;
 423
 424                 ret = __qup_spi_blsp_spi_read(dev, data_buffer, length);
 425                 if (ret != 0)
 426                         return ret;
 427
 428                 data_buffer += length;
 429                 bytes -= length;
 430         }
 431
 432         return 0;
 433 }
 434
 435 /*
 436  * Function to write data to the Output FIFO
 437  */
 438 static int __qup_blsp_spi_write(struct udevice *dev, const u8 *cmd_buffer, unsigned int bytes)
 439 {
 440         struct udevice *bus = dev_get_parent(dev);
 441         struct qup_spi_priv *priv = dev_get_priv(bus);
 442         u32 val;
 443         unsigned int i;
 444         unsigned int write_len = bytes;
 445         unsigned int read_len = bytes;
 446         unsigned int fifo_count;
 447         int ret = 0;
 448         int state_config;
 449
 450         state_config = qup_spi_config_spi_state(dev, SPI_RESET_STATE);
 451         if (state_config)
 452                 return state_config;
 453
 454         writel(bytes, priv->base + QUP_MX_OUTPUT_CNT);
 455         writel(bytes, priv->base + QUP_MX_INPUT_CNT);
 456         state_config = qup_spi_config_spi_state(dev, SPI_RUN_STATE);
 457         if (state_config)
 458                 return state_config;
 459
 460         /* Configure input and output enable */
 461         qup_spi_enable_io_config(dev, write_len, read_len);
 462
 463         /*
 464          * read_len considered to ensure that we read the dummy data for the
 465          * write we performed. This is needed to ensure with WR-RD transaction
 466          * to get the actual data on the subsequent read cycle that happens
 467          */
 468         while (write_len || read_len) {
 469                 ret = qup_spi_check_fifo_status(dev, QUP_OPERATIONAL);
 470                 if (ret != 0)
 471                         goto out;
 472
 473                 val = readl(priv->base + QUP_OPERATIONAL);
 474                 if (val & QUP_OP_OUT_SERVICE_FLAG) {
 475                         /*
 476                          * acknowledge to hw that software will write
 477                          * expected output data
 478                          */
 479                         val &= QUP_OP_OUT_SERVICE_FLAG;
 480                         writel(val, priv->base + QUP_OPERATIONAL);
 481
 482                         if (write_len > SPI_OUTPUT_BLOCK_SIZE)
 483                                 fifo_count = SPI_OUTPUT_BLOCK_SIZE;
 484                         else
 485                                 fifo_count = write_len;
 486
 487                         for (i = 0; i < fifo_count; i++) {
 488                                 /* Write actual data to output FIFO */
 489                                 qup_spi_write_byte(dev, *cmd_buffer);
 490                                 cmd_buffer++;
 491                                 write_len--;
 492                         }
 493                 }
 494                 if (val & QUP_OP_IN_SERVICE_FLAG) {
 495                         /*
 496                          * acknowledge to hw that software
 497                          * will read input data
 498                          */
 499                         val &= QUP_OP_IN_SERVICE_FLAG;
 500                         writel(val, priv->base + QUP_OPERATIONAL);
 501
 502                         if (read_len > SPI_INPUT_BLOCK_SIZE)
 503                                 fifo_count = SPI_INPUT_BLOCK_SIZE;
 504                         else
 505                                 fifo_count = read_len;
 506
 507                         for (i = 0; i < fifo_count; i++) {
 508                                 /* Read dummy data for the data written */
 509                                 (void)qup_spi_read_byte(dev);
 510
 511                                 /* Decrement the write count after reading the
 512                                  * dummy data from the device. This is to make
 513                                  * sure we read dummy data before we write the
 514                                  * data to fifo
 515                                  */
 516                                 read_len--;
 517                         }
 518                 }
 519         }
 520 out:
 521         /*
 522          * Put the SPI Core back in the Reset State
 523          * to end the transfer
 524          */
 525         (void)qup_spi_config_spi_state(dev, SPI_RESET_STATE);
 526
 527         return ret;
 528 }
 529
 530 static int qup_spi_blsp_spi_write(struct udevice *dev, const u8 *cmd_buffer, unsigned int bytes)
 531 {
 532         int length, ret;
 533
 534         while (bytes) {
 535                 length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE;
 536
 537                 ret = __qup_blsp_spi_write(dev, cmd_buffer, length);
 538                 if (ret != 0)
 539                         return ret;
 540
 541                 cmd_buffer += length;
 542                 bytes -= length;
 543         }
 544
 545         return 0;
 546 }
 547
 548 static int qup_spi_set_speed(struct udevice *dev, uint speed)
 549 {
 550         return 0;
 551 }
 552
 553 static int qup_spi_set_mode(struct udevice *dev, uint mode)
 554 {
 555         struct qup_spi_priv *priv = dev_get_priv(dev);
 556         unsigned int clk_idle_state;
 557         unsigned int input_first_mode;
 558         u32 val;
 559
 560         switch (mode) {
 561         case SPI_MODE_0:
 562                 clk_idle_state = 0;
 563                 input_first_mode = SPI_CONFIG_INPUT_FIRST;
 564                 break;
 565         case SPI_MODE_1:
 566                 clk_idle_state = 0;
 567                 input_first_mode = 0;
 568                 break;
 569         case SPI_MODE_2:
 570                 clk_idle_state = 1;
 571                 input_first_mode = SPI_CONFIG_INPUT_FIRST;
 572                 break;
 573         case SPI_MODE_3:
 574                 clk_idle_state = 1;
 575                 input_first_mode = 0;
 576                 break;
 577         default:
 578                 printf("Unsupported spi mode: %d\n", mode);
 579                 return -EINVAL;
 580         }
 581
 582         if (mode & SPI_CS_HIGH)
 583                 priv->cs_high = true;
 584         else
 585                 priv->cs_high = false;
 586
 587         val = readl(priv->base + SPI_CONFIG);
 588         val |= input_first_mode;
 589         writel(val, priv->base + SPI_CONFIG);
 590
 591         val = readl(priv->base + SPI_IO_CONTROL);
 592         if (clk_idle_state)
 593                 val |= SPI_IO_C_CLK_IDLE_HIGH;
 594         else
 595                 val &= ~SPI_IO_C_CLK_IDLE_HIGH;
 596
 597         writel(val, priv->base + SPI_IO_CONTROL);
 598
 599         return 0;
 600 }
 601
 602 static void qup_spi_reset(struct udevice *dev)
 603 {
 604         struct udevice *bus = dev_get_parent(dev);
 605         struct qup_spi_priv *priv = dev_get_priv(bus);
 606
 607         /* Driver may not be probed yet */
 608         if (!priv)
 609                 return;
 610
 611         writel(0x1, priv->base + QUP_SW_RESET);
 612         udelay(5);
 613 }
 614
 615 static int qup_spi_hw_init(struct udevice *dev)
 616 {
 617         struct udevice *bus = dev_get_parent(dev);
 618         struct qup_spi_priv *priv = dev_get_priv(bus);
 619         int ret;
 620
 621         /* QUPn module configuration */
 622         qup_spi_reset(dev);
 623
 624         /* Set the QUPn state */
 625         ret = qup_spi_config_spi_state(dev, SPI_RESET_STATE);
 626         if (ret)
 627                 return ret;
 628
 629         /*
 630          * Configure Mini core to SPI core with Input Output enabled,
 631          * SPI master, N = 8 bits
 632          */
 633         clrsetbits_le32(priv->base + QUP_CONFIG, (QUP_CONFIG_MINI_CORE_MSK |
 634                                                 QUP_CONF_INPUT_MSK |
 635                                                 QUP_CONF_OUTPUT_MSK |
 636                                                 SPI_BIT_WORD_MSK),
 637                                                 (QUP_CONFIG_MINI_CORE_SPI |
 638                                                 QUP_CONF_INPUT_ENA |
 639                                                 QUP_CONF_OUTPUT_ENA |
 640                                                 SPI_8_BIT_WORD));
 641
 642         /*
 643          * Configure Input first SPI protocol,
 644          * SPI master mode and no loopback
 645          */
 646         clrsetbits_le32(priv->base + SPI_CONFIG, (LOOP_BACK_MSK |
 647                                                 SLAVE_OPERATION_MSK),
 648                                                 (NO_LOOP_BACK |
 649                                                 SLAVE_OPERATION));
 650
 651         /*
 652          * Configure SPI IO Control Register
 653          * CLK_ALWAYS_ON = 0
 654          * MX_CS_MODE = 0
 655          * NO_TRI_STATE = 1
 656          */
 657         writel((CLK_ALWAYS_ON | NO_TRI_STATE), priv->base + SPI_IO_CONTROL);
 658
 659         /*
 660          * Configure SPI IO Modes.
 661          * OUTPUT_BIT_SHIFT_EN = 1
 662          * INPUT_MODE = Block Mode
 663          * OUTPUT MODE = Block Mode
 664          */
 665
 666         clrsetbits_le32(priv->base + QUP_IO_M_MODES, (OUTPUT_BIT_SHIFT_MSK |
 667                                 INPUT_BLOCK_MODE_MSK |
 668                                 OUTPUT_BLOCK_MODE_MSK),
 669                                 (OUTPUT_BIT_SHIFT_EN |
 670                                 INPUT_BLOCK_MODE |
 671                                 OUTPUT_BLOCK_MODE));
 672
 673         /* Disable Error mask */
 674         writel(0, priv->base + SPI_ERROR_FLAGS_EN);
 675         writel(0, priv->base + QUP_ERROR_FLAGS_EN);
 676         writel(0, priv->base + BLSP0_SPI_DEASSERT_WAIT_REG);
 677
 678         return ret;
 679 }
 680
 681 static int qup_spi_claim_bus(struct udevice *dev)
 682 {
 683         int ret;
 684
 685         ret = qup_spi_hw_init(dev);
 686         if (ret)
 687                 return -EIO;
 688
 689         return 0;
 690 }
 691
 692 static int qup_spi_release_bus(struct udevice *dev)
 693 {
 694         /* Reset the SPI hardware */
 695         qup_spi_reset(dev);
 696
 697         return 0;
 698 }
 699
 700 static int qup_spi_xfer(struct udevice *dev, unsigned int bitlen,
 701                                                 const void *dout, void *din, unsigned long flags)
 702 {
 703         struct udevice *bus = dev_get_parent(dev);
 704         struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 705         unsigned int len;
 706         const u8 *txp = dout;
 707         u8 *rxp = din;
 708         int ret = 0;
 709
 710         if (bitlen & SPI_BITLEN_MSK) {
 711                 printf("Invalid bit length\n");
 712                 return -EINVAL;
 713         }
 714
 715         len = bitlen >> 3;
 716
 717         if (flags & SPI_XFER_BEGIN) {
 718                 ret = qup_spi_hw_init(dev);
 719                 if (ret != 0)
 720                         return ret;
 721
 722                 ret = qup_spi_set_cs(bus, slave_plat->cs, false);
 723                 if (ret != 0)
 724                         return ret;
 725         }
 726
 727         if (dout != NULL) {
 728                 ret = qup_spi_blsp_spi_write(dev, txp, len);
 729                 if (ret != 0)
 730                         return ret;
 731         }
 732
 733         if (din != NULL) {
 734                 ret = qup_spi_blsp_spi_read(dev, rxp, len);
 735                 if (ret != 0)
 736                         return ret;
 737         }
 738
 739         if (flags & SPI_XFER_END) {
 740                 ret = qup_spi_set_cs(bus, slave_plat->cs, true);
 741                 if (ret != 0)
 742                         return ret;
 743         }
 744
 745         return ret;
 746 }
 747
 748 static int qup_spi_probe(struct udevice *dev)
 749 {
 750         struct qup_spi_priv *priv = dev_get_priv(dev);
 751         int ret;
 752
 753         priv->base = dev_read_addr(dev);
 754         if (priv->base == FDT_ADDR_T_NONE)
 755                 return -EINVAL;
 756
 757         ret = clk_get_by_index(dev, 0, &priv->clk);
 758         if (ret)
 759                 return ret;
 760
 761         ret = clk_enable(&priv->clk);
 762         if (ret < 0)
 763                 return ret;
 764
 765         priv->num_cs = dev_read_u32_default(dev, "num-cs", 1);
 766
 767         ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
 768                                         priv->num_cs, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 769         if (ret < 0) {
 770                 printf("Can't get %s cs gpios: %d\n", dev->name, ret);
 771                 return -EINVAL;
 772         }
 773
 774         return 0;
 775 }
 776
 777 static const struct dm_spi_ops qup_spi_ops = {
 778         .claim_bus      = qup_spi_claim_bus,
 779         .release_bus    = qup_spi_release_bus,
 780         .xfer           = qup_spi_xfer,
 781         .set_speed      = qup_spi_set_speed,
 782         .set_mode       = qup_spi_set_mode,
 783         /*
 784          * cs_info is not needed, since we require all chip selects to be
 785          * in the device tree explicitly
 786          */
 787 };
 788
 789 static const struct udevice_id qup_spi_ids[] = {
 790         { .compatible = "qcom,spi-qup-v1.1.1", },
 791         { .compatible = "qcom,spi-qup-v2.1.1", },
 792         { .compatible = "qcom,spi-qup-v2.2.1", },
 793         { }
 794 };
 795
 796 U_BOOT_DRIVER(spi_qup) = {
 797         .name   = "spi_qup",
 798         .id     = UCLASS_SPI,
 799         .of_match = qup_spi_ids,
 800         .ops    = &qup_spi_ops,
 801         .priv_auto      = sizeof(struct qup_spi_priv),
 802         .probe  = qup_spi_probe,
 803 };