drivers/spi/spi-qup.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2008-2014, The Linux foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/delay.h>
   8 #include <linux/err.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/io.h>
  11 #include <linux/list.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/dmaengine.h>
  18 #include <linux/dma-mapping.h>
  19
  20 #define QUP_CONFIG                      0x0000
  21 #define QUP_STATE                       0x0004
  22 #define QUP_IO_M_MODES                  0x0008
  23 #define QUP_SW_RESET                    0x000c
  24 #define QUP_OPERATIONAL                 0x0018
  25 #define QUP_ERROR_FLAGS                 0x001c
  26 #define QUP_ERROR_FLAGS_EN              0x0020
  27 #define QUP_OPERATIONAL_MASK            0x0028
  28 #define QUP_HW_VERSION                  0x0030
  29 #define QUP_MX_OUTPUT_CNT               0x0100
  30 #define QUP_OUTPUT_FIFO                 0x0110
  31 #define QUP_MX_WRITE_CNT                0x0150
  32 #define QUP_MX_INPUT_CNT                0x0200
  33 #define QUP_MX_READ_CNT                 0x0208
  34 #define QUP_INPUT_FIFO                  0x0218
  35
  36 #define SPI_CONFIG                      0x0300
  37 #define SPI_IO_CONTROL                  0x0304
  38 #define SPI_ERROR_FLAGS                 0x0308
  39 #define SPI_ERROR_FLAGS_EN              0x030c
  40
  41 /* QUP_CONFIG fields */
  42 #define QUP_CONFIG_SPI_MODE             (1 << 8)
  43 #define QUP_CONFIG_CLOCK_AUTO_GATE      BIT(13)
  44 #define QUP_CONFIG_NO_INPUT             BIT(7)
  45 #define QUP_CONFIG_NO_OUTPUT            BIT(6)
  46 #define QUP_CONFIG_N                    0x001f
  47
  48 /* QUP_STATE fields */
  49 #define QUP_STATE_VALID                 BIT(2)
  50 #define QUP_STATE_RESET                 0
  51 #define QUP_STATE_RUN                   1
  52 #define QUP_STATE_PAUSE                 3
  53 #define QUP_STATE_MASK                  3
  54 #define QUP_STATE_CLEAR                 2
  55
  56 #define QUP_HW_VERSION_2_1_1            0x20010001
  57
  58 /* QUP_IO_M_MODES fields */
  59 #define QUP_IO_M_PACK_EN                BIT(15)
  60 #define QUP_IO_M_UNPACK_EN              BIT(14)
  61 #define QUP_IO_M_INPUT_MODE_MASK_SHIFT  12
  62 #define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT 10
  63 #define QUP_IO_M_INPUT_MODE_MASK        (3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT)
  64 #define QUP_IO_M_OUTPUT_MODE_MASK       (3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT)
  65
  66 #define QUP_IO_M_OUTPUT_BLOCK_SIZE(x)   (((x) & (0x03 << 0)) >> 0)
  67 #define QUP_IO_M_OUTPUT_FIFO_SIZE(x)    (((x) & (0x07 << 2)) >> 2)
  68 #define QUP_IO_M_INPUT_BLOCK_SIZE(x)    (((x) & (0x03 << 5)) >> 5)
  69 #define QUP_IO_M_INPUT_FIFO_SIZE(x)     (((x) & (0x07 << 7)) >> 7)
  70
  71 #define QUP_IO_M_MODE_FIFO              0
  72 #define QUP_IO_M_MODE_BLOCK             1
  73 #define QUP_IO_M_MODE_DMOV              2
  74 #define QUP_IO_M_MODE_BAM               3
  75
  76 /* QUP_OPERATIONAL fields */
  77 #define QUP_OP_IN_BLOCK_READ_REQ        BIT(13)
  78 #define QUP_OP_OUT_BLOCK_WRITE_REQ      BIT(12)
  79 #define QUP_OP_MAX_INPUT_DONE_FLAG      BIT(11)
  80 #define QUP_OP_MAX_OUTPUT_DONE_FLAG     BIT(10)
  81 #define QUP_OP_IN_SERVICE_FLAG          BIT(9)
  82 #define QUP_OP_OUT_SERVICE_FLAG         BIT(8)
  83 #define QUP_OP_IN_FIFO_FULL             BIT(7)
  84 #define QUP_OP_OUT_FIFO_FULL            BIT(6)
  85 #define QUP_OP_IN_FIFO_NOT_EMPTY        BIT(5)
  86 #define QUP_OP_OUT_FIFO_NOT_EMPTY       BIT(4)
  87
  88 /* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */
  89 #define QUP_ERROR_OUTPUT_OVER_RUN       BIT(5)
  90 #define QUP_ERROR_INPUT_UNDER_RUN       BIT(4)
  91 #define QUP_ERROR_OUTPUT_UNDER_RUN      BIT(3)
  92 #define QUP_ERROR_INPUT_OVER_RUN        BIT(2)
  93
  94 /* SPI_CONFIG fields */
  95 #define SPI_CONFIG_HS_MODE              BIT(10)
  96 #define SPI_CONFIG_INPUT_FIRST          BIT(9)
  97 #define SPI_CONFIG_LOOPBACK             BIT(8)
  98
  99 /* SPI_IO_CONTROL fields */
 100 #define SPI_IO_C_FORCE_CS               BIT(11)
 101 #define SPI_IO_C_CLK_IDLE_HIGH          BIT(10)
 102 #define SPI_IO_C_MX_CS_MODE             BIT(8)
 103 #define SPI_IO_C_CS_N_POLARITY_0        BIT(4)
 104 #define SPI_IO_C_CS_SELECT(x)           (((x) & 3) << 2)
 105 #define SPI_IO_C_CS_SELECT_MASK         0x000c
 106 #define SPI_IO_C_TRISTATE_CS            BIT(1)
 107 #define SPI_IO_C_NO_TRI_STATE           BIT(0)
 108
 109 /* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */
 110 #define SPI_ERROR_CLK_OVER_RUN          BIT(1)
 111 #define SPI_ERROR_CLK_UNDER_RUN         BIT(0)
 112
 113 #define SPI_NUM_CHIPSELECTS             4
 114
 115 #define SPI_MAX_XFER                    (SZ_64K - 64)
 116
 117 /* high speed mode is when bus rate is greater then 26MHz */
 118 #define SPI_HS_MIN_RATE                 26000000
 119 #define SPI_MAX_RATE                    50000000
 120
 121 #define SPI_DELAY_THRESHOLD             1
 122 #define SPI_DELAY_RETRY                 10
 123
 124 struct spi_qup {
 125         void __iomem            *base;
 126         struct device           *dev;
 127         struct clk              *cclk;  /* core clock */
 128         struct clk              *iclk;  /* interface clock */
 129         int                     irq;
 130         spinlock_t              lock;
 131
 132         int                     in_fifo_sz;
 133         int                     out_fifo_sz;
 134         int                     in_blk_sz;
 135         int                     out_blk_sz;
 136
 137         struct spi_transfer     *xfer;
 138         struct completion       done;
 139         int                     error;
 140         int                     w_size; /* bytes per SPI word */
 141         int                     n_words;
 142         int                     tx_bytes;
 143         int                     rx_bytes;
 144         const u8                *tx_buf;
 145         u8                      *rx_buf;
 146         int                     qup_v1;
 147
 148         int                     mode;
 149         struct dma_slave_config rx_conf;
 150         struct dma_slave_config tx_conf;
 151 };
 152
 153 static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer);
 154
 155 static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag)
 156 {
 157         u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL);
 158
 159         return (opflag & flag) != 0;
 160 }
 161
 162 static inline bool spi_qup_is_dma_xfer(int mode)
 163 {
 164         if (mode == QUP_IO_M_MODE_DMOV || mode == QUP_IO_M_MODE_BAM)
 165                 return true;
 166
 167         return false;
 168 }
 169
 170 /* get's the transaction size length */
 171 static inline unsigned int spi_qup_len(struct spi_qup *controller)
 172 {
 173         return controller->n_words * controller->w_size;
 174 }
 175
 176 static inline bool spi_qup_is_valid_state(struct spi_qup *controller)
 177 {
 178         u32 opstate = readl_relaxed(controller->base + QUP_STATE);
 179
 180         return opstate & QUP_STATE_VALID;
 181 }
 182
 183 static int spi_qup_set_state(struct spi_qup *controller, u32 state)
 184 {
 185         unsigned long loop;
 186         u32 cur_state;
 187
 188         loop = 0;
 189         while (!spi_qup_is_valid_state(controller)) {
 190
 191                 usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2);
 192
 193                 if (++loop > SPI_DELAY_RETRY)
 194                         return -EIO;
 195         }
 196
 197         if (loop)
 198                 dev_dbg(controller->dev, "invalid state for %ld,us %d\n",
 199                         loop, state);
 200
 201         cur_state = readl_relaxed(controller->base + QUP_STATE);
 202         /*
 203          * Per spec: for PAUSE_STATE to RESET_STATE, two writes
 204          * of (b10) are required
 205          */
 206         if (((cur_state & QUP_STATE_MASK) == QUP_STATE_PAUSE) &&
 207             (state == QUP_STATE_RESET)) {
 208                 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
 209                 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
 210         } else {
 211                 cur_state &= ~QUP_STATE_MASK;
 212                 cur_state |= state;
 213                 writel_relaxed(cur_state, controller->base + QUP_STATE);
 214         }
 215
 216         loop = 0;
 217         while (!spi_qup_is_valid_state(controller)) {
 218
 219                 usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2);
 220
 221                 if (++loop > SPI_DELAY_RETRY)
 222                         return -EIO;
 223         }
 224
 225         return 0;
 226 }
 227
 228 static void spi_qup_read_from_fifo(struct spi_qup *controller, u32 num_words)
 229 {
 230         u8 *rx_buf = controller->rx_buf;
 231         int i, shift, num_bytes;
 232         u32 word;
 233
 234         for (; num_words; num_words--) {
 235
 236                 word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
 237
 238                 num_bytes = min_t(int, spi_qup_len(controller) -
 239                                        controller->rx_bytes,
 240                                        controller->w_size);
 241
 242                 if (!rx_buf) {
 243                         controller->rx_bytes += num_bytes;
 244                         continue;
 245                 }
 246
 247                 for (i = 0; i < num_bytes; i++, controller->rx_bytes++) {
 248                         /*
 249                          * The data format depends on bytes per SPI word:
 250                          *  4 bytes: 0x12345678
 251                          *  2 bytes: 0x00001234
 252                          *  1 byte : 0x00000012
 253                          */
 254                         shift = BITS_PER_BYTE;
 255                         shift *= (controller->w_size - i - 1);
 256                         rx_buf[controller->rx_bytes] = word >> shift;
 257                 }
 258         }
 259 }
 260
 261 static void spi_qup_read(struct spi_qup *controller, u32 *opflags)
 262 {
 263         u32 remainder, words_per_block, num_words;
 264         bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
 265
 266         remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->rx_bytes,
 267                                  controller->w_size);
 268         words_per_block = controller->in_blk_sz >> 2;
 269
 270         do {
 271                 /* ACK by clearing service flag */
 272                 writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
 273                                controller->base + QUP_OPERATIONAL);
 274
 275                 if (!remainder)
 276                         goto exit;
 277
 278                 if (is_block_mode) {
 279                         num_words = (remainder > words_per_block) ?
 280                                         words_per_block : remainder;
 281                 } else {
 282                         if (!spi_qup_is_flag_set(controller,
 283                                                  QUP_OP_IN_FIFO_NOT_EMPTY))
 284                                 break;
 285
 286                         num_words = 1;
 287                 }
 288
 289                 /* read up to the maximum transfer size available */
 290                 spi_qup_read_from_fifo(controller, num_words);
 291
 292                 remainder -= num_words;
 293
 294                 /* if block mode, check to see if next block is available */
 295                 if (is_block_mode && !spi_qup_is_flag_set(controller,
 296                                         QUP_OP_IN_BLOCK_READ_REQ))
 297                         break;
 298
 299         } while (remainder);
 300
 301         /*
 302          * Due to extra stickiness of the QUP_OP_IN_SERVICE_FLAG during block
 303          * reads, it has to be cleared again at the very end.  However, be sure
 304          * to refresh opflags value because MAX_INPUT_DONE_FLAG may now be
 305          * present and this is used to determine if transaction is complete
 306          */
 307 exit:
 308         if (!remainder) {
 309                 *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
 310                 if (is_block_mode && *opflags & QUP_OP_MAX_INPUT_DONE_FLAG)
 311                         writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
 312                                        controller->base + QUP_OPERATIONAL);
 313         }
 314 }
 315
 316 static void spi_qup_write_to_fifo(struct spi_qup *controller, u32 num_words)
 317 {
 318         const u8 *tx_buf = controller->tx_buf;
 319         int i, num_bytes;
 320         u32 word, data;
 321
 322         for (; num_words; num_words--) {
 323                 word = 0;
 324
 325                 num_bytes = min_t(int, spi_qup_len(controller) -
 326                                        controller->tx_bytes,
 327                                        controller->w_size);
 328                 if (tx_buf)
 329                         for (i = 0; i < num_bytes; i++) {
 330                                 data = tx_buf[controller->tx_bytes + i];
 331                                 word |= data << (BITS_PER_BYTE * (3 - i));
 332                         }
 333
 334                 controller->tx_bytes += num_bytes;
 335
 336                 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
 337         }
 338 }
 339
 340 static void spi_qup_dma_done(void *data)
 341 {
 342         struct spi_qup *qup = data;
 343
 344         complete(&qup->done);
 345 }
 346
 347 static void spi_qup_write(struct spi_qup *controller)
 348 {
 349         bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
 350         u32 remainder, words_per_block, num_words;
 351
 352         remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->tx_bytes,
 353                                  controller->w_size);
 354         words_per_block = controller->out_blk_sz >> 2;
 355
 356         do {
 357                 /* ACK by clearing service flag */
 358                 writel_relaxed(QUP_OP_OUT_SERVICE_FLAG,
 359                                controller->base + QUP_OPERATIONAL);
 360
 361                 /* make sure the interrupt is valid */
 362                 if (!remainder)
 363                         return;
 364
 365                 if (is_block_mode) {
 366                         num_words = (remainder > words_per_block) ?
 367                                 words_per_block : remainder;
 368                 } else {
 369                         if (spi_qup_is_flag_set(controller,
 370                                                 QUP_OP_OUT_FIFO_FULL))
 371                                 break;
 372
 373                         num_words = 1;
 374                 }
 375
 376                 spi_qup_write_to_fifo(controller, num_words);
 377
 378                 remainder -= num_words;
 379
 380                 /* if block mode, check to see if next block is available */
 381                 if (is_block_mode && !spi_qup_is_flag_set(controller,
 382                                         QUP_OP_OUT_BLOCK_WRITE_REQ))
 383                         break;
 384
 385         } while (remainder);
 386 }
 387
 388 static int spi_qup_prep_sg(struct spi_controller *host, struct scatterlist *sgl,
 389                            unsigned int nents, enum dma_transfer_direction dir,
 390                            dma_async_tx_callback callback)
 391 {
 392         struct spi_qup *qup = spi_controller_get_devdata(host);
 393         unsigned long flags = DMA_PREP_INTERRUPT | DMA_PREP_FENCE;
 394         struct dma_async_tx_descriptor *desc;
 395         struct dma_chan *chan;
 396         dma_cookie_t cookie;
 397
 398         if (dir == DMA_MEM_TO_DEV)
 399                 chan = host->dma_tx;
 400         else
 401                 chan = host->dma_rx;
 402
 403         desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
 404         if (IS_ERR_OR_NULL(desc))
 405                 return desc ? PTR_ERR(desc) : -EINVAL;
 406
 407         desc->callback = callback;
 408         desc->callback_param = qup;
 409
 410         cookie = dmaengine_submit(desc);
 411
 412         return dma_submit_error(cookie);
 413 }
 414
 415 static void spi_qup_dma_terminate(struct spi_controller *host,
 416                                   struct spi_transfer *xfer)
 417 {
 418         if (xfer->tx_buf)
 419                 dmaengine_terminate_all(host->dma_tx);
 420         if (xfer->rx_buf)
 421                 dmaengine_terminate_all(host->dma_rx);
 422 }
 423
 424 static u32 spi_qup_sgl_get_nents_len(struct scatterlist *sgl, u32 max,
 425                                      u32 *nents)
 426 {
 427         struct scatterlist *sg;
 428         u32 total = 0;
 429
 430         for (sg = sgl; sg; sg = sg_next(sg)) {
 431                 unsigned int len = sg_dma_len(sg);
 432
 433                 /* check for overflow as well as limit */
 434                 if (((total + len) < total) || ((total + len) > max))
 435                         break;
 436
 437                 total += len;
 438                 (*nents)++;
 439         }
 440
 441         return total;
 442 }
 443
 444 static int spi_qup_do_dma(struct spi_device *spi, struct spi_transfer *xfer,
 445                           unsigned long timeout)
 446 {
 447         dma_async_tx_callback rx_done = NULL, tx_done = NULL;
 448         struct spi_controller *host = spi->controller;
 449         struct spi_qup *qup = spi_controller_get_devdata(host);
 450         struct scatterlist *tx_sgl, *rx_sgl;
 451         int ret;
 452
 453         if (xfer->rx_buf)
 454                 rx_done = spi_qup_dma_done;
 455         else if (xfer->tx_buf)
 456                 tx_done = spi_qup_dma_done;
 457
 458         rx_sgl = xfer->rx_sg.sgl;
 459         tx_sgl = xfer->tx_sg.sgl;
 460
 461         do {
 462                 u32 rx_nents = 0, tx_nents = 0;
 463
 464                 if (rx_sgl)
 465                         qup->n_words = spi_qup_sgl_get_nents_len(rx_sgl,
 466                                         SPI_MAX_XFER, &rx_nents) / qup->w_size;
 467                 if (tx_sgl)
 468                         qup->n_words = spi_qup_sgl_get_nents_len(tx_sgl,
 469                                         SPI_MAX_XFER, &tx_nents) / qup->w_size;
 470                 if (!qup->n_words)
 471                         return -EIO;
 472
 473                 ret = spi_qup_io_config(spi, xfer);
 474                 if (ret)
 475                         return ret;
 476
 477                 /* before issuing the descriptors, set the QUP to run */
 478                 ret = spi_qup_set_state(qup, QUP_STATE_RUN);
 479                 if (ret) {
 480                         dev_warn(qup->dev, "cannot set RUN state\n");
 481                         return ret;
 482                 }
 483                 if (rx_sgl) {
 484                         ret = spi_qup_prep_sg(host, rx_sgl, rx_nents,
 485                                               DMA_DEV_TO_MEM, rx_done);
 486                         if (ret)
 487                                 return ret;
 488                         dma_async_issue_pending(host->dma_rx);
 489                 }
 490
 491                 if (tx_sgl) {
 492                         ret = spi_qup_prep_sg(host, tx_sgl, tx_nents,
 493                                               DMA_MEM_TO_DEV, tx_done);
 494                         if (ret)
 495                                 return ret;
 496
 497                         dma_async_issue_pending(host->dma_tx);
 498                 }
 499
 500                 if (!wait_for_completion_timeout(&qup->done, timeout))
 501                         return -ETIMEDOUT;
 502
 503                 for (; rx_sgl && rx_nents--; rx_sgl = sg_next(rx_sgl))
 504                         ;
 505                 for (; tx_sgl && tx_nents--; tx_sgl = sg_next(tx_sgl))
 506                         ;
 507
 508         } while (rx_sgl || tx_sgl);
 509
 510         return 0;
 511 }
 512
 513 static int spi_qup_do_pio(struct spi_device *spi, struct spi_transfer *xfer,
 514                           unsigned long timeout)
 515 {
 516         struct spi_controller *host = spi->controller;
 517         struct spi_qup *qup = spi_controller_get_devdata(host);
 518         int ret, n_words, iterations, offset = 0;
 519
 520         n_words = qup->n_words;
 521         iterations = n_words / SPI_MAX_XFER; /* round down */
 522         qup->rx_buf = xfer->rx_buf;
 523         qup->tx_buf = xfer->tx_buf;
 524
 525         do {
 526                 if (iterations)
 527                         qup->n_words = SPI_MAX_XFER;
 528                 else
 529                         qup->n_words = n_words % SPI_MAX_XFER;
 530
 531                 if (qup->tx_buf && offset)
 532                         qup->tx_buf = xfer->tx_buf + offset * SPI_MAX_XFER;
 533
 534                 if (qup->rx_buf && offset)
 535                         qup->rx_buf = xfer->rx_buf + offset * SPI_MAX_XFER;
 536
 537                 /*
 538                  * if the transaction is small enough, we need
 539                  * to fallback to FIFO mode
 540                  */
 541                 if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32)))
 542                         qup->mode = QUP_IO_M_MODE_FIFO;
 543
 544                 ret = spi_qup_io_config(spi, xfer);
 545                 if (ret)
 546                         return ret;
 547
 548                 ret = spi_qup_set_state(qup, QUP_STATE_RUN);
 549                 if (ret) {
 550                         dev_warn(qup->dev, "cannot set RUN state\n");
 551                         return ret;
 552                 }
 553
 554                 ret = spi_qup_set_state(qup, QUP_STATE_PAUSE);
 555                 if (ret) {
 556                         dev_warn(qup->dev, "cannot set PAUSE state\n");
 557                         return ret;
 558                 }
 559
 560                 if (qup->mode == QUP_IO_M_MODE_FIFO)
 561                         spi_qup_write(qup);
 562
 563                 ret = spi_qup_set_state(qup, QUP_STATE_RUN);
 564                 if (ret) {
 565                         dev_warn(qup->dev, "cannot set RUN state\n");
 566                         return ret;
 567                 }
 568
 569                 if (!wait_for_completion_timeout(&qup->done, timeout))
 570                         return -ETIMEDOUT;
 571
 572                 offset++;
 573         } while (iterations--);
 574
 575         return 0;
 576 }
 577
 578 static bool spi_qup_data_pending(struct spi_qup *controller)
 579 {
 580         unsigned int remainder_tx, remainder_rx;
 581
 582         remainder_tx = DIV_ROUND_UP(spi_qup_len(controller) -
 583                                     controller->tx_bytes, controller->w_size);
 584
 585         remainder_rx = DIV_ROUND_UP(spi_qup_len(controller) -
 586                                     controller->rx_bytes, controller->w_size);
 587
 588         return remainder_tx || remainder_rx;
 589 }
 590
 591 static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
 592 {
 593         struct spi_qup *controller = dev_id;
 594         u32 opflags, qup_err, spi_err;
 595         int error = 0;
 596
 597         qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
 598         spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
 599         opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
 600
 601         writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
 602         writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
 603
 604         if (qup_err) {
 605                 if (qup_err & QUP_ERROR_OUTPUT_OVER_RUN)
 606                         dev_warn(controller->dev, "OUTPUT_OVER_RUN\n");
 607                 if (qup_err & QUP_ERROR_INPUT_UNDER_RUN)
 608                         dev_warn(controller->dev, "INPUT_UNDER_RUN\n");
 609                 if (qup_err & QUP_ERROR_OUTPUT_UNDER_RUN)
 610                         dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n");
 611                 if (qup_err & QUP_ERROR_INPUT_OVER_RUN)
 612                         dev_warn(controller->dev, "INPUT_OVER_RUN\n");
 613
 614                 error = -EIO;
 615         }
 616
 617         if (spi_err) {
 618                 if (spi_err & SPI_ERROR_CLK_OVER_RUN)
 619                         dev_warn(controller->dev, "CLK_OVER_RUN\n");
 620                 if (spi_err & SPI_ERROR_CLK_UNDER_RUN)
 621                         dev_warn(controller->dev, "CLK_UNDER_RUN\n");
 622
 623                 error = -EIO;
 624         }
 625
 626         spin_lock(&controller->lock);
 627         if (!controller->error)
 628                 controller->error = error;
 629         spin_unlock(&controller->lock);
 630
 631         if (spi_qup_is_dma_xfer(controller->mode)) {
 632                 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
 633         } else {
 634                 if (opflags & QUP_OP_IN_SERVICE_FLAG)
 635                         spi_qup_read(controller, &opflags);
 636
 637                 if (opflags & QUP_OP_OUT_SERVICE_FLAG)
 638                         spi_qup_write(controller);
 639
 640                 if (!spi_qup_data_pending(controller))
 641                         complete(&controller->done);
 642         }
 643
 644         if (error)
 645                 complete(&controller->done);
 646
 647         if (opflags & QUP_OP_MAX_INPUT_DONE_FLAG) {
 648                 if (!spi_qup_is_dma_xfer(controller->mode)) {
 649                         if (spi_qup_data_pending(controller))
 650                                 return IRQ_HANDLED;
 651                 }
 652                 complete(&controller->done);
 653         }
 654
 655         return IRQ_HANDLED;
 656 }
 657
 658 /* set clock freq ... bits per word, determine mode */
 659 static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer)
 660 {
 661         struct spi_qup *controller = spi_controller_get_devdata(spi->controller);
 662         int ret;
 663
 664         if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
 665                 dev_err(controller->dev, "too big size for loopback %d > %d\n",
 666                         xfer->len, controller->in_fifo_sz);
 667                 return -EIO;
 668         }
 669
 670         ret = clk_set_rate(controller->cclk, xfer->speed_hz);
 671         if (ret) {
 672                 dev_err(controller->dev, "fail to set frequency %d",
 673                         xfer->speed_hz);
 674                 return -EIO;
 675         }
 676
 677         controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8);
 678         controller->n_words = xfer->len / controller->w_size;
 679
 680         if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32)))
 681                 controller->mode = QUP_IO_M_MODE_FIFO;
 682         else if (spi->controller->can_dma &&
 683                  spi->controller->can_dma(spi->controller, spi, xfer) &&
 684                  spi->controller->cur_msg_mapped)
 685                 controller->mode = QUP_IO_M_MODE_BAM;
 686         else
 687                 controller->mode = QUP_IO_M_MODE_BLOCK;
 688
 689         return 0;
 690 }
 691
 692 /* prep qup for another spi transaction of specific type */
 693 static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
 694 {
 695         struct spi_qup *controller = spi_controller_get_devdata(spi->controller);
 696         u32 config, iomode, control;
 697         unsigned long flags;
 698
 699         spin_lock_irqsave(&controller->lock, flags);
 700         controller->xfer     = xfer;
 701         controller->error    = 0;
 702         controller->rx_bytes = 0;
 703         controller->tx_bytes = 0;
 704         spin_unlock_irqrestore(&controller->lock, flags);
 705
 706
 707         if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
 708                 dev_err(controller->dev, "cannot set RESET state\n");
 709                 return -EIO;
 710         }
 711
 712         switch (controller->mode) {
 713         case QUP_IO_M_MODE_FIFO:
 714                 writel_relaxed(controller->n_words,
 715                                controller->base + QUP_MX_READ_CNT);
 716                 writel_relaxed(controller->n_words,
 717                                controller->base + QUP_MX_WRITE_CNT);
 718                 /* must be zero for FIFO */
 719                 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
 720                 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
 721                 break;
 722         case QUP_IO_M_MODE_BAM:
 723                 writel_relaxed(controller->n_words,
 724                                controller->base + QUP_MX_INPUT_CNT);
 725                 writel_relaxed(controller->n_words,
 726                                controller->base + QUP_MX_OUTPUT_CNT);
 727                 /* must be zero for BLOCK and BAM */
 728                 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 729                 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 730
 731                 if (!controller->qup_v1) {
 732                         void __iomem *input_cnt;
 733
 734                         input_cnt = controller->base + QUP_MX_INPUT_CNT;
 735                         /*
 736                          * for DMA transfers, both QUP_MX_INPUT_CNT and
 737                          * QUP_MX_OUTPUT_CNT must be zero to all cases but one.
 738                          * That case is a non-balanced transfer when there is
 739                          * only a rx_buf.
 740                          */
 741                         if (xfer->tx_buf)
 742                                 writel_relaxed(0, input_cnt);
 743                         else
 744                                 writel_relaxed(controller->n_words, input_cnt);
 745
 746                         writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
 747                 }
 748                 break;
 749         case QUP_IO_M_MODE_BLOCK:
 750                 reinit_completion(&controller->done);
 751                 writel_relaxed(controller->n_words,
 752                                controller->base + QUP_MX_INPUT_CNT);
 753                 writel_relaxed(controller->n_words,
 754                                controller->base + QUP_MX_OUTPUT_CNT);
 755                 /* must be zero for BLOCK and BAM */
 756                 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 757                 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 758                 break;
 759         default:
 760                 dev_err(controller->dev, "unknown mode = %d\n",
 761                                 controller->mode);
 762                 return -EIO;
 763         }
 764
 765         iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
 766         /* Set input and output transfer mode */
 767         iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
 768
 769         if (!spi_qup_is_dma_xfer(controller->mode))
 770                 iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
 771         else
 772                 iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN;
 773
 774         iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
 775         iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
 776
 777         writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
 778
 779         control = readl_relaxed(controller->base + SPI_IO_CONTROL);
 780
 781         if (spi->mode & SPI_CPOL)
 782                 control |= SPI_IO_C_CLK_IDLE_HIGH;
 783         else
 784                 control &= ~SPI_IO_C_CLK_IDLE_HIGH;
 785
 786         writel_relaxed(control, controller->base + SPI_IO_CONTROL);
 787
 788         config = readl_relaxed(controller->base + SPI_CONFIG);
 789
 790         if (spi->mode & SPI_LOOP)
 791                 config |= SPI_CONFIG_LOOPBACK;
 792         else
 793                 config &= ~SPI_CONFIG_LOOPBACK;
 794
 795         if (spi->mode & SPI_CPHA)
 796                 config &= ~SPI_CONFIG_INPUT_FIRST;
 797         else
 798                 config |= SPI_CONFIG_INPUT_FIRST;
 799
 800         /*
 801          * HS_MODE improves signal stability for spi-clk high rates,
 802          * but is invalid in loop back mode.
 803          */
 804         if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP))
 805                 config |= SPI_CONFIG_HS_MODE;
 806         else
 807                 config &= ~SPI_CONFIG_HS_MODE;
 808
 809         writel_relaxed(config, controller->base + SPI_CONFIG);
 810
 811         config = readl_relaxed(controller->base + QUP_CONFIG);
 812         config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
 813         config |= xfer->bits_per_word - 1;
 814         config |= QUP_CONFIG_SPI_MODE;
 815
 816         if (spi_qup_is_dma_xfer(controller->mode)) {
 817                 if (!xfer->tx_buf)
 818                         config |= QUP_CONFIG_NO_OUTPUT;
 819                 if (!xfer->rx_buf)
 820                         config |= QUP_CONFIG_NO_INPUT;
 821         }
 822
 823         writel_relaxed(config, controller->base + QUP_CONFIG);
 824
 825         /* only write to OPERATIONAL_MASK when register is present */
 826         if (!controller->qup_v1) {
 827                 u32 mask = 0;
 828
 829                 /*
 830                  * mask INPUT and OUTPUT service flags to prevent IRQs on FIFO
 831                  * status change in BAM mode
 832                  */
 833
 834                 if (spi_qup_is_dma_xfer(controller->mode))
 835                         mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG;
 836
 837                 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
 838         }
 839
 840         return 0;
 841 }
 842
 843 static int spi_qup_transfer_one(struct spi_controller *host,
 844                               struct spi_device *spi,
 845                               struct spi_transfer *xfer)
 846 {
 847         struct spi_qup *controller = spi_controller_get_devdata(host);
 848         unsigned long timeout, flags;
 849         int ret;
 850
 851         ret = spi_qup_io_prep(spi, xfer);
 852         if (ret)
 853                 return ret;
 854
 855         timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC);
 856         timeout = DIV_ROUND_UP(min_t(unsigned long, SPI_MAX_XFER,
 857                                      xfer->len) * 8, timeout);
 858         timeout = 100 * msecs_to_jiffies(timeout);
 859
 860         reinit_completion(&controller->done);
 861
 862         spin_lock_irqsave(&controller->lock, flags);
 863         controller->xfer     = xfer;
 864         controller->error    = 0;
 865         controller->rx_bytes = 0;
 866         controller->tx_bytes = 0;
 867         spin_unlock_irqrestore(&controller->lock, flags);
 868
 869         if (spi_qup_is_dma_xfer(controller->mode))
 870                 ret = spi_qup_do_dma(spi, xfer, timeout);
 871         else
 872                 ret = spi_qup_do_pio(spi, xfer, timeout);
 873
 874         spi_qup_set_state(controller, QUP_STATE_RESET);
 875         spin_lock_irqsave(&controller->lock, flags);
 876         if (!ret)
 877                 ret = controller->error;
 878         spin_unlock_irqrestore(&controller->lock, flags);
 879
 880         if (ret && spi_qup_is_dma_xfer(controller->mode))
 881                 spi_qup_dma_terminate(host, xfer);
 882
 883         return ret;
 884 }
 885
 886 static bool spi_qup_can_dma(struct spi_controller *host, struct spi_device *spi,
 887                             struct spi_transfer *xfer)
 888 {
 889         struct spi_qup *qup = spi_controller_get_devdata(host);
 890         size_t dma_align = dma_get_cache_alignment();
 891         int n_words;
 892
 893         if (xfer->rx_buf) {
 894                 if (!IS_ALIGNED((size_t)xfer->rx_buf, dma_align) ||
 895                     IS_ERR_OR_NULL(host->dma_rx))
 896                         return false;
 897                 if (qup->qup_v1 && (xfer->len % qup->in_blk_sz))
 898                         return false;
 899         }
 900
 901         if (xfer->tx_buf) {
 902                 if (!IS_ALIGNED((size_t)xfer->tx_buf, dma_align) ||
 903                     IS_ERR_OR_NULL(host->dma_tx))
 904                         return false;
 905                 if (qup->qup_v1 && (xfer->len % qup->out_blk_sz))
 906                         return false;
 907         }
 908
 909         n_words = xfer->len / DIV_ROUND_UP(xfer->bits_per_word, 8);
 910         if (n_words <= (qup->in_fifo_sz / sizeof(u32)))
 911                 return false;
 912
 913         return true;
 914 }
 915
 916 static void spi_qup_release_dma(struct spi_controller *host)
 917 {
 918         if (!IS_ERR_OR_NULL(host->dma_rx))
 919                 dma_release_channel(host->dma_rx);
 920         if (!IS_ERR_OR_NULL(host->dma_tx))
 921                 dma_release_channel(host->dma_tx);
 922 }
 923
 924 static int spi_qup_init_dma(struct spi_controller *host, resource_size_t base)
 925 {
 926         struct spi_qup *spi = spi_controller_get_devdata(host);
 927         struct dma_slave_config *rx_conf = &spi->rx_conf,
 928                                 *tx_conf = &spi->tx_conf;
 929         struct device *dev = spi->dev;
 930         int ret;
 931
 932         /* allocate dma resources, if available */
 933         host->dma_rx = dma_request_chan(dev, "rx");
 934         if (IS_ERR(host->dma_rx))
 935                 return PTR_ERR(host->dma_rx);
 936
 937         host->dma_tx = dma_request_chan(dev, "tx");
 938         if (IS_ERR(host->dma_tx)) {
 939                 ret = PTR_ERR(host->dma_tx);
 940                 goto err_tx;
 941         }
 942
 943         /* set DMA parameters */
 944         rx_conf->direction = DMA_DEV_TO_MEM;
 945         rx_conf->device_fc = 1;
 946         rx_conf->src_addr = base + QUP_INPUT_FIFO;
 947         rx_conf->src_maxburst = spi->in_blk_sz;
 948
 949         tx_conf->direction = DMA_MEM_TO_DEV;
 950         tx_conf->device_fc = 1;
 951         tx_conf->dst_addr = base + QUP_OUTPUT_FIFO;
 952         tx_conf->dst_maxburst = spi->out_blk_sz;
 953
 954         ret = dmaengine_slave_config(host->dma_rx, rx_conf);
 955         if (ret) {
 956                 dev_err(dev, "failed to configure RX channel\n");
 957                 goto err;
 958         }
 959
 960         ret = dmaengine_slave_config(host->dma_tx, tx_conf);
 961         if (ret) {
 962                 dev_err(dev, "failed to configure TX channel\n");
 963                 goto err;
 964         }
 965
 966         return 0;
 967
 968 err:
 969         dma_release_channel(host->dma_tx);
 970 err_tx:
 971         dma_release_channel(host->dma_rx);
 972         return ret;
 973 }
 974
 975 static void spi_qup_set_cs(struct spi_device *spi, bool val)
 976 {
 977         struct spi_qup *controller;
 978         u32 spi_ioc;
 979         u32 spi_ioc_orig;
 980
 981         controller = spi_controller_get_devdata(spi->controller);
 982         spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL);
 983         spi_ioc_orig = spi_ioc;
 984         if (!val)
 985                 spi_ioc |= SPI_IO_C_FORCE_CS;
 986         else
 987                 spi_ioc &= ~SPI_IO_C_FORCE_CS;
 988
 989         if (spi_ioc != spi_ioc_orig)
 990                 writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL);
 991 }
 992
 993 static int spi_qup_probe(struct platform_device *pdev)
 994 {
 995         struct spi_controller *host;
 996         struct clk *iclk, *cclk;
 997         struct spi_qup *controller;
 998         struct resource *res;
 999         struct device *dev;
1000         void __iomem *base;
1001         u32 max_freq, iomode, num_cs;
1002         int ret, irq, size;
1003
1004         dev = &pdev->dev;
1005         base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1006         if (IS_ERR(base))
1007                 return PTR_ERR(base);
1008
1009         irq = platform_get_irq(pdev, 0);
1010         if (irq < 0)
1011                 return irq;
1012
1013         cclk = devm_clk_get(dev, "core");
1014         if (IS_ERR(cclk))
1015                 return PTR_ERR(cclk);
1016
1017         iclk = devm_clk_get(dev, "iface");
1018         if (IS_ERR(iclk))
1019                 return PTR_ERR(iclk);
1020
1021         /* This is optional parameter */
1022         if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq))
1023                 max_freq = SPI_MAX_RATE;
1024
1025         if (!max_freq || max_freq > SPI_MAX_RATE) {
1026                 dev_err(dev, "invalid clock frequency %d\n", max_freq);
1027                 return -ENXIO;
1028         }
1029
1030         host = spi_alloc_host(dev, sizeof(struct spi_qup));
1031         if (!host) {
1032                 dev_err(dev, "cannot allocate host\n");
1033                 return -ENOMEM;
1034         }
1035
1036         /* use num-cs unless not present or out of range */
1037         if (of_property_read_u32(dev->of_node, "num-cs", &num_cs) ||
1038             num_cs > SPI_NUM_CHIPSELECTS)
1039                 host->num_chipselect = SPI_NUM_CHIPSELECTS;
1040         else
1041                 host->num_chipselect = num_cs;
1042
1043         host->use_gpio_descriptors = true;
1044         host->max_native_cs = SPI_NUM_CHIPSELECTS;
1045         host->bus_num = pdev->id;
1046         host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1047         host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1048         host->max_speed_hz = max_freq;
1049         host->transfer_one = spi_qup_transfer_one;
1050         host->dev.of_node = pdev->dev.of_node;
1051         host->auto_runtime_pm = true;
1052         host->dma_alignment = dma_get_cache_alignment();
1053         host->max_dma_len = SPI_MAX_XFER;
1054
1055         platform_set_drvdata(pdev, host);
1056
1057         controller = spi_controller_get_devdata(host);
1058
1059         controller->dev = dev;
1060         controller->base = base;
1061         controller->iclk = iclk;
1062         controller->cclk = cclk;
1063         controller->irq = irq;
1064
1065         ret = spi_qup_init_dma(host, res->start);
1066         if (ret == -EPROBE_DEFER)
1067                 goto error;
1068         else if (!ret)
1069                 host->can_dma = spi_qup_can_dma;
1070
1071         controller->qup_v1 = (uintptr_t)of_device_get_match_data(dev);
1072
1073         if (!controller->qup_v1)
1074                 host->set_cs = spi_qup_set_cs;
1075
1076         spin_lock_init(&controller->lock);
1077         init_completion(&controller->done);
1078
1079         ret = clk_prepare_enable(cclk);
1080         if (ret) {
1081                 dev_err(dev, "cannot enable core clock\n");
1082                 goto error_dma;
1083         }
1084
1085         ret = clk_prepare_enable(iclk);
1086         if (ret) {
1087                 clk_disable_unprepare(cclk);
1088                 dev_err(dev, "cannot enable iface clock\n");
1089                 goto error_dma;
1090         }
1091
1092         iomode = readl_relaxed(base + QUP_IO_M_MODES);
1093
1094         size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode);
1095         if (size)
1096                 controller->out_blk_sz = size * 16;
1097         else
1098                 controller->out_blk_sz = 4;
1099
1100         size = QUP_IO_M_INPUT_BLOCK_SIZE(iomode);
1101         if (size)
1102                 controller->in_blk_sz = size * 16;
1103         else
1104                 controller->in_blk_sz = 4;
1105
1106         size = QUP_IO_M_OUTPUT_FIFO_SIZE(iomode);
1107         controller->out_fifo_sz = controller->out_blk_sz * (2 << size);
1108
1109         size = QUP_IO_M_INPUT_FIFO_SIZE(iomode);
1110         controller->in_fifo_sz = controller->in_blk_sz * (2 << size);
1111
1112         dev_info(dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
1113                  controller->in_blk_sz, controller->in_fifo_sz,
1114                  controller->out_blk_sz, controller->out_fifo_sz);
1115
1116         writel_relaxed(1, base + QUP_SW_RESET);
1117
1118         ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1119         if (ret) {
1120                 dev_err(dev, "cannot set RESET state\n");
1121                 goto error_clk;
1122         }
1123
1124         writel_relaxed(0, base + QUP_OPERATIONAL);
1125         writel_relaxed(0, base + QUP_IO_M_MODES);
1126
1127         if (!controller->qup_v1)
1128                 writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
1129
1130         writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN,
1131                        base + SPI_ERROR_FLAGS_EN);
1132
1133         /* if earlier version of the QUP, disable INPUT_OVERRUN */
1134         if (controller->qup_v1)
1135                 writel_relaxed(QUP_ERROR_OUTPUT_OVER_RUN |
1136                         QUP_ERROR_INPUT_UNDER_RUN | QUP_ERROR_OUTPUT_UNDER_RUN,
1137                         base + QUP_ERROR_FLAGS_EN);
1138
1139         writel_relaxed(0, base + SPI_CONFIG);
1140         writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
1141
1142         ret = devm_request_irq(dev, irq, spi_qup_qup_irq,
1143                                IRQF_TRIGGER_HIGH, pdev->name, controller);
1144         if (ret)
1145                 goto error_clk;
1146
1147         pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
1148         pm_runtime_use_autosuspend(dev);
1149         pm_runtime_set_active(dev);
1150         pm_runtime_enable(dev);
1151
1152         ret = devm_spi_register_controller(dev, host);
1153         if (ret)
1154                 goto disable_pm;
1155
1156         return 0;
1157
1158 disable_pm:
1159         pm_runtime_disable(&pdev->dev);
1160 error_clk:
1161         clk_disable_unprepare(cclk);
1162         clk_disable_unprepare(iclk);
1163 error_dma:
1164         spi_qup_release_dma(host);
1165 error:
1166         spi_controller_put(host);
1167         return ret;
1168 }
1169
1170 #ifdef CONFIG_PM
1171 static int spi_qup_pm_suspend_runtime(struct device *device)
1172 {
1173         struct spi_controller *host = dev_get_drvdata(device);
1174         struct spi_qup *controller = spi_controller_get_devdata(host);
1175         u32 config;
1176
1177         /* Enable clocks auto gaiting */
1178         config = readl(controller->base + QUP_CONFIG);
1179         config |= QUP_CONFIG_CLOCK_AUTO_GATE;
1180         writel_relaxed(config, controller->base + QUP_CONFIG);
1181
1182         clk_disable_unprepare(controller->cclk);
1183         clk_disable_unprepare(controller->iclk);
1184
1185         return 0;
1186 }
1187
1188 static int spi_qup_pm_resume_runtime(struct device *device)
1189 {
1190         struct spi_controller *host = dev_get_drvdata(device);
1191         struct spi_qup *controller = spi_controller_get_devdata(host);
1192         u32 config;
1193         int ret;
1194
1195         ret = clk_prepare_enable(controller->iclk);
1196         if (ret)
1197                 return ret;
1198
1199         ret = clk_prepare_enable(controller->cclk);
1200         if (ret) {
1201                 clk_disable_unprepare(controller->iclk);
1202                 return ret;
1203         }
1204
1205         /* Disable clocks auto gaiting */
1206         config = readl_relaxed(controller->base + QUP_CONFIG);
1207         config &= ~QUP_CONFIG_CLOCK_AUTO_GATE;
1208         writel_relaxed(config, controller->base + QUP_CONFIG);
1209         return 0;
1210 }
1211 #endif /* CONFIG_PM */
1212
1213 #ifdef CONFIG_PM_SLEEP
1214 static int spi_qup_suspend(struct device *device)
1215 {
1216         struct spi_controller *host = dev_get_drvdata(device);
1217         struct spi_qup *controller = spi_controller_get_devdata(host);
1218         int ret;
1219
1220         if (pm_runtime_suspended(device)) {
1221                 ret = spi_qup_pm_resume_runtime(device);
1222                 if (ret)
1223                         return ret;
1224         }
1225         ret = spi_controller_suspend(host);
1226         if (ret)
1227                 return ret;
1228
1229         ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1230         if (ret)
1231                 return ret;
1232
1233         clk_disable_unprepare(controller->cclk);
1234         clk_disable_unprepare(controller->iclk);
1235         return 0;
1236 }
1237
1238 static int spi_qup_resume(struct device *device)
1239 {
1240         struct spi_controller *host = dev_get_drvdata(device);
1241         struct spi_qup *controller = spi_controller_get_devdata(host);
1242         int ret;
1243
1244         ret = clk_prepare_enable(controller->iclk);
1245         if (ret)
1246                 return ret;
1247
1248         ret = clk_prepare_enable(controller->cclk);
1249         if (ret) {
1250                 clk_disable_unprepare(controller->iclk);
1251                 return ret;
1252         }
1253
1254         ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1255         if (ret)
1256                 goto disable_clk;
1257
1258         ret = spi_controller_resume(host);
1259         if (ret)
1260                 goto disable_clk;
1261
1262         return 0;
1263
1264 disable_clk:
1265         clk_disable_unprepare(controller->cclk);
1266         clk_disable_unprepare(controller->iclk);
1267         return ret;
1268 }
1269 #endif /* CONFIG_PM_SLEEP */
1270
1271 static void spi_qup_remove(struct platform_device *pdev)
1272 {
1273         struct spi_controller *host = dev_get_drvdata(&pdev->dev);
1274         struct spi_qup *controller = spi_controller_get_devdata(host);
1275         int ret;
1276
1277         ret = pm_runtime_get_sync(&pdev->dev);
1278
1279         if (ret >= 0) {
1280                 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1281                 if (ret)
1282                         dev_warn(&pdev->dev, "failed to reset controller (%pe)\n",
1283                                  ERR_PTR(ret));
1284
1285                 clk_disable_unprepare(controller->cclk);
1286                 clk_disable_unprepare(controller->iclk);
1287         } else {
1288                 dev_warn(&pdev->dev, "failed to resume, skip hw disable (%pe)\n",
1289                          ERR_PTR(ret));
1290         }
1291
1292         spi_qup_release_dma(host);
1293
1294         pm_runtime_put_noidle(&pdev->dev);
1295         pm_runtime_disable(&pdev->dev);
1296 }
1297
1298 static const struct of_device_id spi_qup_dt_match[] = {
1299         { .compatible = "qcom,spi-qup-v1.1.1", .data = (void *)1, },
1300         { .compatible = "qcom,spi-qup-v2.1.1", },
1301         { .compatible = "qcom,spi-qup-v2.2.1", },
1302         { }
1303 };
1304 MODULE_DEVICE_TABLE(of, spi_qup_dt_match);
1305
1306 static const struct dev_pm_ops spi_qup_dev_pm_ops = {
1307         SET_SYSTEM_SLEEP_PM_OPS(spi_qup_suspend, spi_qup_resume)
1308         SET_RUNTIME_PM_OPS(spi_qup_pm_suspend_runtime,
1309                            spi_qup_pm_resume_runtime,
1310                            NULL)
1311 };
1312
1313 static struct platform_driver spi_qup_driver = {
1314         .driver = {
1315                 .name           = "spi_qup",
1316                 .pm             = &spi_qup_dev_pm_ops,
1317                 .of_match_table = spi_qup_dt_match,
1318         },
1319         .probe = spi_qup_probe,
1320         .remove_new = spi_qup_remove,
1321 };
1322 module_platform_driver(spi_qup_driver);
1323
1324 MODULE_LICENSE("GPL v2");
1325 MODULE_ALIAS("platform:spi_qup");