2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/device.h>
19 #include <linux/ioport.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/pci.h>
25 #include <linux/platform_device.h>
26 #include <linux/spi/pxa2xx_spi.h>
27 #include <linux/spi/spi.h>
28 #include <linux/delay.h>
29 #include <linux/gpio.h>
30 #include <linux/slab.h>
31 #include <linux/clk.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/acpi.h>
35 #include "spi-pxa2xx.h"
37 MODULE_AUTHOR("Stephen Street");
38 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
39 MODULE_LICENSE("GPL");
40 MODULE_ALIAS("platform:pxa2xx-spi");
42 #define TIMOUT_DFLT 1000
45 * for testing SSCR1 changes that require SSP restart, basically
46 * everything except the service and interrupt enables, the pxa270 developer
47 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
48 * list, but the PXA255 dev man says all bits without really meaning the
49 * service and interrupt enables
51 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
52 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
53 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
54 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
55 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
56 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
58 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
59 | QUARK_X1000_SSCR1_EFWR \
60 | QUARK_X1000_SSCR1_RFT \
61 | QUARK_X1000_SSCR1_TFT \
62 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
64 #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
65 #define SPI_CS_CONTROL_SW_MODE BIT(0)
66 #define SPI_CS_CONTROL_CS_HIGH BIT(1)
69 /* LPSS offset from drv_data->ioaddr */
71 /* Register offsets from drv_data->lpss_base or -1 */
81 /* Keep these sorted with enum pxa_ssp_type */
82 static const struct lpss_config lpss_platforms[] = {
89 .tx_threshold_lo = 160,
90 .tx_threshold_hi = 224,
98 .tx_threshold_lo = 160,
99 .tx_threshold_hi = 224,
107 .tx_threshold_lo = 32,
108 .tx_threshold_hi = 56,
112 static inline const struct lpss_config
113 *lpss_get_config(const struct driver_data *drv_data)
115 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
118 static bool is_lpss_ssp(const struct driver_data *drv_data)
120 switch (drv_data->ssp_type) {
130 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
132 return drv_data->ssp_type == QUARK_X1000_SSP;
135 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
137 switch (drv_data->ssp_type) {
138 case QUARK_X1000_SSP:
139 return QUARK_X1000_SSCR1_CHANGE_MASK;
141 return SSCR1_CHANGE_MASK;
146 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
148 switch (drv_data->ssp_type) {
149 case QUARK_X1000_SSP:
150 return RX_THRESH_QUARK_X1000_DFLT;
152 return RX_THRESH_DFLT;
156 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
160 switch (drv_data->ssp_type) {
161 case QUARK_X1000_SSP:
162 mask = QUARK_X1000_SSSR_TFL_MASK;
165 mask = SSSR_TFL_MASK;
169 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
172 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
177 switch (drv_data->ssp_type) {
178 case QUARK_X1000_SSP:
179 mask = QUARK_X1000_SSCR1_RFT;
188 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
189 u32 *sccr1_reg, u32 threshold)
191 switch (drv_data->ssp_type) {
192 case QUARK_X1000_SSP:
193 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
196 *sccr1_reg |= SSCR1_RxTresh(threshold);
201 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
202 u32 clk_div, u8 bits)
204 switch (drv_data->ssp_type) {
205 case QUARK_X1000_SSP:
207 | QUARK_X1000_SSCR0_Motorola
208 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
213 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
215 | (bits > 16 ? SSCR0_EDSS : 0);
220 * Read and write LPSS SSP private registers. Caller must first check that
221 * is_lpss_ssp() returns true before these can be called.
223 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
225 WARN_ON(!drv_data->lpss_base);
226 return readl(drv_data->lpss_base + offset);
229 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
230 unsigned offset, u32 value)
232 WARN_ON(!drv_data->lpss_base);
233 writel(value, drv_data->lpss_base + offset);
237 * lpss_ssp_setup - perform LPSS SSP specific setup
238 * @drv_data: pointer to the driver private data
240 * Perform LPSS SSP specific setup. This function must be called first if
241 * one is going to use LPSS SSP private registers.
243 static void lpss_ssp_setup(struct driver_data *drv_data)
245 const struct lpss_config *config;
248 config = lpss_get_config(drv_data);
249 drv_data->lpss_base = drv_data->ioaddr + config->offset;
251 /* Enable software chip select control */
252 value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
253 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
255 /* Enable multiblock DMA transfers */
256 if (drv_data->master_info->enable_dma) {
257 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
259 if (config->reg_general >= 0) {
260 value = __lpss_ssp_read_priv(drv_data,
261 config->reg_general);
262 value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE;
263 __lpss_ssp_write_priv(drv_data,
264 config->reg_general, value);
269 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
271 const struct lpss_config *config;
274 config = lpss_get_config(drv_data);
276 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
278 value &= ~SPI_CS_CONTROL_CS_HIGH;
280 value |= SPI_CS_CONTROL_CS_HIGH;
281 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
284 static void cs_assert(struct driver_data *drv_data)
286 struct chip_data *chip = drv_data->cur_chip;
288 if (drv_data->ssp_type == CE4100_SSP) {
289 pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm);
293 if (chip->cs_control) {
294 chip->cs_control(PXA2XX_CS_ASSERT);
298 if (gpio_is_valid(chip->gpio_cs)) {
299 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
303 if (is_lpss_ssp(drv_data))
304 lpss_ssp_cs_control(drv_data, true);
307 static void cs_deassert(struct driver_data *drv_data)
309 struct chip_data *chip = drv_data->cur_chip;
311 if (drv_data->ssp_type == CE4100_SSP)
314 if (chip->cs_control) {
315 chip->cs_control(PXA2XX_CS_DEASSERT);
319 if (gpio_is_valid(chip->gpio_cs)) {
320 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
324 if (is_lpss_ssp(drv_data))
325 lpss_ssp_cs_control(drv_data, false);
328 int pxa2xx_spi_flush(struct driver_data *drv_data)
330 unsigned long limit = loops_per_jiffy << 1;
333 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
334 pxa2xx_spi_read(drv_data, SSDR);
335 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
336 write_SSSR_CS(drv_data, SSSR_ROR);
341 static int null_writer(struct driver_data *drv_data)
343 u8 n_bytes = drv_data->n_bytes;
345 if (pxa2xx_spi_txfifo_full(drv_data)
346 || (drv_data->tx == drv_data->tx_end))
349 pxa2xx_spi_write(drv_data, SSDR, 0);
350 drv_data->tx += n_bytes;
355 static int null_reader(struct driver_data *drv_data)
357 u8 n_bytes = drv_data->n_bytes;
359 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
360 && (drv_data->rx < drv_data->rx_end)) {
361 pxa2xx_spi_read(drv_data, SSDR);
362 drv_data->rx += n_bytes;
365 return drv_data->rx == drv_data->rx_end;
368 static int u8_writer(struct driver_data *drv_data)
370 if (pxa2xx_spi_txfifo_full(drv_data)
371 || (drv_data->tx == drv_data->tx_end))
374 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
380 static int u8_reader(struct driver_data *drv_data)
382 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
383 && (drv_data->rx < drv_data->rx_end)) {
384 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
388 return drv_data->rx == drv_data->rx_end;
391 static int u16_writer(struct driver_data *drv_data)
393 if (pxa2xx_spi_txfifo_full(drv_data)
394 || (drv_data->tx == drv_data->tx_end))
397 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
403 static int u16_reader(struct driver_data *drv_data)
405 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
406 && (drv_data->rx < drv_data->rx_end)) {
407 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
411 return drv_data->rx == drv_data->rx_end;
414 static int u32_writer(struct driver_data *drv_data)
416 if (pxa2xx_spi_txfifo_full(drv_data)
417 || (drv_data->tx == drv_data->tx_end))
420 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
426 static int u32_reader(struct driver_data *drv_data)
428 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
429 && (drv_data->rx < drv_data->rx_end)) {
430 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
434 return drv_data->rx == drv_data->rx_end;
437 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
439 struct spi_message *msg = drv_data->cur_msg;
440 struct spi_transfer *trans = drv_data->cur_transfer;
442 /* Move to next transfer */
443 if (trans->transfer_list.next != &msg->transfers) {
444 drv_data->cur_transfer =
445 list_entry(trans->transfer_list.next,
448 return RUNNING_STATE;
453 /* caller already set message->status; dma and pio irqs are blocked */
454 static void giveback(struct driver_data *drv_data)
456 struct spi_transfer* last_transfer;
457 struct spi_message *msg;
459 msg = drv_data->cur_msg;
460 drv_data->cur_msg = NULL;
461 drv_data->cur_transfer = NULL;
463 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
466 /* Delay if requested before any change in chip select */
467 if (last_transfer->delay_usecs)
468 udelay(last_transfer->delay_usecs);
470 /* Drop chip select UNLESS cs_change is true or we are returning
471 * a message with an error, or next message is for another chip
473 if (!last_transfer->cs_change)
474 cs_deassert(drv_data);
476 struct spi_message *next_msg;
478 /* Holding of cs was hinted, but we need to make sure
479 * the next message is for the same chip. Don't waste
480 * time with the following tests unless this was hinted.
482 * We cannot postpone this until pump_messages, because
483 * after calling msg->complete (below) the driver that
484 * sent the current message could be unloaded, which
485 * could invalidate the cs_control() callback...
488 /* get a pointer to the next message, if any */
489 next_msg = spi_get_next_queued_message(drv_data->master);
491 /* see if the next and current messages point
494 if (next_msg && next_msg->spi != msg->spi)
496 if (!next_msg || msg->state == ERROR_STATE)
497 cs_deassert(drv_data);
500 drv_data->cur_chip = NULL;
501 spi_finalize_current_message(drv_data->master);
504 static void reset_sccr1(struct driver_data *drv_data)
506 struct chip_data *chip = drv_data->cur_chip;
509 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
510 sccr1_reg &= ~SSCR1_RFT;
511 sccr1_reg |= chip->threshold;
512 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
515 static void int_error_stop(struct driver_data *drv_data, const char* msg)
517 /* Stop and reset SSP */
518 write_SSSR_CS(drv_data, drv_data->clear_sr);
519 reset_sccr1(drv_data);
520 if (!pxa25x_ssp_comp(drv_data))
521 pxa2xx_spi_write(drv_data, SSTO, 0);
522 pxa2xx_spi_flush(drv_data);
523 pxa2xx_spi_write(drv_data, SSCR0,
524 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
526 dev_err(&drv_data->pdev->dev, "%s\n", msg);
528 drv_data->cur_msg->state = ERROR_STATE;
529 tasklet_schedule(&drv_data->pump_transfers);
532 static void int_transfer_complete(struct driver_data *drv_data)
535 write_SSSR_CS(drv_data, drv_data->clear_sr);
536 reset_sccr1(drv_data);
537 if (!pxa25x_ssp_comp(drv_data))
538 pxa2xx_spi_write(drv_data, SSTO, 0);
540 /* Update total byte transferred return count actual bytes read */
541 drv_data->cur_msg->actual_length += drv_data->len -
542 (drv_data->rx_end - drv_data->rx);
544 /* Transfer delays and chip select release are
545 * handled in pump_transfers or giveback
548 /* Move to next transfer */
549 drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
551 /* Schedule transfer tasklet */
552 tasklet_schedule(&drv_data->pump_transfers);
555 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
557 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
558 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
560 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
562 if (irq_status & SSSR_ROR) {
563 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
567 if (irq_status & SSSR_TINT) {
568 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
569 if (drv_data->read(drv_data)) {
570 int_transfer_complete(drv_data);
575 /* Drain rx fifo, Fill tx fifo and prevent overruns */
577 if (drv_data->read(drv_data)) {
578 int_transfer_complete(drv_data);
581 } while (drv_data->write(drv_data));
583 if (drv_data->read(drv_data)) {
584 int_transfer_complete(drv_data);
588 if (drv_data->tx == drv_data->tx_end) {
592 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
593 sccr1_reg &= ~SSCR1_TIE;
596 * PXA25x_SSP has no timeout, set up rx threshould for the
597 * remaining RX bytes.
599 if (pxa25x_ssp_comp(drv_data)) {
602 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
604 bytes_left = drv_data->rx_end - drv_data->rx;
605 switch (drv_data->n_bytes) {
612 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
613 if (rx_thre > bytes_left)
614 rx_thre = bytes_left;
616 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
618 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
621 /* We did something */
625 static irqreturn_t ssp_int(int irq, void *dev_id)
627 struct driver_data *drv_data = dev_id;
629 u32 mask = drv_data->mask_sr;
633 * The IRQ might be shared with other peripherals so we must first
634 * check that are we RPM suspended or not. If we are we assume that
635 * the IRQ was not for us (we shouldn't be RPM suspended when the
636 * interrupt is enabled).
638 if (pm_runtime_suspended(&drv_data->pdev->dev))
642 * If the device is not yet in RPM suspended state and we get an
643 * interrupt that is meant for another device, check if status bits
644 * are all set to one. That means that the device is already
647 status = pxa2xx_spi_read(drv_data, SSSR);
651 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
653 /* Ignore possible writes if we don't need to write */
654 if (!(sccr1_reg & SSCR1_TIE))
657 if (!(status & mask))
660 if (!drv_data->cur_msg) {
662 pxa2xx_spi_write(drv_data, SSCR0,
663 pxa2xx_spi_read(drv_data, SSCR0)
665 pxa2xx_spi_write(drv_data, SSCR1,
666 pxa2xx_spi_read(drv_data, SSCR1)
667 & ~drv_data->int_cr1);
668 if (!pxa25x_ssp_comp(drv_data))
669 pxa2xx_spi_write(drv_data, SSTO, 0);
670 write_SSSR_CS(drv_data, drv_data->clear_sr);
672 dev_err(&drv_data->pdev->dev,
673 "bad message state in interrupt handler\n");
679 return drv_data->transfer_handler(drv_data);
683 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
684 * input frequency by fractions of 2^24. It also has a divider by 5.
686 * There are formulas to get baud rate value for given input frequency and
687 * divider parameters, such as DDS_CLK_RATE and SCR:
691 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
692 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
694 * DDS_CLK_RATE either 2^n or 2^n / 5.
695 * SCR is in range 0 .. 255
697 * Divisor = 5^i * 2^j * 2 * k
698 * i = [0, 1] i = 1 iff j = 0 or j > 3
699 * j = [0, 23] j = 0 iff i = 1
701 * Special case: j = 0, i = 1: Divisor = 2 / 5
703 * Accordingly to the specification the recommended values for DDS_CLK_RATE
705 * Case 1: 2^n, n = [0, 23]
706 * Case 2: 2^24 * 2 / 5 (0x666666)
707 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
709 * In all cases the lowest possible value is better.
711 * The function calculates parameters for all cases and chooses the one closest
712 * to the asked baud rate.
714 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
716 unsigned long xtal = 200000000;
717 unsigned long fref = xtal / 2; /* mandatory division by 2,
720 unsigned long fref1 = fref / 2; /* case 1 */
721 unsigned long fref2 = fref * 2 / 5; /* case 2 */
723 unsigned long q, q1, q2;
729 /* Set initial value for DDS_CLK_RATE */
730 mul = (1 << 24) >> 1;
732 /* Calculate initial quot */
733 q1 = DIV_ROUND_UP(fref1, rate);
735 /* Scale q1 if it's too big */
737 /* Scale q1 to range [1, 512] */
738 scale = fls_long(q1 - 1);
744 /* Round the result if we have a remainder */
748 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
753 /* Get the remainder */
754 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
758 q2 = DIV_ROUND_UP(fref2, rate);
759 r2 = abs(fref2 / q2 - rate);
762 * Choose the best between two: less remainder we have the better. We
763 * can't go case 2 if q2 is greater than 256 since SCR register can
764 * hold only values 0 .. 255.
766 if (r2 >= r1 || q2 > 256) {
767 /* case 1 is better */
771 /* case 2 is better */
774 mul = (1 << 24) * 2 / 5;
777 /* Check case 3 only if the divisor is big enough */
778 if (fref / rate >= 80) {
782 /* Calculate initial quot */
783 q1 = DIV_ROUND_UP(fref, rate);
786 /* Get the remainder */
787 fssp = (u64)fref * m;
788 do_div(fssp, 1 << 24);
789 r1 = abs(fssp - rate);
791 /* Choose this one if it suits better */
793 /* case 3 is better */
803 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
805 unsigned long ssp_clk = drv_data->master->max_speed_hz;
806 const struct ssp_device *ssp = drv_data->ssp;
808 rate = min_t(int, ssp_clk, rate);
810 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
811 return (ssp_clk / (2 * rate) - 1) & 0xff;
813 return (ssp_clk / rate - 1) & 0xfff;
816 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
819 struct chip_data *chip = drv_data->cur_chip;
820 unsigned int clk_div;
822 switch (drv_data->ssp_type) {
823 case QUARK_X1000_SSP:
824 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
827 clk_div = ssp_get_clk_div(drv_data, rate);
833 static void pump_transfers(unsigned long data)
835 struct driver_data *drv_data = (struct driver_data *)data;
836 struct spi_message *message = NULL;
837 struct spi_transfer *transfer = NULL;
838 struct spi_transfer *previous = NULL;
839 struct chip_data *chip = NULL;
845 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
846 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
847 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
849 /* Get current state information */
850 message = drv_data->cur_msg;
851 transfer = drv_data->cur_transfer;
852 chip = drv_data->cur_chip;
854 /* Handle for abort */
855 if (message->state == ERROR_STATE) {
856 message->status = -EIO;
861 /* Handle end of message */
862 if (message->state == DONE_STATE) {
868 /* Delay if requested at end of transfer before CS change */
869 if (message->state == RUNNING_STATE) {
870 previous = list_entry(transfer->transfer_list.prev,
873 if (previous->delay_usecs)
874 udelay(previous->delay_usecs);
876 /* Drop chip select only if cs_change is requested */
877 if (previous->cs_change)
878 cs_deassert(drv_data);
881 /* Check if we can DMA this transfer */
882 if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
884 /* reject already-mapped transfers; PIO won't always work */
885 if (message->is_dma_mapped
886 || transfer->rx_dma || transfer->tx_dma) {
887 dev_err(&drv_data->pdev->dev,
888 "pump_transfers: mapped transfer length of "
889 "%u is greater than %d\n",
890 transfer->len, MAX_DMA_LEN);
891 message->status = -EINVAL;
896 /* warn ... we force this to PIO mode */
897 dev_warn_ratelimited(&message->spi->dev,
898 "pump_transfers: DMA disabled for transfer length %ld "
900 (long)drv_data->len, MAX_DMA_LEN);
903 /* Setup the transfer state based on the type of transfer */
904 if (pxa2xx_spi_flush(drv_data) == 0) {
905 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
906 message->status = -EIO;
910 drv_data->n_bytes = chip->n_bytes;
911 drv_data->tx = (void *)transfer->tx_buf;
912 drv_data->tx_end = drv_data->tx + transfer->len;
913 drv_data->rx = transfer->rx_buf;
914 drv_data->rx_end = drv_data->rx + transfer->len;
915 drv_data->rx_dma = transfer->rx_dma;
916 drv_data->tx_dma = transfer->tx_dma;
917 drv_data->len = transfer->len;
918 drv_data->write = drv_data->tx ? chip->write : null_writer;
919 drv_data->read = drv_data->rx ? chip->read : null_reader;
921 /* Change speed and bit per word on a per transfer */
922 bits = transfer->bits_per_word;
923 speed = transfer->speed_hz;
925 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
928 drv_data->n_bytes = 1;
929 drv_data->read = drv_data->read != null_reader ?
930 u8_reader : null_reader;
931 drv_data->write = drv_data->write != null_writer ?
932 u8_writer : null_writer;
933 } else if (bits <= 16) {
934 drv_data->n_bytes = 2;
935 drv_data->read = drv_data->read != null_reader ?
936 u16_reader : null_reader;
937 drv_data->write = drv_data->write != null_writer ?
938 u16_writer : null_writer;
939 } else if (bits <= 32) {
940 drv_data->n_bytes = 4;
941 drv_data->read = drv_data->read != null_reader ?
942 u32_reader : null_reader;
943 drv_data->write = drv_data->write != null_writer ?
944 u32_writer : null_writer;
947 * if bits/word is changed in dma mode, then must check the
948 * thresholds and burst also
950 if (chip->enable_dma) {
951 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
955 dev_warn_ratelimited(&message->spi->dev,
956 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
959 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
960 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
961 if (!pxa25x_ssp_comp(drv_data))
962 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
963 drv_data->master->max_speed_hz
964 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
965 chip->enable_dma ? "DMA" : "PIO");
967 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
968 drv_data->master->max_speed_hz / 2
969 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
970 chip->enable_dma ? "DMA" : "PIO");
972 message->state = RUNNING_STATE;
974 drv_data->dma_mapped = 0;
975 if (pxa2xx_spi_dma_is_possible(drv_data->len))
976 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
977 if (drv_data->dma_mapped) {
979 /* Ensure we have the correct interrupt handler */
980 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
982 pxa2xx_spi_dma_prepare(drv_data, dma_burst);
984 /* Clear status and start DMA engine */
985 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
986 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
988 pxa2xx_spi_dma_start(drv_data);
990 /* Ensure we have the correct interrupt handler */
991 drv_data->transfer_handler = interrupt_transfer;
994 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
995 write_SSSR_CS(drv_data, drv_data->clear_sr);
998 if (is_lpss_ssp(drv_data)) {
999 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1000 != chip->lpss_rx_threshold)
1001 pxa2xx_spi_write(drv_data, SSIRF,
1002 chip->lpss_rx_threshold);
1003 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1004 != chip->lpss_tx_threshold)
1005 pxa2xx_spi_write(drv_data, SSITF,
1006 chip->lpss_tx_threshold);
1009 if (is_quark_x1000_ssp(drv_data) &&
1010 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1011 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1013 /* see if we need to reload the config registers */
1014 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1015 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1016 != (cr1 & change_mask)) {
1017 /* stop the SSP, and update the other bits */
1018 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1019 if (!pxa25x_ssp_comp(drv_data))
1020 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1021 /* first set CR1 without interrupt and service enables */
1022 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1023 /* restart the SSP */
1024 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1027 if (!pxa25x_ssp_comp(drv_data))
1028 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1031 cs_assert(drv_data);
1033 /* after chip select, release the data by enabling service
1034 * requests and interrupts, without changing any mode bits */
1035 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1038 static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
1039 struct spi_message *msg)
1041 struct driver_data *drv_data = spi_master_get_devdata(master);
1043 drv_data->cur_msg = msg;
1044 /* Initial message state*/
1045 drv_data->cur_msg->state = START_STATE;
1046 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1047 struct spi_transfer,
1050 /* prepare to setup the SSP, in pump_transfers, using the per
1051 * chip configuration */
1052 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1054 /* Mark as busy and launch transfers */
1055 tasklet_schedule(&drv_data->pump_transfers);
1059 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
1061 struct driver_data *drv_data = spi_master_get_devdata(master);
1063 /* Disable the SSP now */
1064 pxa2xx_spi_write(drv_data, SSCR0,
1065 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1070 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1071 struct pxa2xx_spi_chip *chip_info)
1075 if (chip == NULL || chip_info == NULL)
1078 /* NOTE: setup() can be called multiple times, possibly with
1079 * different chip_info, release previously requested GPIO
1081 if (gpio_is_valid(chip->gpio_cs))
1082 gpio_free(chip->gpio_cs);
1084 /* If (*cs_control) is provided, ignore GPIO chip select */
1085 if (chip_info->cs_control) {
1086 chip->cs_control = chip_info->cs_control;
1090 if (gpio_is_valid(chip_info->gpio_cs)) {
1091 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1093 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1094 chip_info->gpio_cs);
1098 chip->gpio_cs = chip_info->gpio_cs;
1099 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1101 err = gpio_direction_output(chip->gpio_cs,
1102 !chip->gpio_cs_inverted);
1108 static int setup(struct spi_device *spi)
1110 struct pxa2xx_spi_chip *chip_info = NULL;
1111 struct chip_data *chip;
1112 const struct lpss_config *config;
1113 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1114 uint tx_thres, tx_hi_thres, rx_thres;
1116 switch (drv_data->ssp_type) {
1117 case QUARK_X1000_SSP:
1118 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1120 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1125 config = lpss_get_config(drv_data);
1126 tx_thres = config->tx_threshold_lo;
1127 tx_hi_thres = config->tx_threshold_hi;
1128 rx_thres = config->rx_threshold;
1131 tx_thres = TX_THRESH_DFLT;
1133 rx_thres = RX_THRESH_DFLT;
1137 /* Only alloc on first setup */
1138 chip = spi_get_ctldata(spi);
1140 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1144 if (drv_data->ssp_type == CE4100_SSP) {
1145 if (spi->chip_select > 4) {
1147 "failed setup: cs number must not be > 4.\n");
1152 chip->frm = spi->chip_select;
1155 chip->enable_dma = 0;
1156 chip->timeout = TIMOUT_DFLT;
1159 /* protocol drivers may change the chip settings, so...
1160 * if chip_info exists, use it */
1161 chip_info = spi->controller_data;
1163 /* chip_info isn't always needed */
1166 if (chip_info->timeout)
1167 chip->timeout = chip_info->timeout;
1168 if (chip_info->tx_threshold)
1169 tx_thres = chip_info->tx_threshold;
1170 if (chip_info->tx_hi_threshold)
1171 tx_hi_thres = chip_info->tx_hi_threshold;
1172 if (chip_info->rx_threshold)
1173 rx_thres = chip_info->rx_threshold;
1174 chip->enable_dma = drv_data->master_info->enable_dma;
1175 chip->dma_threshold = 0;
1176 if (chip_info->enable_loopback)
1177 chip->cr1 = SSCR1_LBM;
1178 } else if (ACPI_HANDLE(&spi->dev)) {
1180 * Slave devices enumerated from ACPI namespace don't
1181 * usually have chip_info but we still might want to use
1184 chip->enable_dma = drv_data->master_info->enable_dma;
1187 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1188 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1189 | SSITF_TxHiThresh(tx_hi_thres);
1191 /* set dma burst and threshold outside of chip_info path so that if
1192 * chip_info goes away after setting chip->enable_dma, the
1193 * burst and threshold can still respond to changes in bits_per_word */
1194 if (chip->enable_dma) {
1195 /* set up legal burst and threshold for dma */
1196 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1198 &chip->dma_burst_size,
1199 &chip->dma_threshold)) {
1201 "in setup: DMA burst size reduced to match bits_per_word\n");
1205 switch (drv_data->ssp_type) {
1206 case QUARK_X1000_SSP:
1207 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1208 & QUARK_X1000_SSCR1_RFT)
1209 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1210 & QUARK_X1000_SSCR1_TFT);
1213 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1214 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1218 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1219 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1220 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1222 if (spi->mode & SPI_LOOP)
1223 chip->cr1 |= SSCR1_LBM;
1225 if (spi->bits_per_word <= 8) {
1227 chip->read = u8_reader;
1228 chip->write = u8_writer;
1229 } else if (spi->bits_per_word <= 16) {
1231 chip->read = u16_reader;
1232 chip->write = u16_writer;
1233 } else if (spi->bits_per_word <= 32) {
1235 chip->read = u32_reader;
1236 chip->write = u32_writer;
1239 spi_set_ctldata(spi, chip);
1241 if (drv_data->ssp_type == CE4100_SSP)
1244 return setup_cs(spi, chip, chip_info);
1247 static void cleanup(struct spi_device *spi)
1249 struct chip_data *chip = spi_get_ctldata(spi);
1250 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1255 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1256 gpio_free(chip->gpio_cs);
1263 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1264 { "INT33C0", LPSS_LPT_SSP },
1265 { "INT33C1", LPSS_LPT_SSP },
1266 { "INT3430", LPSS_LPT_SSP },
1267 { "INT3431", LPSS_LPT_SSP },
1268 { "80860F0E", LPSS_BYT_SSP },
1269 { "8086228E", LPSS_BYT_SSP },
1272 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1275 * PCI IDs of compound devices that integrate both host controller and private
1276 * integrated DMA engine. Please note these are not used in module
1277 * autoloading and probing in this module but matching the LPSS SSP type.
1279 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1281 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1282 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1284 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1285 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1289 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1291 struct device *dev = param;
1293 if (dev != chan->device->dev->parent)
1299 static struct pxa2xx_spi_master *
1300 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1302 struct pxa2xx_spi_master *pdata;
1303 struct acpi_device *adev;
1304 struct ssp_device *ssp;
1305 struct resource *res;
1306 const struct acpi_device_id *adev_id = NULL;
1307 const struct pci_device_id *pcidev_id = NULL;
1311 adev = ACPI_COMPANION(&pdev->dev);
1315 if (dev_is_pci(pdev->dev.parent))
1316 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1317 to_pci_dev(pdev->dev.parent));
1319 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1323 type = (int)adev_id->driver_data;
1325 type = (int)pcidev_id->driver_data;
1329 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1333 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1339 ssp->phys_base = res->start;
1340 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1341 if (IS_ERR(ssp->mmio_base))
1345 pdata->tx_param = pdev->dev.parent;
1346 pdata->rx_param = pdev->dev.parent;
1347 pdata->dma_filter = pxa2xx_spi_idma_filter;
1350 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1351 ssp->irq = platform_get_irq(pdev, 0);
1356 if (adev->pnp.unique_id && !kstrtouint(adev->pnp.unique_id, 0, &devid))
1357 ssp->port_id = devid;
1359 pdata->num_chipselect = 1;
1360 pdata->enable_dma = true;
1366 static inline struct pxa2xx_spi_master *
1367 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1373 static int pxa2xx_spi_probe(struct platform_device *pdev)
1375 struct device *dev = &pdev->dev;
1376 struct pxa2xx_spi_master *platform_info;
1377 struct spi_master *master;
1378 struct driver_data *drv_data;
1379 struct ssp_device *ssp;
1383 platform_info = dev_get_platdata(dev);
1384 if (!platform_info) {
1385 platform_info = pxa2xx_spi_acpi_get_pdata(pdev);
1386 if (!platform_info) {
1387 dev_err(&pdev->dev, "missing platform data\n");
1392 ssp = pxa_ssp_request(pdev->id, pdev->name);
1394 ssp = &platform_info->ssp;
1396 if (!ssp->mmio_base) {
1397 dev_err(&pdev->dev, "failed to get ssp\n");
1401 master = spi_alloc_master(dev, sizeof(struct driver_data));
1403 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1407 drv_data = spi_master_get_devdata(master);
1408 drv_data->master = master;
1409 drv_data->master_info = platform_info;
1410 drv_data->pdev = pdev;
1411 drv_data->ssp = ssp;
1413 master->dev.parent = &pdev->dev;
1414 master->dev.of_node = pdev->dev.of_node;
1415 /* the spi->mode bits understood by this driver: */
1416 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1418 master->bus_num = ssp->port_id;
1419 master->num_chipselect = platform_info->num_chipselect;
1420 master->dma_alignment = DMA_ALIGNMENT;
1421 master->cleanup = cleanup;
1422 master->setup = setup;
1423 master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1424 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1425 master->auto_runtime_pm = true;
1427 drv_data->ssp_type = ssp->type;
1429 drv_data->ioaddr = ssp->mmio_base;
1430 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1431 if (pxa25x_ssp_comp(drv_data)) {
1432 switch (drv_data->ssp_type) {
1433 case QUARK_X1000_SSP:
1434 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1437 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1441 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1442 drv_data->dma_cr1 = 0;
1443 drv_data->clear_sr = SSSR_ROR;
1444 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1446 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1447 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1448 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1449 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1450 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1453 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1456 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1457 goto out_error_master_alloc;
1460 /* Setup DMA if requested */
1461 if (platform_info->enable_dma) {
1462 status = pxa2xx_spi_dma_setup(drv_data);
1464 dev_dbg(dev, "no DMA channels available, using PIO\n");
1465 platform_info->enable_dma = false;
1469 /* Enable SOC clock */
1470 clk_prepare_enable(ssp->clk);
1472 master->max_speed_hz = clk_get_rate(ssp->clk);
1474 /* Load default SSP configuration */
1475 pxa2xx_spi_write(drv_data, SSCR0, 0);
1476 switch (drv_data->ssp_type) {
1477 case QUARK_X1000_SSP:
1478 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT)
1479 | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1480 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1482 /* using the Motorola SPI protocol and use 8 bit frame */
1483 pxa2xx_spi_write(drv_data, SSCR0,
1484 QUARK_X1000_SSCR0_Motorola
1485 | QUARK_X1000_SSCR0_DataSize(8));
1488 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1489 SSCR1_TxTresh(TX_THRESH_DFLT);
1490 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1491 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1492 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1496 if (!pxa25x_ssp_comp(drv_data))
1497 pxa2xx_spi_write(drv_data, SSTO, 0);
1499 if (!is_quark_x1000_ssp(drv_data))
1500 pxa2xx_spi_write(drv_data, SSPSP, 0);
1502 if (is_lpss_ssp(drv_data))
1503 lpss_ssp_setup(drv_data);
1505 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1506 (unsigned long)drv_data);
1508 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1509 pm_runtime_use_autosuspend(&pdev->dev);
1510 pm_runtime_set_active(&pdev->dev);
1511 pm_runtime_enable(&pdev->dev);
1513 /* Register with the SPI framework */
1514 platform_set_drvdata(pdev, drv_data);
1515 status = devm_spi_register_master(&pdev->dev, master);
1517 dev_err(&pdev->dev, "problem registering spi master\n");
1518 goto out_error_clock_enabled;
1523 out_error_clock_enabled:
1524 clk_disable_unprepare(ssp->clk);
1525 pxa2xx_spi_dma_release(drv_data);
1526 free_irq(ssp->irq, drv_data);
1528 out_error_master_alloc:
1529 spi_master_put(master);
1534 static int pxa2xx_spi_remove(struct platform_device *pdev)
1536 struct driver_data *drv_data = platform_get_drvdata(pdev);
1537 struct ssp_device *ssp;
1541 ssp = drv_data->ssp;
1543 pm_runtime_get_sync(&pdev->dev);
1545 /* Disable the SSP at the peripheral and SOC level */
1546 pxa2xx_spi_write(drv_data, SSCR0, 0);
1547 clk_disable_unprepare(ssp->clk);
1550 if (drv_data->master_info->enable_dma)
1551 pxa2xx_spi_dma_release(drv_data);
1553 pm_runtime_put_noidle(&pdev->dev);
1554 pm_runtime_disable(&pdev->dev);
1557 free_irq(ssp->irq, drv_data);
1565 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1569 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1570 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1573 #ifdef CONFIG_PM_SLEEP
1574 static int pxa2xx_spi_suspend(struct device *dev)
1576 struct driver_data *drv_data = dev_get_drvdata(dev);
1577 struct ssp_device *ssp = drv_data->ssp;
1580 status = spi_master_suspend(drv_data->master);
1583 pxa2xx_spi_write(drv_data, SSCR0, 0);
1585 if (!pm_runtime_suspended(dev))
1586 clk_disable_unprepare(ssp->clk);
1591 static int pxa2xx_spi_resume(struct device *dev)
1593 struct driver_data *drv_data = dev_get_drvdata(dev);
1594 struct ssp_device *ssp = drv_data->ssp;
1597 /* Enable the SSP clock */
1598 if (!pm_runtime_suspended(dev))
1599 clk_prepare_enable(ssp->clk);
1601 /* Restore LPSS private register bits */
1602 if (is_lpss_ssp(drv_data))
1603 lpss_ssp_setup(drv_data);
1605 /* Start the queue running */
1606 status = spi_master_resume(drv_data->master);
1608 dev_err(dev, "problem starting queue (%d)\n", status);
1617 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1619 struct driver_data *drv_data = dev_get_drvdata(dev);
1621 clk_disable_unprepare(drv_data->ssp->clk);
1625 static int pxa2xx_spi_runtime_resume(struct device *dev)
1627 struct driver_data *drv_data = dev_get_drvdata(dev);
1629 clk_prepare_enable(drv_data->ssp->clk);
1634 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1635 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1636 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1637 pxa2xx_spi_runtime_resume, NULL)
1640 static struct platform_driver driver = {
1642 .name = "pxa2xx-spi",
1643 .pm = &pxa2xx_spi_pm_ops,
1644 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1646 .probe = pxa2xx_spi_probe,
1647 .remove = pxa2xx_spi_remove,
1648 .shutdown = pxa2xx_spi_shutdown,
1651 static int __init pxa2xx_spi_init(void)
1653 return platform_driver_register(&driver);
1655 subsys_initcall(pxa2xx_spi_init);
1657 static void __exit pxa2xx_spi_exit(void)
1659 platform_driver_unregister(&driver);
1661 module_exit(pxa2xx_spi_exit);