2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/bitops.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/ioport.h>
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/pci.h>
26 #include <linux/platform_device.h>
27 #include <linux/spi/pxa2xx_spi.h>
28 #include <linux/spi/spi.h>
29 #include <linux/delay.h>
30 #include <linux/gpio.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/slab.h>
33 #include <linux/clk.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/acpi.h>
36 #include <linux/of_device.h>
38 #include "spi-pxa2xx.h"
40 MODULE_AUTHOR("Stephen Street");
41 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
42 MODULE_LICENSE("GPL");
43 MODULE_ALIAS("platform:pxa2xx-spi");
45 #define TIMOUT_DFLT 1000
48 * for testing SSCR1 changes that require SSP restart, basically
49 * everything except the service and interrupt enables, the pxa270 developer
50 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
51 * list, but the PXA255 dev man says all bits without really meaning the
52 * service and interrupt enables
54 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
55 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
56 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
57 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
58 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
59 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
61 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
62 | QUARK_X1000_SSCR1_EFWR \
63 | QUARK_X1000_SSCR1_RFT \
64 | QUARK_X1000_SSCR1_TFT \
65 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
67 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
68 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
69 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
70 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
71 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
72 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
74 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
75 #define LPSS_CS_CONTROL_SW_MODE BIT(0)
76 #define LPSS_CS_CONTROL_CS_HIGH BIT(1)
77 #define LPSS_CAPS_CS_EN_SHIFT 9
78 #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
81 /* LPSS offset from drv_data->ioaddr */
83 /* Register offsets from drv_data->lpss_base or -1 */
92 /* Chip select control */
93 unsigned cs_sel_shift;
98 /* Keep these sorted with enum pxa_ssp_type */
99 static const struct lpss_config lpss_platforms[] = {
105 .reg_capabilities = -1,
107 .tx_threshold_lo = 160,
108 .tx_threshold_hi = 224,
115 .reg_capabilities = -1,
117 .tx_threshold_lo = 160,
118 .tx_threshold_hi = 224,
125 .reg_capabilities = -1,
127 .tx_threshold_lo = 160,
128 .tx_threshold_hi = 224,
130 .cs_sel_mask = 1 << 2,
138 .reg_capabilities = -1,
140 .tx_threshold_lo = 32,
141 .tx_threshold_hi = 56,
148 .reg_capabilities = 0xfc,
150 .tx_threshold_lo = 16,
151 .tx_threshold_hi = 48,
153 .cs_sel_mask = 3 << 8,
160 .reg_capabilities = 0xfc,
162 .tx_threshold_lo = 32,
163 .tx_threshold_hi = 56,
165 .cs_sel_mask = 3 << 8,
169 static inline const struct lpss_config
170 *lpss_get_config(const struct driver_data *drv_data)
172 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
175 static bool is_lpss_ssp(const struct driver_data *drv_data)
177 switch (drv_data->ssp_type) {
190 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
192 return drv_data->ssp_type == QUARK_X1000_SSP;
195 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
197 switch (drv_data->ssp_type) {
198 case QUARK_X1000_SSP:
199 return QUARK_X1000_SSCR1_CHANGE_MASK;
201 return CE4100_SSCR1_CHANGE_MASK;
203 return SSCR1_CHANGE_MASK;
208 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
210 switch (drv_data->ssp_type) {
211 case QUARK_X1000_SSP:
212 return RX_THRESH_QUARK_X1000_DFLT;
214 return RX_THRESH_CE4100_DFLT;
216 return RX_THRESH_DFLT;
220 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
224 switch (drv_data->ssp_type) {
225 case QUARK_X1000_SSP:
226 mask = QUARK_X1000_SSSR_TFL_MASK;
229 mask = CE4100_SSSR_TFL_MASK;
232 mask = SSSR_TFL_MASK;
236 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
239 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
244 switch (drv_data->ssp_type) {
245 case QUARK_X1000_SSP:
246 mask = QUARK_X1000_SSCR1_RFT;
249 mask = CE4100_SSCR1_RFT;
258 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
259 u32 *sccr1_reg, u32 threshold)
261 switch (drv_data->ssp_type) {
262 case QUARK_X1000_SSP:
263 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
266 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
269 *sccr1_reg |= SSCR1_RxTresh(threshold);
274 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
275 u32 clk_div, u8 bits)
277 switch (drv_data->ssp_type) {
278 case QUARK_X1000_SSP:
280 | QUARK_X1000_SSCR0_Motorola
281 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
286 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
288 | (bits > 16 ? SSCR0_EDSS : 0);
293 * Read and write LPSS SSP private registers. Caller must first check that
294 * is_lpss_ssp() returns true before these can be called.
296 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
298 WARN_ON(!drv_data->lpss_base);
299 return readl(drv_data->lpss_base + offset);
302 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
303 unsigned offset, u32 value)
305 WARN_ON(!drv_data->lpss_base);
306 writel(value, drv_data->lpss_base + offset);
310 * lpss_ssp_setup - perform LPSS SSP specific setup
311 * @drv_data: pointer to the driver private data
313 * Perform LPSS SSP specific setup. This function must be called first if
314 * one is going to use LPSS SSP private registers.
316 static void lpss_ssp_setup(struct driver_data *drv_data)
318 const struct lpss_config *config;
321 config = lpss_get_config(drv_data);
322 drv_data->lpss_base = drv_data->ioaddr + config->offset;
324 /* Enable software chip select control */
325 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
326 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
327 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
328 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
330 /* Enable multiblock DMA transfers */
331 if (drv_data->controller_info->enable_dma) {
332 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
334 if (config->reg_general >= 0) {
335 value = __lpss_ssp_read_priv(drv_data,
336 config->reg_general);
337 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
338 __lpss_ssp_write_priv(drv_data,
339 config->reg_general, value);
344 static void lpss_ssp_select_cs(struct spi_device *spi,
345 const struct lpss_config *config)
347 struct driver_data *drv_data =
348 spi_controller_get_devdata(spi->controller);
351 if (!config->cs_sel_mask)
354 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
356 cs = spi->chip_select;
357 cs <<= config->cs_sel_shift;
358 if (cs != (value & config->cs_sel_mask)) {
360 * When switching another chip select output active the
361 * output must be selected first and wait 2 ssp_clk cycles
362 * before changing state to active. Otherwise a short
363 * glitch will occur on the previous chip select since
364 * output select is latched but state control is not.
366 value &= ~config->cs_sel_mask;
368 __lpss_ssp_write_priv(drv_data,
369 config->reg_cs_ctrl, value);
371 (drv_data->controller->max_speed_hz / 2));
375 static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
377 struct driver_data *drv_data =
378 spi_controller_get_devdata(spi->controller);
379 const struct lpss_config *config;
382 config = lpss_get_config(drv_data);
385 lpss_ssp_select_cs(spi, config);
387 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
389 value &= ~LPSS_CS_CONTROL_CS_HIGH;
391 value |= LPSS_CS_CONTROL_CS_HIGH;
392 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
395 static void cs_assert(struct spi_device *spi)
397 struct chip_data *chip = spi_get_ctldata(spi);
398 struct driver_data *drv_data =
399 spi_controller_get_devdata(spi->controller);
401 if (drv_data->ssp_type == CE4100_SSP) {
402 pxa2xx_spi_write(drv_data, SSSR, chip->frm);
406 if (chip->cs_control) {
407 chip->cs_control(PXA2XX_CS_ASSERT);
411 if (chip->gpiod_cs) {
412 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
416 if (is_lpss_ssp(drv_data))
417 lpss_ssp_cs_control(spi, true);
420 static void cs_deassert(struct spi_device *spi)
422 struct chip_data *chip = spi_get_ctldata(spi);
423 struct driver_data *drv_data =
424 spi_controller_get_devdata(spi->controller);
425 unsigned long timeout;
427 if (drv_data->ssp_type == CE4100_SSP)
430 /* Wait until SSP becomes idle before deasserting the CS */
431 timeout = jiffies + msecs_to_jiffies(10);
432 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
433 !time_after(jiffies, timeout))
436 if (chip->cs_control) {
437 chip->cs_control(PXA2XX_CS_DEASSERT);
441 if (chip->gpiod_cs) {
442 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
446 if (is_lpss_ssp(drv_data))
447 lpss_ssp_cs_control(spi, false);
450 static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
458 int pxa2xx_spi_flush(struct driver_data *drv_data)
460 unsigned long limit = loops_per_jiffy << 1;
463 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
464 pxa2xx_spi_read(drv_data, SSDR);
465 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
466 write_SSSR_CS(drv_data, SSSR_ROR);
471 static int null_writer(struct driver_data *drv_data)
473 u8 n_bytes = drv_data->n_bytes;
475 if (pxa2xx_spi_txfifo_full(drv_data)
476 || (drv_data->tx == drv_data->tx_end))
479 pxa2xx_spi_write(drv_data, SSDR, 0);
480 drv_data->tx += n_bytes;
485 static int null_reader(struct driver_data *drv_data)
487 u8 n_bytes = drv_data->n_bytes;
489 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
490 && (drv_data->rx < drv_data->rx_end)) {
491 pxa2xx_spi_read(drv_data, SSDR);
492 drv_data->rx += n_bytes;
495 return drv_data->rx == drv_data->rx_end;
498 static int u8_writer(struct driver_data *drv_data)
500 if (pxa2xx_spi_txfifo_full(drv_data)
501 || (drv_data->tx == drv_data->tx_end))
504 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
510 static int u8_reader(struct driver_data *drv_data)
512 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
513 && (drv_data->rx < drv_data->rx_end)) {
514 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
518 return drv_data->rx == drv_data->rx_end;
521 static int u16_writer(struct driver_data *drv_data)
523 if (pxa2xx_spi_txfifo_full(drv_data)
524 || (drv_data->tx == drv_data->tx_end))
527 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
533 static int u16_reader(struct driver_data *drv_data)
535 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
536 && (drv_data->rx < drv_data->rx_end)) {
537 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
541 return drv_data->rx == drv_data->rx_end;
544 static int u32_writer(struct driver_data *drv_data)
546 if (pxa2xx_spi_txfifo_full(drv_data)
547 || (drv_data->tx == drv_data->tx_end))
550 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
556 static int u32_reader(struct driver_data *drv_data)
558 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
559 && (drv_data->rx < drv_data->rx_end)) {
560 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
564 return drv_data->rx == drv_data->rx_end;
567 static void reset_sccr1(struct driver_data *drv_data)
569 struct chip_data *chip =
570 spi_get_ctldata(drv_data->controller->cur_msg->spi);
573 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
574 switch (drv_data->ssp_type) {
575 case QUARK_X1000_SSP:
576 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
579 sccr1_reg &= ~CE4100_SSCR1_RFT;
582 sccr1_reg &= ~SSCR1_RFT;
585 sccr1_reg |= chip->threshold;
586 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
589 static void int_error_stop(struct driver_data *drv_data, const char* msg)
591 /* Stop and reset SSP */
592 write_SSSR_CS(drv_data, drv_data->clear_sr);
593 reset_sccr1(drv_data);
594 if (!pxa25x_ssp_comp(drv_data))
595 pxa2xx_spi_write(drv_data, SSTO, 0);
596 pxa2xx_spi_flush(drv_data);
597 pxa2xx_spi_write(drv_data, SSCR0,
598 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
600 dev_err(&drv_data->pdev->dev, "%s\n", msg);
602 drv_data->controller->cur_msg->status = -EIO;
603 spi_finalize_current_transfer(drv_data->controller);
606 static void int_transfer_complete(struct driver_data *drv_data)
608 /* Clear and disable interrupts */
609 write_SSSR_CS(drv_data, drv_data->clear_sr);
610 reset_sccr1(drv_data);
611 if (!pxa25x_ssp_comp(drv_data))
612 pxa2xx_spi_write(drv_data, SSTO, 0);
614 spi_finalize_current_transfer(drv_data->controller);
617 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
619 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
620 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
622 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
624 if (irq_status & SSSR_ROR) {
625 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
629 if (irq_status & SSSR_TUR) {
630 int_error_stop(drv_data, "interrupt_transfer: fifo underrun");
634 if (irq_status & SSSR_TINT) {
635 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
636 if (drv_data->read(drv_data)) {
637 int_transfer_complete(drv_data);
642 /* Drain rx fifo, Fill tx fifo and prevent overruns */
644 if (drv_data->read(drv_data)) {
645 int_transfer_complete(drv_data);
648 } while (drv_data->write(drv_data));
650 if (drv_data->read(drv_data)) {
651 int_transfer_complete(drv_data);
655 if (drv_data->tx == drv_data->tx_end) {
659 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
660 sccr1_reg &= ~SSCR1_TIE;
663 * PXA25x_SSP has no timeout, set up rx threshould for the
664 * remaining RX bytes.
666 if (pxa25x_ssp_comp(drv_data)) {
669 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
671 bytes_left = drv_data->rx_end - drv_data->rx;
672 switch (drv_data->n_bytes) {
681 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
682 if (rx_thre > bytes_left)
683 rx_thre = bytes_left;
685 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
687 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
690 /* We did something */
694 static void handle_bad_msg(struct driver_data *drv_data)
696 pxa2xx_spi_write(drv_data, SSCR0,
697 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
698 pxa2xx_spi_write(drv_data, SSCR1,
699 pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
700 if (!pxa25x_ssp_comp(drv_data))
701 pxa2xx_spi_write(drv_data, SSTO, 0);
702 write_SSSR_CS(drv_data, drv_data->clear_sr);
704 dev_err(&drv_data->pdev->dev,
705 "bad message state in interrupt handler\n");
708 static irqreturn_t ssp_int(int irq, void *dev_id)
710 struct driver_data *drv_data = dev_id;
712 u32 mask = drv_data->mask_sr;
716 * The IRQ might be shared with other peripherals so we must first
717 * check that are we RPM suspended or not. If we are we assume that
718 * the IRQ was not for us (we shouldn't be RPM suspended when the
719 * interrupt is enabled).
721 if (pm_runtime_suspended(&drv_data->pdev->dev))
725 * If the device is not yet in RPM suspended state and we get an
726 * interrupt that is meant for another device, check if status bits
727 * are all set to one. That means that the device is already
730 status = pxa2xx_spi_read(drv_data, SSSR);
734 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
736 /* Ignore possible writes if we don't need to write */
737 if (!(sccr1_reg & SSCR1_TIE))
740 /* Ignore RX timeout interrupt if it is disabled */
741 if (!(sccr1_reg & SSCR1_TINTE))
744 if (!(status & mask))
747 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
748 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
750 if (!drv_data->controller->cur_msg) {
751 handle_bad_msg(drv_data);
756 return drv_data->transfer_handler(drv_data);
760 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
761 * input frequency by fractions of 2^24. It also has a divider by 5.
763 * There are formulas to get baud rate value for given input frequency and
764 * divider parameters, such as DDS_CLK_RATE and SCR:
768 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
769 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
771 * DDS_CLK_RATE either 2^n or 2^n / 5.
772 * SCR is in range 0 .. 255
774 * Divisor = 5^i * 2^j * 2 * k
775 * i = [0, 1] i = 1 iff j = 0 or j > 3
776 * j = [0, 23] j = 0 iff i = 1
778 * Special case: j = 0, i = 1: Divisor = 2 / 5
780 * Accordingly to the specification the recommended values for DDS_CLK_RATE
782 * Case 1: 2^n, n = [0, 23]
783 * Case 2: 2^24 * 2 / 5 (0x666666)
784 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
786 * In all cases the lowest possible value is better.
788 * The function calculates parameters for all cases and chooses the one closest
789 * to the asked baud rate.
791 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
793 unsigned long xtal = 200000000;
794 unsigned long fref = xtal / 2; /* mandatory division by 2,
797 unsigned long fref1 = fref / 2; /* case 1 */
798 unsigned long fref2 = fref * 2 / 5; /* case 2 */
800 unsigned long q, q1, q2;
806 /* Set initial value for DDS_CLK_RATE */
807 mul = (1 << 24) >> 1;
809 /* Calculate initial quot */
810 q1 = DIV_ROUND_UP(fref1, rate);
812 /* Scale q1 if it's too big */
814 /* Scale q1 to range [1, 512] */
815 scale = fls_long(q1 - 1);
821 /* Round the result if we have a remainder */
825 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
830 /* Get the remainder */
831 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
835 q2 = DIV_ROUND_UP(fref2, rate);
836 r2 = abs(fref2 / q2 - rate);
839 * Choose the best between two: less remainder we have the better. We
840 * can't go case 2 if q2 is greater than 256 since SCR register can
841 * hold only values 0 .. 255.
843 if (r2 >= r1 || q2 > 256) {
844 /* case 1 is better */
848 /* case 2 is better */
851 mul = (1 << 24) * 2 / 5;
854 /* Check case 3 only if the divisor is big enough */
855 if (fref / rate >= 80) {
859 /* Calculate initial quot */
860 q1 = DIV_ROUND_UP(fref, rate);
863 /* Get the remainder */
864 fssp = (u64)fref * m;
865 do_div(fssp, 1 << 24);
866 r1 = abs(fssp - rate);
868 /* Choose this one if it suits better */
870 /* case 3 is better */
880 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
882 unsigned long ssp_clk = drv_data->controller->max_speed_hz;
883 const struct ssp_device *ssp = drv_data->ssp;
885 rate = min_t(int, ssp_clk, rate);
887 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
888 return (ssp_clk / (2 * rate) - 1) & 0xff;
890 return (ssp_clk / rate - 1) & 0xfff;
893 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
896 struct chip_data *chip =
897 spi_get_ctldata(drv_data->controller->cur_msg->spi);
898 unsigned int clk_div;
900 switch (drv_data->ssp_type) {
901 case QUARK_X1000_SSP:
902 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
905 clk_div = ssp_get_clk_div(drv_data, rate);
911 static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
912 struct spi_device *spi,
913 struct spi_transfer *xfer)
915 struct chip_data *chip = spi_get_ctldata(spi);
917 return chip->enable_dma &&
918 xfer->len <= MAX_DMA_LEN &&
919 xfer->len >= chip->dma_burst_size;
922 static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
923 struct spi_device *spi,
924 struct spi_transfer *transfer)
926 struct driver_data *drv_data = spi_controller_get_devdata(controller);
927 struct spi_message *message = controller->cur_msg;
928 struct chip_data *chip = spi_get_ctldata(spi);
929 u32 dma_thresh = chip->dma_threshold;
930 u32 dma_burst = chip->dma_burst_size;
931 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
940 /* Check if we can DMA this transfer */
941 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
943 /* reject already-mapped transfers; PIO won't always work */
944 if (message->is_dma_mapped
945 || transfer->rx_dma || transfer->tx_dma) {
946 dev_err(&drv_data->pdev->dev,
947 "Mapped transfer length of %u is greater than %d\n",
948 transfer->len, MAX_DMA_LEN);
952 /* warn ... we force this to PIO mode */
953 dev_warn_ratelimited(&spi->dev,
954 "DMA disabled for transfer length %ld greater than %d\n",
955 (long)transfer->len, MAX_DMA_LEN);
958 /* Setup the transfer state based on the type of transfer */
959 if (pxa2xx_spi_flush(drv_data) == 0) {
960 dev_err(&drv_data->pdev->dev, "Flush failed\n");
963 drv_data->n_bytes = chip->n_bytes;
964 drv_data->tx = (void *)transfer->tx_buf;
965 drv_data->tx_end = drv_data->tx + transfer->len;
966 drv_data->rx = transfer->rx_buf;
967 drv_data->rx_end = drv_data->rx + transfer->len;
968 drv_data->write = drv_data->tx ? chip->write : null_writer;
969 drv_data->read = drv_data->rx ? chip->read : null_reader;
971 /* Change speed and bit per word on a per transfer */
972 bits = transfer->bits_per_word;
973 speed = transfer->speed_hz;
975 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
978 drv_data->n_bytes = 1;
979 drv_data->read = drv_data->read != null_reader ?
980 u8_reader : null_reader;
981 drv_data->write = drv_data->write != null_writer ?
982 u8_writer : null_writer;
983 } else if (bits <= 16) {
984 drv_data->n_bytes = 2;
985 drv_data->read = drv_data->read != null_reader ?
986 u16_reader : null_reader;
987 drv_data->write = drv_data->write != null_writer ?
988 u16_writer : null_writer;
989 } else if (bits <= 32) {
990 drv_data->n_bytes = 4;
991 drv_data->read = drv_data->read != null_reader ?
992 u32_reader : null_reader;
993 drv_data->write = drv_data->write != null_writer ?
994 u32_writer : null_writer;
997 * if bits/word is changed in dma mode, then must check the
998 * thresholds and burst also
1000 if (chip->enable_dma) {
1001 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1005 dev_warn_ratelimited(&spi->dev,
1006 "DMA burst size reduced to match bits_per_word\n");
1009 dma_mapped = controller->can_dma &&
1010 controller->can_dma(controller, spi, transfer) &&
1011 controller->cur_msg_mapped;
1014 /* Ensure we have the correct interrupt handler */
1015 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1017 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1021 /* Clear status and start DMA engine */
1022 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1023 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1025 pxa2xx_spi_dma_start(drv_data);
1027 /* Ensure we have the correct interrupt handler */
1028 drv_data->transfer_handler = interrupt_transfer;
1031 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1032 write_SSSR_CS(drv_data, drv_data->clear_sr);
1035 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1036 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1037 if (!pxa25x_ssp_comp(drv_data))
1038 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1039 controller->max_speed_hz
1040 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1041 dma_mapped ? "DMA" : "PIO");
1043 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1044 controller->max_speed_hz / 2
1045 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1046 dma_mapped ? "DMA" : "PIO");
1048 if (is_lpss_ssp(drv_data)) {
1049 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1050 != chip->lpss_rx_threshold)
1051 pxa2xx_spi_write(drv_data, SSIRF,
1052 chip->lpss_rx_threshold);
1053 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1054 != chip->lpss_tx_threshold)
1055 pxa2xx_spi_write(drv_data, SSITF,
1056 chip->lpss_tx_threshold);
1059 if (is_quark_x1000_ssp(drv_data) &&
1060 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1061 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1063 /* see if we need to reload the config registers */
1064 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1065 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1066 != (cr1 & change_mask)) {
1067 /* stop the SSP, and update the other bits */
1068 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1069 if (!pxa25x_ssp_comp(drv_data))
1070 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1071 /* first set CR1 without interrupt and service enables */
1072 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1073 /* restart the SSP */
1074 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1077 if (!pxa25x_ssp_comp(drv_data))
1078 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1081 if (drv_data->ssp_type == MMP2_SSP) {
1082 u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR)
1083 & SSSR_TFL_MASK) >> 8;
1086 /* On MMP2, flipping SSE doesn't to empty TXFIFO. */
1087 dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n",
1089 if (tx_level > transfer->len)
1090 tx_level = transfer->len;
1091 drv_data->tx += tx_level;
1095 if (spi_controller_is_slave(controller)) {
1096 while (drv_data->write(drv_data))
1098 if (drv_data->gpiod_ready) {
1099 gpiod_set_value(drv_data->gpiod_ready, 1);
1101 gpiod_set_value(drv_data->gpiod_ready, 0);
1106 * Release the data by enabling service requests and interrupts,
1107 * without changing any mode bits
1109 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1114 static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
1116 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1118 /* Stop and reset SSP */
1119 write_SSSR_CS(drv_data, drv_data->clear_sr);
1120 reset_sccr1(drv_data);
1121 if (!pxa25x_ssp_comp(drv_data))
1122 pxa2xx_spi_write(drv_data, SSTO, 0);
1123 pxa2xx_spi_flush(drv_data);
1124 pxa2xx_spi_write(drv_data, SSCR0,
1125 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1127 dev_dbg(&drv_data->pdev->dev, "transfer aborted\n");
1129 drv_data->controller->cur_msg->status = -EINTR;
1130 spi_finalize_current_transfer(drv_data->controller);
1135 static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1136 struct spi_message *msg)
1138 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1140 /* Disable the SSP */
1141 pxa2xx_spi_write(drv_data, SSCR0,
1142 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1143 /* Clear and disable interrupts and service requests */
1144 write_SSSR_CS(drv_data, drv_data->clear_sr);
1145 pxa2xx_spi_write(drv_data, SSCR1,
1146 pxa2xx_spi_read(drv_data, SSCR1)
1147 & ~(drv_data->int_cr1 | drv_data->dma_cr1));
1148 if (!pxa25x_ssp_comp(drv_data))
1149 pxa2xx_spi_write(drv_data, SSTO, 0);
1152 * Stop the DMA if running. Note DMA callback handler may have unset
1153 * the dma_running already, which is fine as stopping is not needed
1154 * then but we shouldn't rely this flag for anything else than
1155 * stopping. For instance to differentiate between PIO and DMA
1158 if (atomic_read(&drv_data->dma_running))
1159 pxa2xx_spi_dma_stop(drv_data);
1162 static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1164 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1166 /* Disable the SSP now */
1167 pxa2xx_spi_write(drv_data, SSCR0,
1168 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1173 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1174 struct pxa2xx_spi_chip *chip_info)
1176 struct driver_data *drv_data =
1177 spi_controller_get_devdata(spi->controller);
1178 struct gpio_desc *gpiod;
1184 if (drv_data->cs_gpiods) {
1185 gpiod = drv_data->cs_gpiods[spi->chip_select];
1187 chip->gpiod_cs = gpiod;
1188 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1189 gpiod_set_value(gpiod, chip->gpio_cs_inverted);
1195 if (chip_info == NULL)
1198 /* NOTE: setup() can be called multiple times, possibly with
1199 * different chip_info, release previously requested GPIO
1201 if (chip->gpiod_cs) {
1202 gpiod_put(chip->gpiod_cs);
1203 chip->gpiod_cs = NULL;
1206 /* If (*cs_control) is provided, ignore GPIO chip select */
1207 if (chip_info->cs_control) {
1208 chip->cs_control = chip_info->cs_control;
1212 if (gpio_is_valid(chip_info->gpio_cs)) {
1213 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1215 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1216 chip_info->gpio_cs);
1220 gpiod = gpio_to_desc(chip_info->gpio_cs);
1221 chip->gpiod_cs = gpiod;
1222 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1224 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
1230 static int setup(struct spi_device *spi)
1232 struct pxa2xx_spi_chip *chip_info;
1233 struct chip_data *chip;
1234 const struct lpss_config *config;
1235 struct driver_data *drv_data =
1236 spi_controller_get_devdata(spi->controller);
1237 uint tx_thres, tx_hi_thres, rx_thres;
1239 switch (drv_data->ssp_type) {
1240 case QUARK_X1000_SSP:
1241 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1243 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1246 tx_thres = TX_THRESH_CE4100_DFLT;
1248 rx_thres = RX_THRESH_CE4100_DFLT;
1256 config = lpss_get_config(drv_data);
1257 tx_thres = config->tx_threshold_lo;
1258 tx_hi_thres = config->tx_threshold_hi;
1259 rx_thres = config->rx_threshold;
1263 if (spi_controller_is_slave(drv_data->controller)) {
1267 tx_thres = TX_THRESH_DFLT;
1268 rx_thres = RX_THRESH_DFLT;
1273 /* Only alloc on first setup */
1274 chip = spi_get_ctldata(spi);
1276 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1280 if (drv_data->ssp_type == CE4100_SSP) {
1281 if (spi->chip_select > 4) {
1283 "failed setup: cs number must not be > 4.\n");
1288 chip->frm = spi->chip_select;
1290 chip->enable_dma = drv_data->controller_info->enable_dma;
1291 chip->timeout = TIMOUT_DFLT;
1294 /* protocol drivers may change the chip settings, so...
1295 * if chip_info exists, use it */
1296 chip_info = spi->controller_data;
1298 /* chip_info isn't always needed */
1301 if (chip_info->timeout)
1302 chip->timeout = chip_info->timeout;
1303 if (chip_info->tx_threshold)
1304 tx_thres = chip_info->tx_threshold;
1305 if (chip_info->tx_hi_threshold)
1306 tx_hi_thres = chip_info->tx_hi_threshold;
1307 if (chip_info->rx_threshold)
1308 rx_thres = chip_info->rx_threshold;
1309 chip->dma_threshold = 0;
1310 if (chip_info->enable_loopback)
1311 chip->cr1 = SSCR1_LBM;
1313 if (spi_controller_is_slave(drv_data->controller)) {
1314 chip->cr1 |= SSCR1_SCFR;
1315 chip->cr1 |= SSCR1_SCLKDIR;
1316 chip->cr1 |= SSCR1_SFRMDIR;
1317 chip->cr1 |= SSCR1_SPH;
1320 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1321 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1322 | SSITF_TxHiThresh(tx_hi_thres);
1324 /* set dma burst and threshold outside of chip_info path so that if
1325 * chip_info goes away after setting chip->enable_dma, the
1326 * burst and threshold can still respond to changes in bits_per_word */
1327 if (chip->enable_dma) {
1328 /* set up legal burst and threshold for dma */
1329 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1331 &chip->dma_burst_size,
1332 &chip->dma_threshold)) {
1334 "in setup: DMA burst size reduced to match bits_per_word\n");
1337 "in setup: DMA burst size set to %u\n",
1338 chip->dma_burst_size);
1341 switch (drv_data->ssp_type) {
1342 case QUARK_X1000_SSP:
1343 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1344 & QUARK_X1000_SSCR1_RFT)
1345 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1346 & QUARK_X1000_SSCR1_TFT);
1349 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1350 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1353 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1354 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1358 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1359 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1360 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1362 if (spi->mode & SPI_LOOP)
1363 chip->cr1 |= SSCR1_LBM;
1365 if (spi->bits_per_word <= 8) {
1367 chip->read = u8_reader;
1368 chip->write = u8_writer;
1369 } else if (spi->bits_per_word <= 16) {
1371 chip->read = u16_reader;
1372 chip->write = u16_writer;
1373 } else if (spi->bits_per_word <= 32) {
1375 chip->read = u32_reader;
1376 chip->write = u32_writer;
1379 spi_set_ctldata(spi, chip);
1381 if (drv_data->ssp_type == CE4100_SSP)
1384 return setup_cs(spi, chip, chip_info);
1387 static void cleanup(struct spi_device *spi)
1389 struct chip_data *chip = spi_get_ctldata(spi);
1390 struct driver_data *drv_data =
1391 spi_controller_get_devdata(spi->controller);
1396 if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
1398 gpiod_put(chip->gpiod_cs);
1403 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1404 { "INT33C0", LPSS_LPT_SSP },
1405 { "INT33C1", LPSS_LPT_SSP },
1406 { "INT3430", LPSS_LPT_SSP },
1407 { "INT3431", LPSS_LPT_SSP },
1408 { "80860F0E", LPSS_BYT_SSP },
1409 { "8086228E", LPSS_BSW_SSP },
1412 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1415 * PCI IDs of compound devices that integrate both host controller and private
1416 * integrated DMA engine. Please note these are not used in module
1417 * autoloading and probing in this module but matching the LPSS SSP type.
1419 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1421 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1422 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1424 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1425 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1427 { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1428 { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1430 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1431 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1432 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1434 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1435 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1436 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1438 { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
1439 { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
1440 { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
1442 { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
1443 { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
1444 { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
1446 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1447 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1448 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1450 { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
1451 { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
1452 { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
1454 { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
1455 { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
1456 { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
1460 static const struct of_device_id pxa2xx_spi_of_match[] = {
1461 { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1464 MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
1468 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1473 if (adev && adev->pnp.unique_id &&
1474 !kstrtouint(adev->pnp.unique_id, 0, &devid))
1479 #else /* !CONFIG_ACPI */
1481 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1486 #endif /* CONFIG_ACPI */
1491 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1493 struct device *dev = param;
1495 if (dev != chan->device->dev->parent)
1501 #endif /* CONFIG_PCI */
1503 static struct pxa2xx_spi_controller *
1504 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1506 struct pxa2xx_spi_controller *pdata;
1507 struct acpi_device *adev;
1508 struct ssp_device *ssp;
1509 struct resource *res;
1510 const struct acpi_device_id *adev_id = NULL;
1511 const struct pci_device_id *pcidev_id = NULL;
1512 const struct of_device_id *of_id = NULL;
1513 enum pxa_ssp_type type;
1515 adev = ACPI_COMPANION(&pdev->dev);
1517 if (pdev->dev.of_node)
1518 of_id = of_match_device(pdev->dev.driver->of_match_table,
1520 else if (dev_is_pci(pdev->dev.parent))
1521 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1522 to_pci_dev(pdev->dev.parent));
1524 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1530 type = (enum pxa_ssp_type)adev_id->driver_data;
1532 type = (enum pxa_ssp_type)pcidev_id->driver_data;
1534 type = (enum pxa_ssp_type)of_id->data;
1538 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1542 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1548 ssp->phys_base = res->start;
1549 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1550 if (IS_ERR(ssp->mmio_base))
1555 pdata->tx_param = pdev->dev.parent;
1556 pdata->rx_param = pdev->dev.parent;
1557 pdata->dma_filter = pxa2xx_spi_idma_filter;
1561 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1562 ssp->irq = platform_get_irq(pdev, 0);
1565 ssp->port_id = pxa2xx_spi_get_port_id(adev);
1567 pdata->is_slave = of_property_read_bool(pdev->dev.of_node, "spi-slave");
1568 pdata->num_chipselect = 1;
1569 pdata->enable_dma = true;
1570 pdata->dma_burst_size = 1;
1575 static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1578 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1580 if (has_acpi_companion(&drv_data->pdev->dev)) {
1581 switch (drv_data->ssp_type) {
1583 * For Atoms the ACPI DeviceSelection used by the Windows
1584 * driver starts from 1 instead of 0 so translate it here
1585 * to match what Linux expects.
1599 static int pxa2xx_spi_probe(struct platform_device *pdev)
1601 struct device *dev = &pdev->dev;
1602 struct pxa2xx_spi_controller *platform_info;
1603 struct spi_controller *controller;
1604 struct driver_data *drv_data;
1605 struct ssp_device *ssp;
1606 const struct lpss_config *config;
1610 platform_info = dev_get_platdata(dev);
1611 if (!platform_info) {
1612 platform_info = pxa2xx_spi_init_pdata(pdev);
1613 if (!platform_info) {
1614 dev_err(&pdev->dev, "missing platform data\n");
1619 ssp = pxa_ssp_request(pdev->id, pdev->name);
1621 ssp = &platform_info->ssp;
1623 if (!ssp->mmio_base) {
1624 dev_err(&pdev->dev, "failed to get ssp\n");
1628 if (platform_info->is_slave)
1629 controller = spi_alloc_slave(dev, sizeof(struct driver_data));
1631 controller = spi_alloc_master(dev, sizeof(struct driver_data));
1634 dev_err(&pdev->dev, "cannot alloc spi_controller\n");
1638 drv_data = spi_controller_get_devdata(controller);
1639 drv_data->controller = controller;
1640 drv_data->controller_info = platform_info;
1641 drv_data->pdev = pdev;
1642 drv_data->ssp = ssp;
1644 controller->dev.of_node = pdev->dev.of_node;
1645 /* the spi->mode bits understood by this driver: */
1646 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1648 controller->bus_num = ssp->port_id;
1649 controller->dma_alignment = DMA_ALIGNMENT;
1650 controller->cleanup = cleanup;
1651 controller->setup = setup;
1652 controller->set_cs = pxa2xx_spi_set_cs;
1653 controller->transfer_one = pxa2xx_spi_transfer_one;
1654 controller->slave_abort = pxa2xx_spi_slave_abort;
1655 controller->handle_err = pxa2xx_spi_handle_err;
1656 controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1657 controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1658 controller->auto_runtime_pm = true;
1659 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1661 drv_data->ssp_type = ssp->type;
1663 drv_data->ioaddr = ssp->mmio_base;
1664 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1665 if (pxa25x_ssp_comp(drv_data)) {
1666 switch (drv_data->ssp_type) {
1667 case QUARK_X1000_SSP:
1668 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1671 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1675 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1676 drv_data->dma_cr1 = 0;
1677 drv_data->clear_sr = SSSR_ROR;
1678 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1680 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1681 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1682 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1683 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1684 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1685 | SSSR_ROR | SSSR_TUR;
1688 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1691 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1692 goto out_error_controller_alloc;
1695 /* Setup DMA if requested */
1696 if (platform_info->enable_dma) {
1697 status = pxa2xx_spi_dma_setup(drv_data);
1699 dev_dbg(dev, "no DMA channels available, using PIO\n");
1700 platform_info->enable_dma = false;
1702 controller->can_dma = pxa2xx_spi_can_dma;
1703 controller->max_dma_len = MAX_DMA_LEN;
1707 /* Enable SOC clock */
1708 status = clk_prepare_enable(ssp->clk);
1710 goto out_error_dma_irq_alloc;
1712 controller->max_speed_hz = clk_get_rate(ssp->clk);
1714 /* Load default SSP configuration */
1715 pxa2xx_spi_write(drv_data, SSCR0, 0);
1716 switch (drv_data->ssp_type) {
1717 case QUARK_X1000_SSP:
1718 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1719 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1720 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1722 /* using the Motorola SPI protocol and use 8 bit frame */
1723 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1724 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1727 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1728 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1729 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1730 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1731 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1735 if (spi_controller_is_slave(controller)) {
1743 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1744 SSCR1_TxTresh(TX_THRESH_DFLT);
1746 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1747 tmp = SSCR0_Motorola | SSCR0_DataSize(8);
1748 if (!spi_controller_is_slave(controller))
1749 tmp |= SSCR0_SCR(2);
1750 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1754 if (!pxa25x_ssp_comp(drv_data))
1755 pxa2xx_spi_write(drv_data, SSTO, 0);
1757 if (!is_quark_x1000_ssp(drv_data))
1758 pxa2xx_spi_write(drv_data, SSPSP, 0);
1760 if (is_lpss_ssp(drv_data)) {
1761 lpss_ssp_setup(drv_data);
1762 config = lpss_get_config(drv_data);
1763 if (config->reg_capabilities >= 0) {
1764 tmp = __lpss_ssp_read_priv(drv_data,
1765 config->reg_capabilities);
1766 tmp &= LPSS_CAPS_CS_EN_MASK;
1767 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1768 platform_info->num_chipselect = ffz(tmp);
1769 } else if (config->cs_num) {
1770 platform_info->num_chipselect = config->cs_num;
1773 controller->num_chipselect = platform_info->num_chipselect;
1775 count = gpiod_count(&pdev->dev, "cs");
1779 controller->num_chipselect = max_t(int, count,
1780 controller->num_chipselect);
1782 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
1783 controller->num_chipselect, sizeof(struct gpio_desc *),
1785 if (!drv_data->cs_gpiods) {
1787 goto out_error_clock_enabled;
1790 for (i = 0; i < controller->num_chipselect; i++) {
1791 struct gpio_desc *gpiod;
1793 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1794 if (IS_ERR(gpiod)) {
1795 /* Means use native chip select */
1796 if (PTR_ERR(gpiod) == -ENOENT)
1799 status = PTR_ERR(gpiod);
1800 goto out_error_clock_enabled;
1802 drv_data->cs_gpiods[i] = gpiod;
1807 if (platform_info->is_slave) {
1808 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1809 "ready", GPIOD_OUT_LOW);
1810 if (IS_ERR(drv_data->gpiod_ready)) {
1811 status = PTR_ERR(drv_data->gpiod_ready);
1812 goto out_error_clock_enabled;
1816 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1817 pm_runtime_use_autosuspend(&pdev->dev);
1818 pm_runtime_set_active(&pdev->dev);
1819 pm_runtime_enable(&pdev->dev);
1821 /* Register with the SPI framework */
1822 platform_set_drvdata(pdev, drv_data);
1823 status = devm_spi_register_controller(&pdev->dev, controller);
1825 dev_err(&pdev->dev, "problem registering spi controller\n");
1826 goto out_error_clock_enabled;
1831 out_error_clock_enabled:
1832 pm_runtime_put_noidle(&pdev->dev);
1833 pm_runtime_disable(&pdev->dev);
1834 clk_disable_unprepare(ssp->clk);
1836 out_error_dma_irq_alloc:
1837 pxa2xx_spi_dma_release(drv_data);
1838 free_irq(ssp->irq, drv_data);
1840 out_error_controller_alloc:
1841 spi_controller_put(controller);
1846 static int pxa2xx_spi_remove(struct platform_device *pdev)
1848 struct driver_data *drv_data = platform_get_drvdata(pdev);
1849 struct ssp_device *ssp;
1853 ssp = drv_data->ssp;
1855 pm_runtime_get_sync(&pdev->dev);
1857 /* Disable the SSP at the peripheral and SOC level */
1858 pxa2xx_spi_write(drv_data, SSCR0, 0);
1859 clk_disable_unprepare(ssp->clk);
1862 if (drv_data->controller_info->enable_dma)
1863 pxa2xx_spi_dma_release(drv_data);
1865 pm_runtime_put_noidle(&pdev->dev);
1866 pm_runtime_disable(&pdev->dev);
1869 free_irq(ssp->irq, drv_data);
1877 #ifdef CONFIG_PM_SLEEP
1878 static int pxa2xx_spi_suspend(struct device *dev)
1880 struct driver_data *drv_data = dev_get_drvdata(dev);
1881 struct ssp_device *ssp = drv_data->ssp;
1884 status = spi_controller_suspend(drv_data->controller);
1887 pxa2xx_spi_write(drv_data, SSCR0, 0);
1889 if (!pm_runtime_suspended(dev))
1890 clk_disable_unprepare(ssp->clk);
1895 static int pxa2xx_spi_resume(struct device *dev)
1897 struct driver_data *drv_data = dev_get_drvdata(dev);
1898 struct ssp_device *ssp = drv_data->ssp;
1901 /* Enable the SSP clock */
1902 if (!pm_runtime_suspended(dev)) {
1903 status = clk_prepare_enable(ssp->clk);
1908 /* Start the queue running */
1909 return spi_controller_resume(drv_data->controller);
1914 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1916 struct driver_data *drv_data = dev_get_drvdata(dev);
1918 clk_disable_unprepare(drv_data->ssp->clk);
1922 static int pxa2xx_spi_runtime_resume(struct device *dev)
1924 struct driver_data *drv_data = dev_get_drvdata(dev);
1927 status = clk_prepare_enable(drv_data->ssp->clk);
1932 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1933 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1934 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1935 pxa2xx_spi_runtime_resume, NULL)
1938 static struct platform_driver driver = {
1940 .name = "pxa2xx-spi",
1941 .pm = &pxa2xx_spi_pm_ops,
1942 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1943 .of_match_table = of_match_ptr(pxa2xx_spi_of_match),
1945 .probe = pxa2xx_spi_probe,
1946 .remove = pxa2xx_spi_remove,
1949 static int __init pxa2xx_spi_init(void)
1951 return platform_driver_register(&driver);
1953 subsys_initcall(pxa2xx_spi_init);
1955 static void __exit pxa2xx_spi_exit(void)
1957 platform_driver_unregister(&driver);
1959 module_exit(pxa2xx_spi_exit);