drivers/spi/spi-pxa2xx.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   4  * Copyright (C) 2013, Intel Corporation
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/bitops.h>
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/device.h>
  12 #include <linux/err.h>
  13 #include <linux/errno.h>
  14 #include <linux/gpio/consumer.h>
  15 #include <linux/gpio.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/ioport.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/mod_devicetable.h>
  22 #include <linux/of.h>
  23 #include <linux/pci.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/property.h>
  27 #include <linux/slab.h>
  28 #include <linux/spi/pxa2xx_spi.h>
  29 #include <linux/spi/spi.h>
  30
  31 #include "spi-pxa2xx.h"
  32
  33 MODULE_AUTHOR("Stephen Street");
  34 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
  35 MODULE_LICENSE("GPL");
  36 MODULE_ALIAS("platform:pxa2xx-spi");
  37
  38 #define TIMOUT_DFLT             1000
  39
  40 /*
  41  * for testing SSCR1 changes that require SSP restart, basically
  42  * everything except the service and interrupt enables, the pxa270 developer
  43  * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
  44  * list, but the PXA255 dev man says all bits without really meaning the
  45  * service and interrupt enables
  46  */
  47 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  48                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  49                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  50                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  51                                 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
  52                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  53
  54 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF   \
  55                                 | QUARK_X1000_SSCR1_EFWR        \
  56                                 | QUARK_X1000_SSCR1_RFT         \
  57                                 | QUARK_X1000_SSCR1_TFT         \
  58                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  59
  60 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  61                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  62                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  63                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  64                                 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
  65                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  66
  67 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE   BIT(24)
  68 #define LPSS_CS_CONTROL_SW_MODE                 BIT(0)
  69 #define LPSS_CS_CONTROL_CS_HIGH                 BIT(1)
  70 #define LPSS_CAPS_CS_EN_SHIFT                   9
  71 #define LPSS_CAPS_CS_EN_MASK                    (0xf << LPSS_CAPS_CS_EN_SHIFT)
  72
  73 struct lpss_config {
  74         /* LPSS offset from drv_data->ioaddr */
  75         unsigned offset;
  76         /* Register offsets from drv_data->lpss_base or -1 */
  77         int reg_general;
  78         int reg_ssp;
  79         int reg_cs_ctrl;
  80         int reg_capabilities;
  81         /* FIFO thresholds */
  82         u32 rx_threshold;
  83         u32 tx_threshold_lo;
  84         u32 tx_threshold_hi;
  85         /* Chip select control */
  86         unsigned cs_sel_shift;
  87         unsigned cs_sel_mask;
  88         unsigned cs_num;
  89 };
  90
  91 /* Keep these sorted with enum pxa_ssp_type */
  92 static const struct lpss_config lpss_platforms[] = {
  93         {       /* LPSS_LPT_SSP */
  94                 .offset = 0x800,
  95                 .reg_general = 0x08,
  96                 .reg_ssp = 0x0c,
  97                 .reg_cs_ctrl = 0x18,
  98                 .reg_capabilities = -1,
  99                 .rx_threshold = 64,
 100                 .tx_threshold_lo = 160,
 101                 .tx_threshold_hi = 224,
 102         },
 103         {       /* LPSS_BYT_SSP */
 104                 .offset = 0x400,
 105                 .reg_general = 0x08,
 106                 .reg_ssp = 0x0c,
 107                 .reg_cs_ctrl = 0x18,
 108                 .reg_capabilities = -1,
 109                 .rx_threshold = 64,
 110                 .tx_threshold_lo = 160,
 111                 .tx_threshold_hi = 224,
 112         },
 113         {       /* LPSS_BSW_SSP */
 114                 .offset = 0x400,
 115                 .reg_general = 0x08,
 116                 .reg_ssp = 0x0c,
 117                 .reg_cs_ctrl = 0x18,
 118                 .reg_capabilities = -1,
 119                 .rx_threshold = 64,
 120                 .tx_threshold_lo = 160,
 121                 .tx_threshold_hi = 224,
 122                 .cs_sel_shift = 2,
 123                 .cs_sel_mask = 1 << 2,
 124                 .cs_num = 2,
 125         },
 126         {       /* LPSS_SPT_SSP */
 127                 .offset = 0x200,
 128                 .reg_general = -1,
 129                 .reg_ssp = 0x20,
 130                 .reg_cs_ctrl = 0x24,
 131                 .reg_capabilities = -1,
 132                 .rx_threshold = 1,
 133                 .tx_threshold_lo = 32,
 134                 .tx_threshold_hi = 56,
 135         },
 136         {       /* LPSS_BXT_SSP */
 137                 .offset = 0x200,
 138                 .reg_general = -1,
 139                 .reg_ssp = 0x20,
 140                 .reg_cs_ctrl = 0x24,
 141                 .reg_capabilities = 0xfc,
 142                 .rx_threshold = 1,
 143                 .tx_threshold_lo = 16,
 144                 .tx_threshold_hi = 48,
 145                 .cs_sel_shift = 8,
 146                 .cs_sel_mask = 3 << 8,
 147         },
 148         {       /* LPSS_CNL_SSP */
 149                 .offset = 0x200,
 150                 .reg_general = -1,
 151                 .reg_ssp = 0x20,
 152                 .reg_cs_ctrl = 0x24,
 153                 .reg_capabilities = 0xfc,
 154                 .rx_threshold = 1,
 155                 .tx_threshold_lo = 32,
 156                 .tx_threshold_hi = 56,
 157                 .cs_sel_shift = 8,
 158                 .cs_sel_mask = 3 << 8,
 159         },
 160 };
 161
 162 static inline const struct lpss_config
 163 *lpss_get_config(const struct driver_data *drv_data)
 164 {
 165         return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
 166 }
 167
 168 static bool is_lpss_ssp(const struct driver_data *drv_data)
 169 {
 170         switch (drv_data->ssp_type) {
 171         case LPSS_LPT_SSP:
 172         case LPSS_BYT_SSP:
 173         case LPSS_BSW_SSP:
 174         case LPSS_SPT_SSP:
 175         case LPSS_BXT_SSP:
 176         case LPSS_CNL_SSP:
 177                 return true;
 178         default:
 179                 return false;
 180         }
 181 }
 182
 183 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
 184 {
 185         return drv_data->ssp_type == QUARK_X1000_SSP;
 186 }
 187
 188 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
 189 {
 190         switch (drv_data->ssp_type) {
 191         case QUARK_X1000_SSP:
 192                 return QUARK_X1000_SSCR1_CHANGE_MASK;
 193         case CE4100_SSP:
 194                 return CE4100_SSCR1_CHANGE_MASK;
 195         default:
 196                 return SSCR1_CHANGE_MASK;
 197         }
 198 }
 199
 200 static u32
 201 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
 202 {
 203         switch (drv_data->ssp_type) {
 204         case QUARK_X1000_SSP:
 205                 return RX_THRESH_QUARK_X1000_DFLT;
 206         case CE4100_SSP:
 207                 return RX_THRESH_CE4100_DFLT;
 208         default:
 209                 return RX_THRESH_DFLT;
 210         }
 211 }
 212
 213 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
 214 {
 215         u32 mask;
 216
 217         switch (drv_data->ssp_type) {
 218         case QUARK_X1000_SSP:
 219                 mask = QUARK_X1000_SSSR_TFL_MASK;
 220                 break;
 221         case CE4100_SSP:
 222                 mask = CE4100_SSSR_TFL_MASK;
 223                 break;
 224         default:
 225                 mask = SSSR_TFL_MASK;
 226                 break;
 227         }
 228
 229         return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
 230 }
 231
 232 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
 233                                      u32 *sccr1_reg)
 234 {
 235         u32 mask;
 236
 237         switch (drv_data->ssp_type) {
 238         case QUARK_X1000_SSP:
 239                 mask = QUARK_X1000_SSCR1_RFT;
 240                 break;
 241         case CE4100_SSP:
 242                 mask = CE4100_SSCR1_RFT;
 243                 break;
 244         default:
 245                 mask = SSCR1_RFT;
 246                 break;
 247         }
 248         *sccr1_reg &= ~mask;
 249 }
 250
 251 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
 252                                    u32 *sccr1_reg, u32 threshold)
 253 {
 254         switch (drv_data->ssp_type) {
 255         case QUARK_X1000_SSP:
 256                 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
 257                 break;
 258         case CE4100_SSP:
 259                 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
 260                 break;
 261         default:
 262                 *sccr1_reg |= SSCR1_RxTresh(threshold);
 263                 break;
 264         }
 265 }
 266
 267 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
 268                                   u32 clk_div, u8 bits)
 269 {
 270         switch (drv_data->ssp_type) {
 271         case QUARK_X1000_SSP:
 272                 return clk_div
 273                         | QUARK_X1000_SSCR0_Motorola
 274                         | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
 275                         | SSCR0_SSE;
 276         default:
 277                 return clk_div
 278                         | SSCR0_Motorola
 279                         | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
 280                         | SSCR0_SSE
 281                         | (bits > 16 ? SSCR0_EDSS : 0);
 282         }
 283 }
 284
 285 /*
 286  * Read and write LPSS SSP private registers. Caller must first check that
 287  * is_lpss_ssp() returns true before these can be called.
 288  */
 289 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
 290 {
 291         WARN_ON(!drv_data->lpss_base);
 292         return readl(drv_data->lpss_base + offset);
 293 }
 294
 295 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
 296                                   unsigned offset, u32 value)
 297 {
 298         WARN_ON(!drv_data->lpss_base);
 299         writel(value, drv_data->lpss_base + offset);
 300 }
 301
 302 /*
 303  * lpss_ssp_setup - perform LPSS SSP specific setup
 304  * @drv_data: pointer to the driver private data
 305  *
 306  * Perform LPSS SSP specific setup. This function must be called first if
 307  * one is going to use LPSS SSP private registers.
 308  */
 309 static void lpss_ssp_setup(struct driver_data *drv_data)
 310 {
 311         const struct lpss_config *config;
 312         u32 value;
 313
 314         config = lpss_get_config(drv_data);
 315         drv_data->lpss_base = drv_data->ioaddr + config->offset;
 316
 317         /* Enable software chip select control */
 318         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 319         value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
 320         value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
 321         __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 322
 323         /* Enable multiblock DMA transfers */
 324         if (drv_data->controller_info->enable_dma) {
 325                 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
 326
 327                 if (config->reg_general >= 0) {
 328                         value = __lpss_ssp_read_priv(drv_data,
 329                                                      config->reg_general);
 330                         value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
 331                         __lpss_ssp_write_priv(drv_data,
 332                                               config->reg_general, value);
 333                 }
 334         }
 335 }
 336
 337 static void lpss_ssp_select_cs(struct spi_device *spi,
 338                                const struct lpss_config *config)
 339 {
 340         struct driver_data *drv_data =
 341                 spi_controller_get_devdata(spi->controller);
 342         u32 value, cs;
 343
 344         if (!config->cs_sel_mask)
 345                 return;
 346
 347         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 348
 349         cs = spi->chip_select;
 350         cs <<= config->cs_sel_shift;
 351         if (cs != (value & config->cs_sel_mask)) {
 352                 /*
 353                  * When switching another chip select output active the
 354                  * output must be selected first and wait 2 ssp_clk cycles
 355                  * before changing state to active. Otherwise a short
 356                  * glitch will occur on the previous chip select since
 357                  * output select is latched but state control is not.
 358                  */
 359                 value &= ~config->cs_sel_mask;
 360                 value |= cs;
 361                 __lpss_ssp_write_priv(drv_data,
 362                                       config->reg_cs_ctrl, value);
 363                 ndelay(1000000000 /
 364                        (drv_data->controller->max_speed_hz / 2));
 365         }
 366 }
 367
 368 static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
 369 {
 370         struct driver_data *drv_data =
 371                 spi_controller_get_devdata(spi->controller);
 372         const struct lpss_config *config;
 373         u32 value;
 374
 375         config = lpss_get_config(drv_data);
 376
 377         if (enable)
 378                 lpss_ssp_select_cs(spi, config);
 379
 380         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 381         if (enable)
 382                 value &= ~LPSS_CS_CONTROL_CS_HIGH;
 383         else
 384                 value |= LPSS_CS_CONTROL_CS_HIGH;
 385         __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 386 }
 387
 388 static void cs_assert(struct spi_device *spi)
 389 {
 390         struct chip_data *chip = spi_get_ctldata(spi);
 391         struct driver_data *drv_data =
 392                 spi_controller_get_devdata(spi->controller);
 393
 394         if (drv_data->ssp_type == CE4100_SSP) {
 395                 pxa2xx_spi_write(drv_data, SSSR, chip->frm);
 396                 return;
 397         }
 398
 399         if (chip->cs_control) {
 400                 chip->cs_control(PXA2XX_CS_ASSERT);
 401                 return;
 402         }
 403
 404         if (chip->gpiod_cs) {
 405                 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
 406                 return;
 407         }
 408
 409         if (is_lpss_ssp(drv_data))
 410                 lpss_ssp_cs_control(spi, true);
 411 }
 412
 413 static void cs_deassert(struct spi_device *spi)
 414 {
 415         struct chip_data *chip = spi_get_ctldata(spi);
 416         struct driver_data *drv_data =
 417                 spi_controller_get_devdata(spi->controller);
 418         unsigned long timeout;
 419
 420         if (drv_data->ssp_type == CE4100_SSP)
 421                 return;
 422
 423         /* Wait until SSP becomes idle before deasserting the CS */
 424         timeout = jiffies + msecs_to_jiffies(10);
 425         while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
 426                !time_after(jiffies, timeout))
 427                 cpu_relax();
 428
 429         if (chip->cs_control) {
 430                 chip->cs_control(PXA2XX_CS_DEASSERT);
 431                 return;
 432         }
 433
 434         if (chip->gpiod_cs) {
 435                 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
 436                 return;
 437         }
 438
 439         if (is_lpss_ssp(drv_data))
 440                 lpss_ssp_cs_control(spi, false);
 441 }
 442
 443 static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
 444 {
 445         if (level)
 446                 cs_deassert(spi);
 447         else
 448                 cs_assert(spi);
 449 }
 450
 451 int pxa2xx_spi_flush(struct driver_data *drv_data)
 452 {
 453         unsigned long limit = loops_per_jiffy << 1;
 454
 455         do {
 456                 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 457                         pxa2xx_spi_read(drv_data, SSDR);
 458         } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
 459         write_SSSR_CS(drv_data, SSSR_ROR);
 460
 461         return limit;
 462 }
 463
 464 static void pxa2xx_spi_off(struct driver_data *drv_data)
 465 {
 466         /* On MMP, disabling SSE seems to corrupt the rx fifo */
 467         if (drv_data->ssp_type == MMP2_SSP)
 468                 return;
 469
 470         pxa2xx_spi_write(drv_data, SSCR0,
 471                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
 472 }
 473
 474 static int null_writer(struct driver_data *drv_data)
 475 {
 476         u8 n_bytes = drv_data->n_bytes;
 477
 478         if (pxa2xx_spi_txfifo_full(drv_data)
 479                 || (drv_data->tx == drv_data->tx_end))
 480                 return 0;
 481
 482         pxa2xx_spi_write(drv_data, SSDR, 0);
 483         drv_data->tx += n_bytes;
 484
 485         return 1;
 486 }
 487
 488 static int null_reader(struct driver_data *drv_data)
 489 {
 490         u8 n_bytes = drv_data->n_bytes;
 491
 492         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 493                && (drv_data->rx < drv_data->rx_end)) {
 494                 pxa2xx_spi_read(drv_data, SSDR);
 495                 drv_data->rx += n_bytes;
 496         }
 497
 498         return drv_data->rx == drv_data->rx_end;
 499 }
 500
 501 static int u8_writer(struct driver_data *drv_data)
 502 {
 503         if (pxa2xx_spi_txfifo_full(drv_data)
 504                 || (drv_data->tx == drv_data->tx_end))
 505                 return 0;
 506
 507         pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
 508         ++drv_data->tx;
 509
 510         return 1;
 511 }
 512
 513 static int u8_reader(struct driver_data *drv_data)
 514 {
 515         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 516                && (drv_data->rx < drv_data->rx_end)) {
 517                 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 518                 ++drv_data->rx;
 519         }
 520
 521         return drv_data->rx == drv_data->rx_end;
 522 }
 523
 524 static int u16_writer(struct driver_data *drv_data)
 525 {
 526         if (pxa2xx_spi_txfifo_full(drv_data)
 527                 || (drv_data->tx == drv_data->tx_end))
 528                 return 0;
 529
 530         pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
 531         drv_data->tx += 2;
 532
 533         return 1;
 534 }
 535
 536 static int u16_reader(struct driver_data *drv_data)
 537 {
 538         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 539                && (drv_data->rx < drv_data->rx_end)) {
 540                 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 541                 drv_data->rx += 2;
 542         }
 543
 544         return drv_data->rx == drv_data->rx_end;
 545 }
 546
 547 static int u32_writer(struct driver_data *drv_data)
 548 {
 549         if (pxa2xx_spi_txfifo_full(drv_data)
 550                 || (drv_data->tx == drv_data->tx_end))
 551                 return 0;
 552
 553         pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
 554         drv_data->tx += 4;
 555
 556         return 1;
 557 }
 558
 559 static int u32_reader(struct driver_data *drv_data)
 560 {
 561         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 562                && (drv_data->rx < drv_data->rx_end)) {
 563                 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 564                 drv_data->rx += 4;
 565         }
 566
 567         return drv_data->rx == drv_data->rx_end;
 568 }
 569
 570 static void reset_sccr1(struct driver_data *drv_data)
 571 {
 572         struct chip_data *chip =
 573                 spi_get_ctldata(drv_data->controller->cur_msg->spi);
 574         u32 sccr1_reg;
 575
 576         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
 577         switch (drv_data->ssp_type) {
 578         case QUARK_X1000_SSP:
 579                 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
 580                 break;
 581         case CE4100_SSP:
 582                 sccr1_reg &= ~CE4100_SSCR1_RFT;
 583                 break;
 584         default:
 585                 sccr1_reg &= ~SSCR1_RFT;
 586                 break;
 587         }
 588         sccr1_reg |= chip->threshold;
 589         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 590 }
 591
 592 static void int_error_stop(struct driver_data *drv_data, const char* msg)
 593 {
 594         /* Stop and reset SSP */
 595         write_SSSR_CS(drv_data, drv_data->clear_sr);
 596         reset_sccr1(drv_data);
 597         if (!pxa25x_ssp_comp(drv_data))
 598                 pxa2xx_spi_write(drv_data, SSTO, 0);
 599         pxa2xx_spi_flush(drv_data);
 600         pxa2xx_spi_off(drv_data);
 601
 602         dev_err(&drv_data->pdev->dev, "%s\n", msg);
 603
 604         drv_data->controller->cur_msg->status = -EIO;
 605         spi_finalize_current_transfer(drv_data->controller);
 606 }
 607
 608 static void int_transfer_complete(struct driver_data *drv_data)
 609 {
 610         /* Clear and disable interrupts */
 611         write_SSSR_CS(drv_data, drv_data->clear_sr);
 612         reset_sccr1(drv_data);
 613         if (!pxa25x_ssp_comp(drv_data))
 614                 pxa2xx_spi_write(drv_data, SSTO, 0);
 615
 616         spi_finalize_current_transfer(drv_data->controller);
 617 }
 618
 619 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
 620 {
 621         u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
 622                        drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
 623
 624         u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
 625
 626         if (irq_status & SSSR_ROR) {
 627                 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
 628                 return IRQ_HANDLED;
 629         }
 630
 631         if (irq_status & SSSR_TUR) {
 632                 int_error_stop(drv_data, "interrupt_transfer: fifo underrun");
 633                 return IRQ_HANDLED;
 634         }
 635
 636         if (irq_status & SSSR_TINT) {
 637                 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
 638                 if (drv_data->read(drv_data)) {
 639                         int_transfer_complete(drv_data);
 640                         return IRQ_HANDLED;
 641                 }
 642         }
 643
 644         /* Drain rx fifo, Fill tx fifo and prevent overruns */
 645         do {
 646                 if (drv_data->read(drv_data)) {
 647                         int_transfer_complete(drv_data);
 648                         return IRQ_HANDLED;
 649                 }
 650         } while (drv_data->write(drv_data));
 651
 652         if (drv_data->read(drv_data)) {
 653                 int_transfer_complete(drv_data);
 654                 return IRQ_HANDLED;
 655         }
 656
 657         if (drv_data->tx == drv_data->tx_end) {
 658                 u32 bytes_left;
 659                 u32 sccr1_reg;
 660
 661                 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
 662                 sccr1_reg &= ~SSCR1_TIE;
 663
 664                 /*
 665                  * PXA25x_SSP has no timeout, set up rx threshould for the
 666                  * remaining RX bytes.
 667                  */
 668                 if (pxa25x_ssp_comp(drv_data)) {
 669                         u32 rx_thre;
 670
 671                         pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
 672
 673                         bytes_left = drv_data->rx_end - drv_data->rx;
 674                         switch (drv_data->n_bytes) {
 675                         case 4:
 676                                 bytes_left >>= 2;
 677                                 break;
 678                         case 2:
 679                                 bytes_left >>= 1;
 680                                 break;
 681                         }
 682
 683                         rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
 684                         if (rx_thre > bytes_left)
 685                                 rx_thre = bytes_left;
 686
 687                         pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
 688                 }
 689                 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 690         }
 691
 692         /* We did something */
 693         return IRQ_HANDLED;
 694 }
 695
 696 static void handle_bad_msg(struct driver_data *drv_data)
 697 {
 698         pxa2xx_spi_off(drv_data);
 699         pxa2xx_spi_write(drv_data, SSCR1,
 700                          pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
 701         if (!pxa25x_ssp_comp(drv_data))
 702                 pxa2xx_spi_write(drv_data, SSTO, 0);
 703         write_SSSR_CS(drv_data, drv_data->clear_sr);
 704
 705         dev_err(&drv_data->pdev->dev,
 706                 "bad message state in interrupt handler\n");
 707 }
 708
 709 static irqreturn_t ssp_int(int irq, void *dev_id)
 710 {
 711         struct driver_data *drv_data = dev_id;
 712         u32 sccr1_reg;
 713         u32 mask = drv_data->mask_sr;
 714         u32 status;
 715
 716         /*
 717          * The IRQ might be shared with other peripherals so we must first
 718          * check that are we RPM suspended or not. If we are we assume that
 719          * the IRQ was not for us (we shouldn't be RPM suspended when the
 720          * interrupt is enabled).
 721          */
 722         if (pm_runtime_suspended(&drv_data->pdev->dev))
 723                 return IRQ_NONE;
 724
 725         /*
 726          * If the device is not yet in RPM suspended state and we get an
 727          * interrupt that is meant for another device, check if status bits
 728          * are all set to one. That means that the device is already
 729          * powered off.
 730          */
 731         status = pxa2xx_spi_read(drv_data, SSSR);
 732         if (status == ~0)
 733                 return IRQ_NONE;
 734
 735         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
 736
 737         /* Ignore possible writes if we don't need to write */
 738         if (!(sccr1_reg & SSCR1_TIE))
 739                 mask &= ~SSSR_TFS;
 740
 741         /* Ignore RX timeout interrupt if it is disabled */
 742         if (!(sccr1_reg & SSCR1_TINTE))
 743                 mask &= ~SSSR_TINT;
 744
 745         if (!(status & mask))
 746                 return IRQ_NONE;
 747
 748         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
 749         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 750
 751         if (!drv_data->controller->cur_msg) {
 752                 handle_bad_msg(drv_data);
 753                 /* Never fail */
 754                 return IRQ_HANDLED;
 755         }
 756
 757         return drv_data->transfer_handler(drv_data);
 758 }
 759
 760 /*
 761  * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
 762  * input frequency by fractions of 2^24. It also has a divider by 5.
 763  *
 764  * There are formulas to get baud rate value for given input frequency and
 765  * divider parameters, such as DDS_CLK_RATE and SCR:
 766  *
 767  * Fsys = 200MHz
 768  *
 769  * Fssp = Fsys * DDS_CLK_RATE / 2^24                    (1)
 770  * Baud rate = Fsclk = Fssp / (2 * (SCR + 1))           (2)
 771  *
 772  * DDS_CLK_RATE either 2^n or 2^n / 5.
 773  * SCR is in range 0 .. 255
 774  *
 775  * Divisor = 5^i * 2^j * 2 * k
 776  *       i = [0, 1]      i = 1 iff j = 0 or j > 3
 777  *       j = [0, 23]     j = 0 iff i = 1
 778  *       k = [1, 256]
 779  * Special case: j = 0, i = 1: Divisor = 2 / 5
 780  *
 781  * Accordingly to the specification the recommended values for DDS_CLK_RATE
 782  * are:
 783  *      Case 1:         2^n, n = [0, 23]
 784  *      Case 2:         2^24 * 2 / 5 (0x666666)
 785  *      Case 3:         less than or equal to 2^24 / 5 / 16 (0x33333)
 786  *
 787  * In all cases the lowest possible value is better.
 788  *
 789  * The function calculates parameters for all cases and chooses the one closest
 790  * to the asked baud rate.
 791  */
 792 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
 793 {
 794         unsigned long xtal = 200000000;
 795         unsigned long fref = xtal / 2;          /* mandatory division by 2,
 796                                                    see (2) */
 797                                                 /* case 3 */
 798         unsigned long fref1 = fref / 2;         /* case 1 */
 799         unsigned long fref2 = fref * 2 / 5;     /* case 2 */
 800         unsigned long scale;
 801         unsigned long q, q1, q2;
 802         long r, r1, r2;
 803         u32 mul;
 804
 805         /* Case 1 */
 806
 807         /* Set initial value for DDS_CLK_RATE */
 808         mul = (1 << 24) >> 1;
 809
 810         /* Calculate initial quot */
 811         q1 = DIV_ROUND_UP(fref1, rate);
 812
 813         /* Scale q1 if it's too big */
 814         if (q1 > 256) {
 815                 /* Scale q1 to range [1, 512] */
 816                 scale = fls_long(q1 - 1);
 817                 if (scale > 9) {
 818                         q1 >>= scale - 9;
 819                         mul >>= scale - 9;
 820                 }
 821
 822                 /* Round the result if we have a remainder */
 823                 q1 += q1 & 1;
 824         }
 825
 826         /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
 827         scale = __ffs(q1);
 828         q1 >>= scale;
 829         mul >>= scale;
 830
 831         /* Get the remainder */
 832         r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
 833
 834         /* Case 2 */
 835
 836         q2 = DIV_ROUND_UP(fref2, rate);
 837         r2 = abs(fref2 / q2 - rate);
 838
 839         /*
 840          * Choose the best between two: less remainder we have the better. We
 841          * can't go case 2 if q2 is greater than 256 since SCR register can
 842          * hold only values 0 .. 255.
 843          */
 844         if (r2 >= r1 || q2 > 256) {
 845                 /* case 1 is better */
 846                 r = r1;
 847                 q = q1;
 848         } else {
 849                 /* case 2 is better */
 850                 r = r2;
 851                 q = q2;
 852                 mul = (1 << 24) * 2 / 5;
 853         }
 854
 855         /* Check case 3 only if the divisor is big enough */
 856         if (fref / rate >= 80) {
 857                 u64 fssp;
 858                 u32 m;
 859
 860                 /* Calculate initial quot */
 861                 q1 = DIV_ROUND_UP(fref, rate);
 862                 m = (1 << 24) / q1;
 863
 864                 /* Get the remainder */
 865                 fssp = (u64)fref * m;
 866                 do_div(fssp, 1 << 24);
 867                 r1 = abs(fssp - rate);
 868
 869                 /* Choose this one if it suits better */
 870                 if (r1 < r) {
 871                         /* case 3 is better */
 872                         q = 1;
 873                         mul = m;
 874                 }
 875         }
 876
 877         *dds = mul;
 878         return q - 1;
 879 }
 880
 881 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
 882 {
 883         unsigned long ssp_clk = drv_data->controller->max_speed_hz;
 884         const struct ssp_device *ssp = drv_data->ssp;
 885
 886         rate = min_t(int, ssp_clk, rate);
 887
 888         /*
 889          * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
 890          * that the SSP transmission rate can be greater than the device rate
 891          */
 892         if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
 893                 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
 894         else
 895                 return (DIV_ROUND_UP(ssp_clk, rate) - 1)  & 0xfff;
 896 }
 897
 898 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
 899                                            int rate)
 900 {
 901         struct chip_data *chip =
 902                 spi_get_ctldata(drv_data->controller->cur_msg->spi);
 903         unsigned int clk_div;
 904
 905         switch (drv_data->ssp_type) {
 906         case QUARK_X1000_SSP:
 907                 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
 908                 break;
 909         default:
 910                 clk_div = ssp_get_clk_div(drv_data, rate);
 911                 break;
 912         }
 913         return clk_div << 8;
 914 }
 915
 916 static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
 917                                struct spi_device *spi,
 918                                struct spi_transfer *xfer)
 919 {
 920         struct chip_data *chip = spi_get_ctldata(spi);
 921
 922         return chip->enable_dma &&
 923                xfer->len <= MAX_DMA_LEN &&
 924                xfer->len >= chip->dma_burst_size;
 925 }
 926
 927 static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
 928                                    struct spi_device *spi,
 929                                    struct spi_transfer *transfer)
 930 {
 931         struct driver_data *drv_data = spi_controller_get_devdata(controller);
 932         struct spi_message *message = controller->cur_msg;
 933         struct chip_data *chip = spi_get_ctldata(spi);
 934         u32 dma_thresh = chip->dma_threshold;
 935         u32 dma_burst = chip->dma_burst_size;
 936         u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
 937         u32 clk_div;
 938         u8 bits;
 939         u32 speed;
 940         u32 cr0;
 941         u32 cr1;
 942         int err;
 943         int dma_mapped;
 944
 945         /* Check if we can DMA this transfer */
 946         if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
 947
 948                 /* reject already-mapped transfers; PIO won't always work */
 949                 if (message->is_dma_mapped
 950                                 || transfer->rx_dma || transfer->tx_dma) {
 951                         dev_err(&spi->dev,
 952                                 "Mapped transfer length of %u is greater than %d\n",
 953                                 transfer->len, MAX_DMA_LEN);
 954                         return -EINVAL;
 955                 }
 956
 957                 /* warn ... we force this to PIO mode */
 958                 dev_warn_ratelimited(&spi->dev,
 959                                      "DMA disabled for transfer length %ld greater than %d\n",
 960                                      (long)transfer->len, MAX_DMA_LEN);
 961         }
 962
 963         /* Setup the transfer state based on the type of transfer */
 964         if (pxa2xx_spi_flush(drv_data) == 0) {
 965                 dev_err(&spi->dev, "Flush failed\n");
 966                 return -EIO;
 967         }
 968         drv_data->n_bytes = chip->n_bytes;
 969         drv_data->tx = (void *)transfer->tx_buf;
 970         drv_data->tx_end = drv_data->tx + transfer->len;
 971         drv_data->rx = transfer->rx_buf;
 972         drv_data->rx_end = drv_data->rx + transfer->len;
 973         drv_data->write = drv_data->tx ? chip->write : null_writer;
 974         drv_data->read = drv_data->rx ? chip->read : null_reader;
 975
 976         /* Change speed and bit per word on a per transfer */
 977         bits = transfer->bits_per_word;
 978         speed = transfer->speed_hz;
 979
 980         clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
 981
 982         if (bits <= 8) {
 983                 drv_data->n_bytes = 1;
 984                 drv_data->read = drv_data->read != null_reader ?
 985                                         u8_reader : null_reader;
 986                 drv_data->write = drv_data->write != null_writer ?
 987                                         u8_writer : null_writer;
 988         } else if (bits <= 16) {
 989                 drv_data->n_bytes = 2;
 990                 drv_data->read = drv_data->read != null_reader ?
 991                                         u16_reader : null_reader;
 992                 drv_data->write = drv_data->write != null_writer ?
 993                                         u16_writer : null_writer;
 994         } else if (bits <= 32) {
 995                 drv_data->n_bytes = 4;
 996                 drv_data->read = drv_data->read != null_reader ?
 997                                         u32_reader : null_reader;
 998                 drv_data->write = drv_data->write != null_writer ?
 999                                         u32_writer : null_writer;
1000         }
1001         /*
1002          * if bits/word is changed in dma mode, then must check the
1003          * thresholds and burst also
1004          */
1005         if (chip->enable_dma) {
1006                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1007                                                 spi,
1008                                                 bits, &dma_burst,
1009                                                 &dma_thresh))
1010                         dev_warn_ratelimited(&spi->dev,
1011                                              "DMA burst size reduced to match bits_per_word\n");
1012         }
1013
1014         dma_mapped = controller->can_dma &&
1015                      controller->can_dma(controller, spi, transfer) &&
1016                      controller->cur_msg_mapped;
1017         if (dma_mapped) {
1018
1019                 /* Ensure we have the correct interrupt handler */
1020                 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1021
1022                 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1023                 if (err)
1024                         return err;
1025
1026                 /* Clear status and start DMA engine */
1027                 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1028                 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1029
1030                 pxa2xx_spi_dma_start(drv_data);
1031         } else {
1032                 /* Ensure we have the correct interrupt handler */
1033                 drv_data->transfer_handler = interrupt_transfer;
1034
1035                 /* Clear status  */
1036                 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1037                 write_SSSR_CS(drv_data, drv_data->clear_sr);
1038         }
1039
1040         /* NOTE:  PXA25x_SSP _could_ use external clocking ... */
1041         cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1042         if (!pxa25x_ssp_comp(drv_data))
1043                 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1044                         controller->max_speed_hz
1045                                 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1046                         dma_mapped ? "DMA" : "PIO");
1047         else
1048                 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1049                         controller->max_speed_hz / 2
1050                                 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1051                         dma_mapped ? "DMA" : "PIO");
1052
1053         if (is_lpss_ssp(drv_data)) {
1054                 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1055                     != chip->lpss_rx_threshold)
1056                         pxa2xx_spi_write(drv_data, SSIRF,
1057                                          chip->lpss_rx_threshold);
1058                 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1059                     != chip->lpss_tx_threshold)
1060                         pxa2xx_spi_write(drv_data, SSITF,
1061                                          chip->lpss_tx_threshold);
1062         }
1063
1064         if (is_quark_x1000_ssp(drv_data) &&
1065             (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1066                 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1067
1068         /* see if we need to reload the config registers */
1069         if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1070             || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1071             != (cr1 & change_mask)) {
1072                 /* stop the SSP, and update the other bits */
1073                 if (drv_data->ssp_type != MMP2_SSP)
1074                         pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1075                 if (!pxa25x_ssp_comp(drv_data))
1076                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1077                 /* first set CR1 without interrupt and service enables */
1078                 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1079                 /* restart the SSP */
1080                 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1081
1082         } else {
1083                 if (!pxa25x_ssp_comp(drv_data))
1084                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1085         }
1086
1087         if (drv_data->ssp_type == MMP2_SSP) {
1088                 u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR)
1089                                         & SSSR_TFL_MASK) >> 8;
1090
1091                 if (tx_level) {
1092                         /* On MMP2, flipping SSE doesn't to empty TXFIFO. */
1093                         dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n",
1094                                                                 tx_level);
1095                         if (tx_level > transfer->len)
1096                                 tx_level = transfer->len;
1097                         drv_data->tx += tx_level;
1098                 }
1099         }
1100
1101         if (spi_controller_is_slave(controller)) {
1102                 while (drv_data->write(drv_data))
1103                         ;
1104                 if (drv_data->gpiod_ready) {
1105                         gpiod_set_value(drv_data->gpiod_ready, 1);
1106                         udelay(1);
1107                         gpiod_set_value(drv_data->gpiod_ready, 0);
1108                 }
1109         }
1110
1111         /*
1112          * Release the data by enabling service requests and interrupts,
1113          * without changing any mode bits
1114          */
1115         pxa2xx_spi_write(drv_data, SSCR1, cr1);
1116
1117         return 1;
1118 }
1119
1120 static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
1121 {
1122         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1123
1124         /* Stop and reset SSP */
1125         write_SSSR_CS(drv_data, drv_data->clear_sr);
1126         reset_sccr1(drv_data);
1127         if (!pxa25x_ssp_comp(drv_data))
1128                 pxa2xx_spi_write(drv_data, SSTO, 0);
1129         pxa2xx_spi_flush(drv_data);
1130         pxa2xx_spi_off(drv_data);
1131
1132         dev_dbg(&drv_data->pdev->dev, "transfer aborted\n");
1133
1134         drv_data->controller->cur_msg->status = -EINTR;
1135         spi_finalize_current_transfer(drv_data->controller);
1136
1137         return 0;
1138 }
1139
1140 static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1141                                  struct spi_message *msg)
1142 {
1143         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1144
1145         /* Disable the SSP */
1146         pxa2xx_spi_off(drv_data);
1147         /* Clear and disable interrupts and service requests */
1148         write_SSSR_CS(drv_data, drv_data->clear_sr);
1149         pxa2xx_spi_write(drv_data, SSCR1,
1150                          pxa2xx_spi_read(drv_data, SSCR1)
1151                          & ~(drv_data->int_cr1 | drv_data->dma_cr1));
1152         if (!pxa25x_ssp_comp(drv_data))
1153                 pxa2xx_spi_write(drv_data, SSTO, 0);
1154
1155         /*
1156          * Stop the DMA if running. Note DMA callback handler may have unset
1157          * the dma_running already, which is fine as stopping is not needed
1158          * then but we shouldn't rely this flag for anything else than
1159          * stopping. For instance to differentiate between PIO and DMA
1160          * transfers.
1161          */
1162         if (atomic_read(&drv_data->dma_running))
1163                 pxa2xx_spi_dma_stop(drv_data);
1164 }
1165
1166 static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1167 {
1168         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1169
1170         /* Disable the SSP now */
1171         pxa2xx_spi_off(drv_data);
1172
1173         return 0;
1174 }
1175
1176 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1177                     struct pxa2xx_spi_chip *chip_info)
1178 {
1179         struct driver_data *drv_data =
1180                 spi_controller_get_devdata(spi->controller);
1181         struct gpio_desc *gpiod;
1182         int err = 0;
1183
1184         if (chip == NULL)
1185                 return 0;
1186
1187         if (drv_data->cs_gpiods) {
1188                 gpiod = drv_data->cs_gpiods[spi->chip_select];
1189                 if (gpiod) {
1190                         chip->gpiod_cs = gpiod;
1191                         chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1192                         gpiod_set_value(gpiod, chip->gpio_cs_inverted);
1193                 }
1194
1195                 return 0;
1196         }
1197
1198         if (chip_info == NULL)
1199                 return 0;
1200
1201         /* NOTE: setup() can be called multiple times, possibly with
1202          * different chip_info, release previously requested GPIO
1203          */
1204         if (chip->gpiod_cs) {
1205                 gpiod_put(chip->gpiod_cs);
1206                 chip->gpiod_cs = NULL;
1207         }
1208
1209         /* If (*cs_control) is provided, ignore GPIO chip select */
1210         if (chip_info->cs_control) {
1211                 chip->cs_control = chip_info->cs_control;
1212                 return 0;
1213         }
1214
1215         if (gpio_is_valid(chip_info->gpio_cs)) {
1216                 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1217                 if (err) {
1218                         dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1219                                 chip_info->gpio_cs);
1220                         return err;
1221                 }
1222
1223                 gpiod = gpio_to_desc(chip_info->gpio_cs);
1224                 chip->gpiod_cs = gpiod;
1225                 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1226
1227                 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
1228         }
1229
1230         return err;
1231 }
1232
1233 static int setup(struct spi_device *spi)
1234 {
1235         struct pxa2xx_spi_chip *chip_info;
1236         struct chip_data *chip;
1237         const struct lpss_config *config;
1238         struct driver_data *drv_data =
1239                 spi_controller_get_devdata(spi->controller);
1240         uint tx_thres, tx_hi_thres, rx_thres;
1241
1242         switch (drv_data->ssp_type) {
1243         case QUARK_X1000_SSP:
1244                 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1245                 tx_hi_thres = 0;
1246                 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1247                 break;
1248         case CE4100_SSP:
1249                 tx_thres = TX_THRESH_CE4100_DFLT;
1250                 tx_hi_thres = 0;
1251                 rx_thres = RX_THRESH_CE4100_DFLT;
1252                 break;
1253         case LPSS_LPT_SSP:
1254         case LPSS_BYT_SSP:
1255         case LPSS_BSW_SSP:
1256         case LPSS_SPT_SSP:
1257         case LPSS_BXT_SSP:
1258         case LPSS_CNL_SSP:
1259                 config = lpss_get_config(drv_data);
1260                 tx_thres = config->tx_threshold_lo;
1261                 tx_hi_thres = config->tx_threshold_hi;
1262                 rx_thres = config->rx_threshold;
1263                 break;
1264         default:
1265                 tx_hi_thres = 0;
1266                 if (spi_controller_is_slave(drv_data->controller)) {
1267                         tx_thres = 1;
1268                         rx_thres = 2;
1269                 } else {
1270                         tx_thres = TX_THRESH_DFLT;
1271                         rx_thres = RX_THRESH_DFLT;
1272                 }
1273                 break;
1274         }
1275
1276         /* Only alloc on first setup */
1277         chip = spi_get_ctldata(spi);
1278         if (!chip) {
1279                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1280                 if (!chip)
1281                         return -ENOMEM;
1282
1283                 if (drv_data->ssp_type == CE4100_SSP) {
1284                         if (spi->chip_select > 4) {
1285                                 dev_err(&spi->dev,
1286                                         "failed setup: cs number must not be > 4.\n");
1287                                 kfree(chip);
1288                                 return -EINVAL;
1289                         }
1290
1291                         chip->frm = spi->chip_select;
1292                 }
1293                 chip->enable_dma = drv_data->controller_info->enable_dma;
1294                 chip->timeout = TIMOUT_DFLT;
1295         }
1296
1297         /* protocol drivers may change the chip settings, so...
1298          * if chip_info exists, use it */
1299         chip_info = spi->controller_data;
1300
1301         /* chip_info isn't always needed */
1302         chip->cr1 = 0;
1303         if (chip_info) {
1304                 if (chip_info->timeout)
1305                         chip->timeout = chip_info->timeout;
1306                 if (chip_info->tx_threshold)
1307                         tx_thres = chip_info->tx_threshold;
1308                 if (chip_info->tx_hi_threshold)
1309                         tx_hi_thres = chip_info->tx_hi_threshold;
1310                 if (chip_info->rx_threshold)
1311                         rx_thres = chip_info->rx_threshold;
1312                 chip->dma_threshold = 0;
1313                 if (chip_info->enable_loopback)
1314                         chip->cr1 = SSCR1_LBM;
1315         }
1316         if (spi_controller_is_slave(drv_data->controller)) {
1317                 chip->cr1 |= SSCR1_SCFR;
1318                 chip->cr1 |= SSCR1_SCLKDIR;
1319                 chip->cr1 |= SSCR1_SFRMDIR;
1320                 chip->cr1 |= SSCR1_SPH;
1321         }
1322
1323         chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1324         chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1325                                 | SSITF_TxHiThresh(tx_hi_thres);
1326
1327         /* set dma burst and threshold outside of chip_info path so that if
1328          * chip_info goes away after setting chip->enable_dma, the
1329          * burst and threshold can still respond to changes in bits_per_word */
1330         if (chip->enable_dma) {
1331                 /* set up legal burst and threshold for dma */
1332                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1333                                                 spi->bits_per_word,
1334                                                 &chip->dma_burst_size,
1335                                                 &chip->dma_threshold)) {
1336                         dev_warn(&spi->dev,
1337                                  "in setup: DMA burst size reduced to match bits_per_word\n");
1338                 }
1339                 dev_dbg(&spi->dev,
1340                         "in setup: DMA burst size set to %u\n",
1341                         chip->dma_burst_size);
1342         }
1343
1344         switch (drv_data->ssp_type) {
1345         case QUARK_X1000_SSP:
1346                 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1347                                    & QUARK_X1000_SSCR1_RFT)
1348                                    | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1349                                    & QUARK_X1000_SSCR1_TFT);
1350                 break;
1351         case CE4100_SSP:
1352                 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1353                         (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1354                 break;
1355         default:
1356                 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1357                         (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1358                 break;
1359         }
1360
1361         chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1362         chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1363                         | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1364
1365         if (spi->mode & SPI_LOOP)
1366                 chip->cr1 |= SSCR1_LBM;
1367
1368         if (spi->bits_per_word <= 8) {
1369                 chip->n_bytes = 1;
1370                 chip->read = u8_reader;
1371                 chip->write = u8_writer;
1372         } else if (spi->bits_per_word <= 16) {
1373                 chip->n_bytes = 2;
1374                 chip->read = u16_reader;
1375                 chip->write = u16_writer;
1376         } else if (spi->bits_per_word <= 32) {
1377                 chip->n_bytes = 4;
1378                 chip->read = u32_reader;
1379                 chip->write = u32_writer;
1380         }
1381
1382         spi_set_ctldata(spi, chip);
1383
1384         if (drv_data->ssp_type == CE4100_SSP)
1385                 return 0;
1386
1387         return setup_cs(spi, chip, chip_info);
1388 }
1389
1390 static void cleanup(struct spi_device *spi)
1391 {
1392         struct chip_data *chip = spi_get_ctldata(spi);
1393         struct driver_data *drv_data =
1394                 spi_controller_get_devdata(spi->controller);
1395
1396         if (!chip)
1397                 return;
1398
1399         if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
1400             chip->gpiod_cs)
1401                 gpiod_put(chip->gpiod_cs);
1402
1403         kfree(chip);
1404 }
1405
1406 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1407         { "INT33C0", LPSS_LPT_SSP },
1408         { "INT33C1", LPSS_LPT_SSP },
1409         { "INT3430", LPSS_LPT_SSP },
1410         { "INT3431", LPSS_LPT_SSP },
1411         { "80860F0E", LPSS_BYT_SSP },
1412         { "8086228E", LPSS_BSW_SSP },
1413         { },
1414 };
1415 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1416
1417 /*
1418  * PCI IDs of compound devices that integrate both host controller and private
1419  * integrated DMA engine. Please note these are not used in module
1420  * autoloading and probing in this module but matching the LPSS SSP type.
1421  */
1422 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1423         /* SPT-LP */
1424         { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1425         { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1426         /* SPT-H */
1427         { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1428         { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1429         /* KBL-H */
1430         { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1431         { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1432         /* CML-V */
1433         { PCI_VDEVICE(INTEL, 0xa3a9), LPSS_SPT_SSP },
1434         { PCI_VDEVICE(INTEL, 0xa3aa), LPSS_SPT_SSP },
1435         /* BXT A-Step */
1436         { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1437         { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1438         { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1439         /* BXT B-Step */
1440         { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1441         { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1442         { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1443         /* GLK */
1444         { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
1445         { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
1446         { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
1447         /* ICL-LP */
1448         { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
1449         { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
1450         { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
1451         /* EHL */
1452         { PCI_VDEVICE(INTEL, 0x4b2a), LPSS_BXT_SSP },
1453         { PCI_VDEVICE(INTEL, 0x4b2b), LPSS_BXT_SSP },
1454         { PCI_VDEVICE(INTEL, 0x4b37), LPSS_BXT_SSP },
1455         /* JSL */
1456         { PCI_VDEVICE(INTEL, 0x4daa), LPSS_CNL_SSP },
1457         { PCI_VDEVICE(INTEL, 0x4dab), LPSS_CNL_SSP },
1458         { PCI_VDEVICE(INTEL, 0x4dfb), LPSS_CNL_SSP },
1459         /* APL */
1460         { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1461         { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1462         { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1463         /* CNL-LP */
1464         { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
1465         { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
1466         { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
1467         /* CNL-H */
1468         { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
1469         { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
1470         { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
1471         /* CML-LP */
1472         { PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP },
1473         { PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP },
1474         { PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP },
1475         /* CML-H */
1476         { PCI_VDEVICE(INTEL, 0x06aa), LPSS_CNL_SSP },
1477         { PCI_VDEVICE(INTEL, 0x06ab), LPSS_CNL_SSP },
1478         { PCI_VDEVICE(INTEL, 0x06fb), LPSS_CNL_SSP },
1479         /* TGL-LP */
1480         { PCI_VDEVICE(INTEL, 0xa0aa), LPSS_CNL_SSP },
1481         { PCI_VDEVICE(INTEL, 0xa0ab), LPSS_CNL_SSP },
1482         { PCI_VDEVICE(INTEL, 0xa0de), LPSS_CNL_SSP },
1483         { PCI_VDEVICE(INTEL, 0xa0df), LPSS_CNL_SSP },
1484         { PCI_VDEVICE(INTEL, 0xa0fb), LPSS_CNL_SSP },
1485         { PCI_VDEVICE(INTEL, 0xa0fd), LPSS_CNL_SSP },
1486         { PCI_VDEVICE(INTEL, 0xa0fe), LPSS_CNL_SSP },
1487         { },
1488 };
1489
1490 static const struct of_device_id pxa2xx_spi_of_match[] = {
1491         { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1492         {},
1493 };
1494 MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
1495
1496 #ifdef CONFIG_ACPI
1497
1498 static int pxa2xx_spi_get_port_id(struct device *dev)
1499 {
1500         struct acpi_device *adev;
1501         unsigned int devid;
1502         int port_id = -1;
1503
1504         adev = ACPI_COMPANION(dev);
1505         if (adev && adev->pnp.unique_id &&
1506             !kstrtouint(adev->pnp.unique_id, 0, &devid))
1507                 port_id = devid;
1508         return port_id;
1509 }
1510
1511 #else /* !CONFIG_ACPI */
1512
1513 static int pxa2xx_spi_get_port_id(struct device *dev)
1514 {
1515         return -1;
1516 }
1517
1518 #endif /* CONFIG_ACPI */
1519
1520
1521 #ifdef CONFIG_PCI
1522
1523 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1524 {
1525         return param == chan->device->dev;
1526 }
1527
1528 #endif /* CONFIG_PCI */
1529
1530 static struct pxa2xx_spi_controller *
1531 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1532 {
1533         struct pxa2xx_spi_controller *pdata;
1534         struct ssp_device *ssp;
1535         struct resource *res;
1536         struct device *parent = pdev->dev.parent;
1537         struct pci_dev *pcidev = dev_is_pci(parent) ? to_pci_dev(parent) : NULL;
1538         const struct pci_device_id *pcidev_id = NULL;
1539         enum pxa_ssp_type type;
1540         const void *match;
1541
1542         if (pcidev)
1543                 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, pcidev);
1544
1545         match = device_get_match_data(&pdev->dev);
1546         if (match)
1547                 type = (enum pxa_ssp_type)match;
1548         else if (pcidev_id)
1549                 type = (enum pxa_ssp_type)pcidev_id->driver_data;
1550         else
1551                 return NULL;
1552
1553         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1554         if (!pdata)
1555                 return NULL;
1556
1557         ssp = &pdata->ssp;
1558
1559         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1560         ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1561         if (IS_ERR(ssp->mmio_base))
1562                 return NULL;
1563
1564         ssp->phys_base = res->start;
1565
1566 #ifdef CONFIG_PCI
1567         if (pcidev_id) {
1568                 pdata->tx_param = parent;
1569                 pdata->rx_param = parent;
1570                 pdata->dma_filter = pxa2xx_spi_idma_filter;
1571         }
1572 #endif
1573
1574         ssp->clk = devm_clk_get(&pdev->dev, NULL);
1575         if (IS_ERR(ssp->clk))
1576                 return NULL;
1577
1578         ssp->irq = platform_get_irq(pdev, 0);
1579         if (ssp->irq < 0)
1580                 return NULL;
1581
1582         ssp->type = type;
1583         ssp->dev = &pdev->dev;
1584         ssp->port_id = pxa2xx_spi_get_port_id(&pdev->dev);
1585
1586         pdata->is_slave = device_property_read_bool(&pdev->dev, "spi-slave");
1587         pdata->num_chipselect = 1;
1588         pdata->enable_dma = true;
1589         pdata->dma_burst_size = 1;
1590
1591         return pdata;
1592 }
1593
1594 static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1595                                       unsigned int cs)
1596 {
1597         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1598
1599         if (has_acpi_companion(&drv_data->pdev->dev)) {
1600                 switch (drv_data->ssp_type) {
1601                 /*
1602                  * For Atoms the ACPI DeviceSelection used by the Windows
1603                  * driver starts from 1 instead of 0 so translate it here
1604                  * to match what Linux expects.
1605                  */
1606                 case LPSS_BYT_SSP:
1607                 case LPSS_BSW_SSP:
1608                         return cs - 1;
1609
1610                 default:
1611                         break;
1612                 }
1613         }
1614
1615         return cs;
1616 }
1617
1618 static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
1619 {
1620         return MAX_DMA_LEN;
1621 }
1622
1623 static int pxa2xx_spi_probe(struct platform_device *pdev)
1624 {
1625         struct device *dev = &pdev->dev;
1626         struct pxa2xx_spi_controller *platform_info;
1627         struct spi_controller *controller;
1628         struct driver_data *drv_data;
1629         struct ssp_device *ssp;
1630         const struct lpss_config *config;
1631         int status, count;
1632         u32 tmp;
1633
1634         platform_info = dev_get_platdata(dev);
1635         if (!platform_info) {
1636                 platform_info = pxa2xx_spi_init_pdata(pdev);
1637                 if (!platform_info) {
1638                         dev_err(&pdev->dev, "missing platform data\n");
1639                         return -ENODEV;
1640                 }
1641         }
1642
1643         ssp = pxa_ssp_request(pdev->id, pdev->name);
1644         if (!ssp)
1645                 ssp = &platform_info->ssp;
1646
1647         if (!ssp->mmio_base) {
1648                 dev_err(&pdev->dev, "failed to get ssp\n");
1649                 return -ENODEV;
1650         }
1651
1652         if (platform_info->is_slave)
1653                 controller = spi_alloc_slave(dev, sizeof(struct driver_data));
1654         else
1655                 controller = spi_alloc_master(dev, sizeof(struct driver_data));
1656
1657         if (!controller) {
1658                 dev_err(&pdev->dev, "cannot alloc spi_controller\n");
1659                 pxa_ssp_free(ssp);
1660                 return -ENOMEM;
1661         }
1662         drv_data = spi_controller_get_devdata(controller);
1663         drv_data->controller = controller;
1664         drv_data->controller_info = platform_info;
1665         drv_data->pdev = pdev;
1666         drv_data->ssp = ssp;
1667
1668         controller->dev.of_node = pdev->dev.of_node;
1669         /* the spi->mode bits understood by this driver: */
1670         controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1671
1672         controller->bus_num = ssp->port_id;
1673         controller->dma_alignment = DMA_ALIGNMENT;
1674         controller->cleanup = cleanup;
1675         controller->setup = setup;
1676         controller->set_cs = pxa2xx_spi_set_cs;
1677         controller->transfer_one = pxa2xx_spi_transfer_one;
1678         controller->slave_abort = pxa2xx_spi_slave_abort;
1679         controller->handle_err = pxa2xx_spi_handle_err;
1680         controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1681         controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1682         controller->auto_runtime_pm = true;
1683         controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1684
1685         drv_data->ssp_type = ssp->type;
1686
1687         drv_data->ioaddr = ssp->mmio_base;
1688         drv_data->ssdr_physical = ssp->phys_base + SSDR;
1689         if (pxa25x_ssp_comp(drv_data)) {
1690                 switch (drv_data->ssp_type) {
1691                 case QUARK_X1000_SSP:
1692                         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1693                         break;
1694                 default:
1695                         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1696                         break;
1697                 }
1698
1699                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1700                 drv_data->dma_cr1 = 0;
1701                 drv_data->clear_sr = SSSR_ROR;
1702                 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1703         } else {
1704                 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1705                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1706                 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1707                 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1708                 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1709                                                 | SSSR_ROR | SSSR_TUR;
1710         }
1711
1712         status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1713                         drv_data);
1714         if (status < 0) {
1715                 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1716                 goto out_error_controller_alloc;
1717         }
1718
1719         /* Setup DMA if requested */
1720         if (platform_info->enable_dma) {
1721                 status = pxa2xx_spi_dma_setup(drv_data);
1722                 if (status) {
1723                         dev_warn(dev, "no DMA channels available, using PIO\n");
1724                         platform_info->enable_dma = false;
1725                 } else {
1726                         controller->can_dma = pxa2xx_spi_can_dma;
1727                         controller->max_dma_len = MAX_DMA_LEN;
1728                         controller->max_transfer_size =
1729                                 pxa2xx_spi_max_dma_transfer_size;
1730                 }
1731         }
1732
1733         /* Enable SOC clock */
1734         status = clk_prepare_enable(ssp->clk);
1735         if (status)
1736                 goto out_error_dma_irq_alloc;
1737
1738         controller->max_speed_hz = clk_get_rate(ssp->clk);
1739         /*
1740          * Set minimum speed for all other platforms than Intel Quark which is
1741          * able do under 1 Hz transfers.
1742          */
1743         if (!pxa25x_ssp_comp(drv_data))
1744                 controller->min_speed_hz =
1745                         DIV_ROUND_UP(controller->max_speed_hz, 4096);
1746         else if (!is_quark_x1000_ssp(drv_data))
1747                 controller->min_speed_hz =
1748                         DIV_ROUND_UP(controller->max_speed_hz, 512);
1749
1750         /* Load default SSP configuration */
1751         pxa2xx_spi_write(drv_data, SSCR0, 0);
1752         switch (drv_data->ssp_type) {
1753         case QUARK_X1000_SSP:
1754                 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1755                       QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1756                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1757
1758                 /* using the Motorola SPI protocol and use 8 bit frame */
1759                 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1760                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1761                 break;
1762         case CE4100_SSP:
1763                 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1764                       CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1765                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1766                 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1767                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1768                 break;
1769         default:
1770
1771                 if (spi_controller_is_slave(controller)) {
1772                         tmp = SSCR1_SCFR |
1773                               SSCR1_SCLKDIR |
1774                               SSCR1_SFRMDIR |
1775                               SSCR1_RxTresh(2) |
1776                               SSCR1_TxTresh(1) |
1777                               SSCR1_SPH;
1778                 } else {
1779                         tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1780                               SSCR1_TxTresh(TX_THRESH_DFLT);
1781                 }
1782                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1783                 tmp = SSCR0_Motorola | SSCR0_DataSize(8);
1784                 if (!spi_controller_is_slave(controller))
1785                         tmp |= SSCR0_SCR(2);
1786                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1787                 break;
1788         }
1789
1790         if (!pxa25x_ssp_comp(drv_data))
1791                 pxa2xx_spi_write(drv_data, SSTO, 0);
1792
1793         if (!is_quark_x1000_ssp(drv_data))
1794                 pxa2xx_spi_write(drv_data, SSPSP, 0);
1795
1796         if (is_lpss_ssp(drv_data)) {
1797                 lpss_ssp_setup(drv_data);
1798                 config = lpss_get_config(drv_data);
1799                 if (config->reg_capabilities >= 0) {
1800                         tmp = __lpss_ssp_read_priv(drv_data,
1801                                                    config->reg_capabilities);
1802                         tmp &= LPSS_CAPS_CS_EN_MASK;
1803                         tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1804                         platform_info->num_chipselect = ffz(tmp);
1805                 } else if (config->cs_num) {
1806                         platform_info->num_chipselect = config->cs_num;
1807                 }
1808         }
1809         controller->num_chipselect = platform_info->num_chipselect;
1810
1811         count = gpiod_count(&pdev->dev, "cs");
1812         if (count > 0) {
1813                 int i;
1814
1815                 controller->num_chipselect = max_t(int, count,
1816                         controller->num_chipselect);
1817
1818                 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
1819                         controller->num_chipselect, sizeof(struct gpio_desc *),
1820                         GFP_KERNEL);
1821                 if (!drv_data->cs_gpiods) {
1822                         status = -ENOMEM;
1823                         goto out_error_clock_enabled;
1824                 }
1825
1826                 for (i = 0; i < controller->num_chipselect; i++) {
1827                         struct gpio_desc *gpiod;
1828
1829                         gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1830                         if (IS_ERR(gpiod)) {
1831                                 /* Means use native chip select */
1832                                 if (PTR_ERR(gpiod) == -ENOENT)
1833                                         continue;
1834
1835                                 status = PTR_ERR(gpiod);
1836                                 goto out_error_clock_enabled;
1837                         } else {
1838                                 drv_data->cs_gpiods[i] = gpiod;
1839                         }
1840                 }
1841         }
1842
1843         if (platform_info->is_slave) {
1844                 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1845                                                 "ready", GPIOD_OUT_LOW);
1846                 if (IS_ERR(drv_data->gpiod_ready)) {
1847                         status = PTR_ERR(drv_data->gpiod_ready);
1848                         goto out_error_clock_enabled;
1849                 }
1850         }
1851
1852         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1853         pm_runtime_use_autosuspend(&pdev->dev);
1854         pm_runtime_set_active(&pdev->dev);
1855         pm_runtime_enable(&pdev->dev);
1856
1857         /* Register with the SPI framework */
1858         platform_set_drvdata(pdev, drv_data);
1859         status = devm_spi_register_controller(&pdev->dev, controller);
1860         if (status != 0) {
1861                 dev_err(&pdev->dev, "problem registering spi controller\n");
1862                 goto out_error_pm_runtime_enabled;
1863         }
1864
1865         return status;
1866
1867 out_error_pm_runtime_enabled:
1868         pm_runtime_put_noidle(&pdev->dev);
1869         pm_runtime_disable(&pdev->dev);
1870
1871 out_error_clock_enabled:
1872         clk_disable_unprepare(ssp->clk);
1873
1874 out_error_dma_irq_alloc:
1875         pxa2xx_spi_dma_release(drv_data);
1876         free_irq(ssp->irq, drv_data);
1877
1878 out_error_controller_alloc:
1879         spi_controller_put(controller);
1880         pxa_ssp_free(ssp);
1881         return status;
1882 }
1883
1884 static int pxa2xx_spi_remove(struct platform_device *pdev)
1885 {
1886         struct driver_data *drv_data = platform_get_drvdata(pdev);
1887         struct ssp_device *ssp;
1888
1889         if (!drv_data)
1890                 return 0;
1891         ssp = drv_data->ssp;
1892
1893         pm_runtime_get_sync(&pdev->dev);
1894
1895         /* Disable the SSP at the peripheral and SOC level */
1896         pxa2xx_spi_write(drv_data, SSCR0, 0);
1897         clk_disable_unprepare(ssp->clk);
1898
1899         /* Release DMA */
1900         if (drv_data->controller_info->enable_dma)
1901                 pxa2xx_spi_dma_release(drv_data);
1902
1903         pm_runtime_put_noidle(&pdev->dev);
1904         pm_runtime_disable(&pdev->dev);
1905
1906         /* Release IRQ */
1907         free_irq(ssp->irq, drv_data);
1908
1909         /* Release SSP */
1910         pxa_ssp_free(ssp);
1911
1912         return 0;
1913 }
1914
1915 #ifdef CONFIG_PM_SLEEP
1916 static int pxa2xx_spi_suspend(struct device *dev)
1917 {
1918         struct driver_data *drv_data = dev_get_drvdata(dev);
1919         struct ssp_device *ssp = drv_data->ssp;
1920         int status;
1921
1922         status = spi_controller_suspend(drv_data->controller);
1923         if (status != 0)
1924                 return status;
1925         pxa2xx_spi_write(drv_data, SSCR0, 0);
1926
1927         if (!pm_runtime_suspended(dev))
1928                 clk_disable_unprepare(ssp->clk);
1929
1930         return 0;
1931 }
1932
1933 static int pxa2xx_spi_resume(struct device *dev)
1934 {
1935         struct driver_data *drv_data = dev_get_drvdata(dev);
1936         struct ssp_device *ssp = drv_data->ssp;
1937         int status;
1938
1939         /* Enable the SSP clock */
1940         if (!pm_runtime_suspended(dev)) {
1941                 status = clk_prepare_enable(ssp->clk);
1942                 if (status)
1943                         return status;
1944         }
1945
1946         /* Start the queue running */
1947         return spi_controller_resume(drv_data->controller);
1948 }
1949 #endif
1950
1951 #ifdef CONFIG_PM
1952 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1953 {
1954         struct driver_data *drv_data = dev_get_drvdata(dev);
1955
1956         clk_disable_unprepare(drv_data->ssp->clk);
1957         return 0;
1958 }
1959
1960 static int pxa2xx_spi_runtime_resume(struct device *dev)
1961 {
1962         struct driver_data *drv_data = dev_get_drvdata(dev);
1963         int status;
1964
1965         status = clk_prepare_enable(drv_data->ssp->clk);
1966         return status;
1967 }
1968 #endif
1969
1970 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1971         SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1972         SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1973                            pxa2xx_spi_runtime_resume, NULL)
1974 };
1975
1976 static struct platform_driver driver = {
1977         .driver = {
1978                 .name   = "pxa2xx-spi",
1979                 .pm     = &pxa2xx_spi_pm_ops,
1980                 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1981                 .of_match_table = of_match_ptr(pxa2xx_spi_of_match),
1982         },
1983         .probe = pxa2xx_spi_probe,
1984         .remove = pxa2xx_spi_remove,
1985 };
1986
1987 static int __init pxa2xx_spi_init(void)
1988 {
1989         return platform_driver_register(&driver);
1990 }
1991 subsys_initcall(pxa2xx_spi_init);
1992
1993 static void __exit pxa2xx_spi_exit(void)
1994 {
1995         platform_driver_unregister(&driver);
1996 }
1997 module_exit(pxa2xx_spi_exit);
1998
1999 MODULE_SOFTDEP("pre: dw_dmac");