2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/bitops.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/ioport.h>
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/pci.h>
26 #include <linux/platform_device.h>
27 #include <linux/spi/pxa2xx_spi.h>
28 #include <linux/spi/spi.h>
29 #include <linux/delay.h>
30 #include <linux/gpio.h>
31 #include <linux/slab.h>
32 #include <linux/clk.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/acpi.h>
36 #include "spi-pxa2xx.h"
38 MODULE_AUTHOR("Stephen Street");
39 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
40 MODULE_LICENSE("GPL");
41 MODULE_ALIAS("platform:pxa2xx-spi");
43 #define TIMOUT_DFLT 1000
46 * for testing SSCR1 changes that require SSP restart, basically
47 * everything except the service and interrupt enables, the pxa270 developer
48 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
49 * list, but the PXA255 dev man says all bits without really meaning the
50 * service and interrupt enables
52 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
53 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
54 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
55 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
56 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
57 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
59 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
60 | QUARK_X1000_SSCR1_EFWR \
61 | QUARK_X1000_SSCR1_RFT \
62 | QUARK_X1000_SSCR1_TFT \
63 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
65 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
66 #define LPSS_CS_CONTROL_SW_MODE BIT(0)
67 #define LPSS_CS_CONTROL_CS_HIGH BIT(1)
68 #define LPSS_CS_CONTROL_CS_SEL_SHIFT 8
69 #define LPSS_CS_CONTROL_CS_SEL_MASK (3 << LPSS_CS_CONTROL_CS_SEL_SHIFT)
70 #define LPSS_CAPS_CS_EN_SHIFT 9
71 #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
74 /* LPSS offset from drv_data->ioaddr */
76 /* Register offsets from drv_data->lpss_base or -1 */
87 /* Keep these sorted with enum pxa_ssp_type */
88 static const struct lpss_config lpss_platforms[] = {
94 .reg_capabilities = -1,
96 .tx_threshold_lo = 160,
97 .tx_threshold_hi = 224,
104 .reg_capabilities = -1,
106 .tx_threshold_lo = 160,
107 .tx_threshold_hi = 224,
114 .reg_capabilities = 0xfc,
116 .tx_threshold_lo = 32,
117 .tx_threshold_hi = 56,
124 .reg_capabilities = 0xfc,
126 .tx_threshold_lo = 16,
127 .tx_threshold_hi = 48,
131 static inline const struct lpss_config
132 *lpss_get_config(const struct driver_data *drv_data)
134 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
137 static bool is_lpss_ssp(const struct driver_data *drv_data)
139 switch (drv_data->ssp_type) {
150 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
152 return drv_data->ssp_type == QUARK_X1000_SSP;
155 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
157 switch (drv_data->ssp_type) {
158 case QUARK_X1000_SSP:
159 return QUARK_X1000_SSCR1_CHANGE_MASK;
161 return SSCR1_CHANGE_MASK;
166 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
168 switch (drv_data->ssp_type) {
169 case QUARK_X1000_SSP:
170 return RX_THRESH_QUARK_X1000_DFLT;
172 return RX_THRESH_DFLT;
176 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
180 switch (drv_data->ssp_type) {
181 case QUARK_X1000_SSP:
182 mask = QUARK_X1000_SSSR_TFL_MASK;
185 mask = SSSR_TFL_MASK;
189 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
192 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
197 switch (drv_data->ssp_type) {
198 case QUARK_X1000_SSP:
199 mask = QUARK_X1000_SSCR1_RFT;
208 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
209 u32 *sccr1_reg, u32 threshold)
211 switch (drv_data->ssp_type) {
212 case QUARK_X1000_SSP:
213 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
216 *sccr1_reg |= SSCR1_RxTresh(threshold);
221 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
222 u32 clk_div, u8 bits)
224 switch (drv_data->ssp_type) {
225 case QUARK_X1000_SSP:
227 | QUARK_X1000_SSCR0_Motorola
228 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
233 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
235 | (bits > 16 ? SSCR0_EDSS : 0);
240 * Read and write LPSS SSP private registers. Caller must first check that
241 * is_lpss_ssp() returns true before these can be called.
243 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
245 WARN_ON(!drv_data->lpss_base);
246 return readl(drv_data->lpss_base + offset);
249 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
250 unsigned offset, u32 value)
252 WARN_ON(!drv_data->lpss_base);
253 writel(value, drv_data->lpss_base + offset);
257 * lpss_ssp_setup - perform LPSS SSP specific setup
258 * @drv_data: pointer to the driver private data
260 * Perform LPSS SSP specific setup. This function must be called first if
261 * one is going to use LPSS SSP private registers.
263 static void lpss_ssp_setup(struct driver_data *drv_data)
265 const struct lpss_config *config;
268 config = lpss_get_config(drv_data);
269 drv_data->lpss_base = drv_data->ioaddr + config->offset;
271 /* Enable software chip select control */
272 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
273 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
274 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
275 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
277 /* Enable multiblock DMA transfers */
278 if (drv_data->master_info->enable_dma) {
279 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
281 if (config->reg_general >= 0) {
282 value = __lpss_ssp_read_priv(drv_data,
283 config->reg_general);
284 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
285 __lpss_ssp_write_priv(drv_data,
286 config->reg_general, value);
291 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
293 const struct lpss_config *config;
296 config = lpss_get_config(drv_data);
298 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
300 cs = drv_data->cur_msg->spi->chip_select;
301 cs <<= LPSS_CS_CONTROL_CS_SEL_SHIFT;
302 if (cs != (value & LPSS_CS_CONTROL_CS_SEL_MASK)) {
304 * When switching another chip select output active
305 * the output must be selected first and wait 2 ssp_clk
306 * cycles before changing state to active. Otherwise
307 * a short glitch will occur on the previous chip
308 * select since output select is latched but state
311 value &= ~LPSS_CS_CONTROL_CS_SEL_MASK;
313 __lpss_ssp_write_priv(drv_data,
314 config->reg_cs_ctrl, value);
316 (drv_data->master->max_speed_hz / 2));
318 value &= ~LPSS_CS_CONTROL_CS_HIGH;
320 value |= LPSS_CS_CONTROL_CS_HIGH;
322 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
325 static void cs_assert(struct driver_data *drv_data)
327 struct chip_data *chip = drv_data->cur_chip;
329 if (drv_data->ssp_type == CE4100_SSP) {
330 pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm);
334 if (chip->cs_control) {
335 chip->cs_control(PXA2XX_CS_ASSERT);
339 if (gpio_is_valid(chip->gpio_cs)) {
340 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
344 if (is_lpss_ssp(drv_data))
345 lpss_ssp_cs_control(drv_data, true);
348 static void cs_deassert(struct driver_data *drv_data)
350 struct chip_data *chip = drv_data->cur_chip;
352 if (drv_data->ssp_type == CE4100_SSP)
355 if (chip->cs_control) {
356 chip->cs_control(PXA2XX_CS_DEASSERT);
360 if (gpio_is_valid(chip->gpio_cs)) {
361 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
365 if (is_lpss_ssp(drv_data))
366 lpss_ssp_cs_control(drv_data, false);
369 int pxa2xx_spi_flush(struct driver_data *drv_data)
371 unsigned long limit = loops_per_jiffy << 1;
374 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
375 pxa2xx_spi_read(drv_data, SSDR);
376 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
377 write_SSSR_CS(drv_data, SSSR_ROR);
382 static int null_writer(struct driver_data *drv_data)
384 u8 n_bytes = drv_data->n_bytes;
386 if (pxa2xx_spi_txfifo_full(drv_data)
387 || (drv_data->tx == drv_data->tx_end))
390 pxa2xx_spi_write(drv_data, SSDR, 0);
391 drv_data->tx += n_bytes;
396 static int null_reader(struct driver_data *drv_data)
398 u8 n_bytes = drv_data->n_bytes;
400 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
401 && (drv_data->rx < drv_data->rx_end)) {
402 pxa2xx_spi_read(drv_data, SSDR);
403 drv_data->rx += n_bytes;
406 return drv_data->rx == drv_data->rx_end;
409 static int u8_writer(struct driver_data *drv_data)
411 if (pxa2xx_spi_txfifo_full(drv_data)
412 || (drv_data->tx == drv_data->tx_end))
415 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
421 static int u8_reader(struct driver_data *drv_data)
423 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
424 && (drv_data->rx < drv_data->rx_end)) {
425 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
429 return drv_data->rx == drv_data->rx_end;
432 static int u16_writer(struct driver_data *drv_data)
434 if (pxa2xx_spi_txfifo_full(drv_data)
435 || (drv_data->tx == drv_data->tx_end))
438 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
444 static int u16_reader(struct driver_data *drv_data)
446 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
447 && (drv_data->rx < drv_data->rx_end)) {
448 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
452 return drv_data->rx == drv_data->rx_end;
455 static int u32_writer(struct driver_data *drv_data)
457 if (pxa2xx_spi_txfifo_full(drv_data)
458 || (drv_data->tx == drv_data->tx_end))
461 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
467 static int u32_reader(struct driver_data *drv_data)
469 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
470 && (drv_data->rx < drv_data->rx_end)) {
471 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
475 return drv_data->rx == drv_data->rx_end;
478 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
480 struct spi_message *msg = drv_data->cur_msg;
481 struct spi_transfer *trans = drv_data->cur_transfer;
483 /* Move to next transfer */
484 if (trans->transfer_list.next != &msg->transfers) {
485 drv_data->cur_transfer =
486 list_entry(trans->transfer_list.next,
489 return RUNNING_STATE;
494 /* caller already set message->status; dma and pio irqs are blocked */
495 static void giveback(struct driver_data *drv_data)
497 struct spi_transfer* last_transfer;
498 struct spi_message *msg;
500 msg = drv_data->cur_msg;
501 drv_data->cur_msg = NULL;
502 drv_data->cur_transfer = NULL;
504 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
507 /* Delay if requested before any change in chip select */
508 if (last_transfer->delay_usecs)
509 udelay(last_transfer->delay_usecs);
511 /* Drop chip select UNLESS cs_change is true or we are returning
512 * a message with an error, or next message is for another chip
514 if (!last_transfer->cs_change)
515 cs_deassert(drv_data);
517 struct spi_message *next_msg;
519 /* Holding of cs was hinted, but we need to make sure
520 * the next message is for the same chip. Don't waste
521 * time with the following tests unless this was hinted.
523 * We cannot postpone this until pump_messages, because
524 * after calling msg->complete (below) the driver that
525 * sent the current message could be unloaded, which
526 * could invalidate the cs_control() callback...
529 /* get a pointer to the next message, if any */
530 next_msg = spi_get_next_queued_message(drv_data->master);
532 /* see if the next and current messages point
535 if (next_msg && next_msg->spi != msg->spi)
537 if (!next_msg || msg->state == ERROR_STATE)
538 cs_deassert(drv_data);
541 drv_data->cur_chip = NULL;
542 spi_finalize_current_message(drv_data->master);
545 static void reset_sccr1(struct driver_data *drv_data)
547 struct chip_data *chip = drv_data->cur_chip;
550 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
551 sccr1_reg &= ~SSCR1_RFT;
552 sccr1_reg |= chip->threshold;
553 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
556 static void int_error_stop(struct driver_data *drv_data, const char* msg)
558 /* Stop and reset SSP */
559 write_SSSR_CS(drv_data, drv_data->clear_sr);
560 reset_sccr1(drv_data);
561 if (!pxa25x_ssp_comp(drv_data))
562 pxa2xx_spi_write(drv_data, SSTO, 0);
563 pxa2xx_spi_flush(drv_data);
564 pxa2xx_spi_write(drv_data, SSCR0,
565 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
567 dev_err(&drv_data->pdev->dev, "%s\n", msg);
569 drv_data->cur_msg->state = ERROR_STATE;
570 tasklet_schedule(&drv_data->pump_transfers);
573 static void int_transfer_complete(struct driver_data *drv_data)
576 write_SSSR_CS(drv_data, drv_data->clear_sr);
577 reset_sccr1(drv_data);
578 if (!pxa25x_ssp_comp(drv_data))
579 pxa2xx_spi_write(drv_data, SSTO, 0);
581 /* Update total byte transferred return count actual bytes read */
582 drv_data->cur_msg->actual_length += drv_data->len -
583 (drv_data->rx_end - drv_data->rx);
585 /* Transfer delays and chip select release are
586 * handled in pump_transfers or giveback
589 /* Move to next transfer */
590 drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
592 /* Schedule transfer tasklet */
593 tasklet_schedule(&drv_data->pump_transfers);
596 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
598 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
599 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
601 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
603 if (irq_status & SSSR_ROR) {
604 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
608 if (irq_status & SSSR_TINT) {
609 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
610 if (drv_data->read(drv_data)) {
611 int_transfer_complete(drv_data);
616 /* Drain rx fifo, Fill tx fifo and prevent overruns */
618 if (drv_data->read(drv_data)) {
619 int_transfer_complete(drv_data);
622 } while (drv_data->write(drv_data));
624 if (drv_data->read(drv_data)) {
625 int_transfer_complete(drv_data);
629 if (drv_data->tx == drv_data->tx_end) {
633 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
634 sccr1_reg &= ~SSCR1_TIE;
637 * PXA25x_SSP has no timeout, set up rx threshould for the
638 * remaining RX bytes.
640 if (pxa25x_ssp_comp(drv_data)) {
643 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
645 bytes_left = drv_data->rx_end - drv_data->rx;
646 switch (drv_data->n_bytes) {
653 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
654 if (rx_thre > bytes_left)
655 rx_thre = bytes_left;
657 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
659 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
662 /* We did something */
666 static irqreturn_t ssp_int(int irq, void *dev_id)
668 struct driver_data *drv_data = dev_id;
670 u32 mask = drv_data->mask_sr;
674 * The IRQ might be shared with other peripherals so we must first
675 * check that are we RPM suspended or not. If we are we assume that
676 * the IRQ was not for us (we shouldn't be RPM suspended when the
677 * interrupt is enabled).
679 if (pm_runtime_suspended(&drv_data->pdev->dev))
683 * If the device is not yet in RPM suspended state and we get an
684 * interrupt that is meant for another device, check if status bits
685 * are all set to one. That means that the device is already
688 status = pxa2xx_spi_read(drv_data, SSSR);
692 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
694 /* Ignore possible writes if we don't need to write */
695 if (!(sccr1_reg & SSCR1_TIE))
698 if (!(status & mask))
701 if (!drv_data->cur_msg) {
703 pxa2xx_spi_write(drv_data, SSCR0,
704 pxa2xx_spi_read(drv_data, SSCR0)
706 pxa2xx_spi_write(drv_data, SSCR1,
707 pxa2xx_spi_read(drv_data, SSCR1)
708 & ~drv_data->int_cr1);
709 if (!pxa25x_ssp_comp(drv_data))
710 pxa2xx_spi_write(drv_data, SSTO, 0);
711 write_SSSR_CS(drv_data, drv_data->clear_sr);
713 dev_err(&drv_data->pdev->dev,
714 "bad message state in interrupt handler\n");
720 return drv_data->transfer_handler(drv_data);
724 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
725 * input frequency by fractions of 2^24. It also has a divider by 5.
727 * There are formulas to get baud rate value for given input frequency and
728 * divider parameters, such as DDS_CLK_RATE and SCR:
732 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
733 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
735 * DDS_CLK_RATE either 2^n or 2^n / 5.
736 * SCR is in range 0 .. 255
738 * Divisor = 5^i * 2^j * 2 * k
739 * i = [0, 1] i = 1 iff j = 0 or j > 3
740 * j = [0, 23] j = 0 iff i = 1
742 * Special case: j = 0, i = 1: Divisor = 2 / 5
744 * Accordingly to the specification the recommended values for DDS_CLK_RATE
746 * Case 1: 2^n, n = [0, 23]
747 * Case 2: 2^24 * 2 / 5 (0x666666)
748 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
750 * In all cases the lowest possible value is better.
752 * The function calculates parameters for all cases and chooses the one closest
753 * to the asked baud rate.
755 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
757 unsigned long xtal = 200000000;
758 unsigned long fref = xtal / 2; /* mandatory division by 2,
761 unsigned long fref1 = fref / 2; /* case 1 */
762 unsigned long fref2 = fref * 2 / 5; /* case 2 */
764 unsigned long q, q1, q2;
770 /* Set initial value for DDS_CLK_RATE */
771 mul = (1 << 24) >> 1;
773 /* Calculate initial quot */
774 q1 = DIV_ROUND_UP(fref1, rate);
776 /* Scale q1 if it's too big */
778 /* Scale q1 to range [1, 512] */
779 scale = fls_long(q1 - 1);
785 /* Round the result if we have a remainder */
789 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
794 /* Get the remainder */
795 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
799 q2 = DIV_ROUND_UP(fref2, rate);
800 r2 = abs(fref2 / q2 - rate);
803 * Choose the best between two: less remainder we have the better. We
804 * can't go case 2 if q2 is greater than 256 since SCR register can
805 * hold only values 0 .. 255.
807 if (r2 >= r1 || q2 > 256) {
808 /* case 1 is better */
812 /* case 2 is better */
815 mul = (1 << 24) * 2 / 5;
818 /* Check case 3 only if the divisor is big enough */
819 if (fref / rate >= 80) {
823 /* Calculate initial quot */
824 q1 = DIV_ROUND_UP(fref, rate);
827 /* Get the remainder */
828 fssp = (u64)fref * m;
829 do_div(fssp, 1 << 24);
830 r1 = abs(fssp - rate);
832 /* Choose this one if it suits better */
834 /* case 3 is better */
844 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
846 unsigned long ssp_clk = drv_data->master->max_speed_hz;
847 const struct ssp_device *ssp = drv_data->ssp;
849 rate = min_t(int, ssp_clk, rate);
851 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
852 return (ssp_clk / (2 * rate) - 1) & 0xff;
854 return (ssp_clk / rate - 1) & 0xfff;
857 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
860 struct chip_data *chip = drv_data->cur_chip;
861 unsigned int clk_div;
863 switch (drv_data->ssp_type) {
864 case QUARK_X1000_SSP:
865 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
868 clk_div = ssp_get_clk_div(drv_data, rate);
874 static void pump_transfers(unsigned long data)
876 struct driver_data *drv_data = (struct driver_data *)data;
877 struct spi_message *message = NULL;
878 struct spi_transfer *transfer = NULL;
879 struct spi_transfer *previous = NULL;
880 struct chip_data *chip = NULL;
886 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
887 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
888 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
890 /* Get current state information */
891 message = drv_data->cur_msg;
892 transfer = drv_data->cur_transfer;
893 chip = drv_data->cur_chip;
895 /* Handle for abort */
896 if (message->state == ERROR_STATE) {
897 message->status = -EIO;
902 /* Handle end of message */
903 if (message->state == DONE_STATE) {
909 /* Delay if requested at end of transfer before CS change */
910 if (message->state == RUNNING_STATE) {
911 previous = list_entry(transfer->transfer_list.prev,
914 if (previous->delay_usecs)
915 udelay(previous->delay_usecs);
917 /* Drop chip select only if cs_change is requested */
918 if (previous->cs_change)
919 cs_deassert(drv_data);
922 /* Check if we can DMA this transfer */
923 if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
925 /* reject already-mapped transfers; PIO won't always work */
926 if (message->is_dma_mapped
927 || transfer->rx_dma || transfer->tx_dma) {
928 dev_err(&drv_data->pdev->dev,
929 "pump_transfers: mapped transfer length of "
930 "%u is greater than %d\n",
931 transfer->len, MAX_DMA_LEN);
932 message->status = -EINVAL;
937 /* warn ... we force this to PIO mode */
938 dev_warn_ratelimited(&message->spi->dev,
939 "pump_transfers: DMA disabled for transfer length %ld "
941 (long)drv_data->len, MAX_DMA_LEN);
944 /* Setup the transfer state based on the type of transfer */
945 if (pxa2xx_spi_flush(drv_data) == 0) {
946 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
947 message->status = -EIO;
951 drv_data->n_bytes = chip->n_bytes;
952 drv_data->tx = (void *)transfer->tx_buf;
953 drv_data->tx_end = drv_data->tx + transfer->len;
954 drv_data->rx = transfer->rx_buf;
955 drv_data->rx_end = drv_data->rx + transfer->len;
956 drv_data->rx_dma = transfer->rx_dma;
957 drv_data->tx_dma = transfer->tx_dma;
958 drv_data->len = transfer->len;
959 drv_data->write = drv_data->tx ? chip->write : null_writer;
960 drv_data->read = drv_data->rx ? chip->read : null_reader;
962 /* Change speed and bit per word on a per transfer */
963 bits = transfer->bits_per_word;
964 speed = transfer->speed_hz;
966 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
969 drv_data->n_bytes = 1;
970 drv_data->read = drv_data->read != null_reader ?
971 u8_reader : null_reader;
972 drv_data->write = drv_data->write != null_writer ?
973 u8_writer : null_writer;
974 } else if (bits <= 16) {
975 drv_data->n_bytes = 2;
976 drv_data->read = drv_data->read != null_reader ?
977 u16_reader : null_reader;
978 drv_data->write = drv_data->write != null_writer ?
979 u16_writer : null_writer;
980 } else if (bits <= 32) {
981 drv_data->n_bytes = 4;
982 drv_data->read = drv_data->read != null_reader ?
983 u32_reader : null_reader;
984 drv_data->write = drv_data->write != null_writer ?
985 u32_writer : null_writer;
988 * if bits/word is changed in dma mode, then must check the
989 * thresholds and burst also
991 if (chip->enable_dma) {
992 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
996 dev_warn_ratelimited(&message->spi->dev,
997 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
1000 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1001 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1002 if (!pxa25x_ssp_comp(drv_data))
1003 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1004 drv_data->master->max_speed_hz
1005 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1006 chip->enable_dma ? "DMA" : "PIO");
1008 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1009 drv_data->master->max_speed_hz / 2
1010 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1011 chip->enable_dma ? "DMA" : "PIO");
1013 message->state = RUNNING_STATE;
1015 drv_data->dma_mapped = 0;
1016 if (pxa2xx_spi_dma_is_possible(drv_data->len))
1017 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
1018 if (drv_data->dma_mapped) {
1020 /* Ensure we have the correct interrupt handler */
1021 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1023 pxa2xx_spi_dma_prepare(drv_data, dma_burst);
1025 /* Clear status and start DMA engine */
1026 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1027 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1029 pxa2xx_spi_dma_start(drv_data);
1031 /* Ensure we have the correct interrupt handler */
1032 drv_data->transfer_handler = interrupt_transfer;
1035 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1036 write_SSSR_CS(drv_data, drv_data->clear_sr);
1039 if (is_lpss_ssp(drv_data)) {
1040 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1041 != chip->lpss_rx_threshold)
1042 pxa2xx_spi_write(drv_data, SSIRF,
1043 chip->lpss_rx_threshold);
1044 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1045 != chip->lpss_tx_threshold)
1046 pxa2xx_spi_write(drv_data, SSITF,
1047 chip->lpss_tx_threshold);
1050 if (is_quark_x1000_ssp(drv_data) &&
1051 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1052 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1054 /* see if we need to reload the config registers */
1055 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1056 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1057 != (cr1 & change_mask)) {
1058 /* stop the SSP, and update the other bits */
1059 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1060 if (!pxa25x_ssp_comp(drv_data))
1061 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1062 /* first set CR1 without interrupt and service enables */
1063 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1064 /* restart the SSP */
1065 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1068 if (!pxa25x_ssp_comp(drv_data))
1069 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1072 cs_assert(drv_data);
1074 /* after chip select, release the data by enabling service
1075 * requests and interrupts, without changing any mode bits */
1076 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1079 static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
1080 struct spi_message *msg)
1082 struct driver_data *drv_data = spi_master_get_devdata(master);
1084 drv_data->cur_msg = msg;
1085 /* Initial message state*/
1086 drv_data->cur_msg->state = START_STATE;
1087 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1088 struct spi_transfer,
1091 /* prepare to setup the SSP, in pump_transfers, using the per
1092 * chip configuration */
1093 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1095 /* Mark as busy and launch transfers */
1096 tasklet_schedule(&drv_data->pump_transfers);
1100 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
1102 struct driver_data *drv_data = spi_master_get_devdata(master);
1104 /* Disable the SSP now */
1105 pxa2xx_spi_write(drv_data, SSCR0,
1106 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1111 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1112 struct pxa2xx_spi_chip *chip_info)
1116 if (chip == NULL || chip_info == NULL)
1119 /* NOTE: setup() can be called multiple times, possibly with
1120 * different chip_info, release previously requested GPIO
1122 if (gpio_is_valid(chip->gpio_cs))
1123 gpio_free(chip->gpio_cs);
1125 /* If (*cs_control) is provided, ignore GPIO chip select */
1126 if (chip_info->cs_control) {
1127 chip->cs_control = chip_info->cs_control;
1131 if (gpio_is_valid(chip_info->gpio_cs)) {
1132 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1134 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1135 chip_info->gpio_cs);
1139 chip->gpio_cs = chip_info->gpio_cs;
1140 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1142 err = gpio_direction_output(chip->gpio_cs,
1143 !chip->gpio_cs_inverted);
1149 static int setup(struct spi_device *spi)
1151 struct pxa2xx_spi_chip *chip_info = NULL;
1152 struct chip_data *chip;
1153 const struct lpss_config *config;
1154 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1155 uint tx_thres, tx_hi_thres, rx_thres;
1157 switch (drv_data->ssp_type) {
1158 case QUARK_X1000_SSP:
1159 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1161 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1167 config = lpss_get_config(drv_data);
1168 tx_thres = config->tx_threshold_lo;
1169 tx_hi_thres = config->tx_threshold_hi;
1170 rx_thres = config->rx_threshold;
1173 tx_thres = TX_THRESH_DFLT;
1175 rx_thres = RX_THRESH_DFLT;
1179 /* Only alloc on first setup */
1180 chip = spi_get_ctldata(spi);
1182 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1186 if (drv_data->ssp_type == CE4100_SSP) {
1187 if (spi->chip_select > 4) {
1189 "failed setup: cs number must not be > 4.\n");
1194 chip->frm = spi->chip_select;
1197 chip->enable_dma = 0;
1198 chip->timeout = TIMOUT_DFLT;
1201 /* protocol drivers may change the chip settings, so...
1202 * if chip_info exists, use it */
1203 chip_info = spi->controller_data;
1205 /* chip_info isn't always needed */
1208 if (chip_info->timeout)
1209 chip->timeout = chip_info->timeout;
1210 if (chip_info->tx_threshold)
1211 tx_thres = chip_info->tx_threshold;
1212 if (chip_info->tx_hi_threshold)
1213 tx_hi_thres = chip_info->tx_hi_threshold;
1214 if (chip_info->rx_threshold)
1215 rx_thres = chip_info->rx_threshold;
1216 chip->enable_dma = drv_data->master_info->enable_dma;
1217 chip->dma_threshold = 0;
1218 if (chip_info->enable_loopback)
1219 chip->cr1 = SSCR1_LBM;
1220 } else if (ACPI_HANDLE(&spi->dev)) {
1222 * Slave devices enumerated from ACPI namespace don't
1223 * usually have chip_info but we still might want to use
1226 chip->enable_dma = drv_data->master_info->enable_dma;
1229 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1230 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1231 | SSITF_TxHiThresh(tx_hi_thres);
1233 /* set dma burst and threshold outside of chip_info path so that if
1234 * chip_info goes away after setting chip->enable_dma, the
1235 * burst and threshold can still respond to changes in bits_per_word */
1236 if (chip->enable_dma) {
1237 /* set up legal burst and threshold for dma */
1238 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1240 &chip->dma_burst_size,
1241 &chip->dma_threshold)) {
1243 "in setup: DMA burst size reduced to match bits_per_word\n");
1247 switch (drv_data->ssp_type) {
1248 case QUARK_X1000_SSP:
1249 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1250 & QUARK_X1000_SSCR1_RFT)
1251 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1252 & QUARK_X1000_SSCR1_TFT);
1255 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1256 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1260 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1261 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1262 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1264 if (spi->mode & SPI_LOOP)
1265 chip->cr1 |= SSCR1_LBM;
1267 if (spi->bits_per_word <= 8) {
1269 chip->read = u8_reader;
1270 chip->write = u8_writer;
1271 } else if (spi->bits_per_word <= 16) {
1273 chip->read = u16_reader;
1274 chip->write = u16_writer;
1275 } else if (spi->bits_per_word <= 32) {
1277 chip->read = u32_reader;
1278 chip->write = u32_writer;
1281 spi_set_ctldata(spi, chip);
1283 if (drv_data->ssp_type == CE4100_SSP)
1286 return setup_cs(spi, chip, chip_info);
1289 static void cleanup(struct spi_device *spi)
1291 struct chip_data *chip = spi_get_ctldata(spi);
1292 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1297 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1298 gpio_free(chip->gpio_cs);
1306 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1307 { "INT33C0", LPSS_LPT_SSP },
1308 { "INT33C1", LPSS_LPT_SSP },
1309 { "INT3430", LPSS_LPT_SSP },
1310 { "INT3431", LPSS_LPT_SSP },
1311 { "80860F0E", LPSS_BYT_SSP },
1312 { "8086228E", LPSS_BYT_SSP },
1315 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1317 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1322 if (adev && adev->pnp.unique_id &&
1323 !kstrtouint(adev->pnp.unique_id, 0, &devid))
1327 #else /* !CONFIG_ACPI */
1328 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1335 * PCI IDs of compound devices that integrate both host controller and private
1336 * integrated DMA engine. Please note these are not used in module
1337 * autoloading and probing in this module but matching the LPSS SSP type.
1339 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1341 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1342 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1344 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1345 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1347 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1348 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1349 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1351 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1352 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1353 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1357 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1359 struct device *dev = param;
1361 if (dev != chan->device->dev->parent)
1367 static struct pxa2xx_spi_master *
1368 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1370 struct pxa2xx_spi_master *pdata;
1371 struct acpi_device *adev;
1372 struct ssp_device *ssp;
1373 struct resource *res;
1374 const struct acpi_device_id *adev_id = NULL;
1375 const struct pci_device_id *pcidev_id = NULL;
1378 adev = ACPI_COMPANION(&pdev->dev);
1380 if (dev_is_pci(pdev->dev.parent))
1381 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1382 to_pci_dev(pdev->dev.parent));
1384 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1390 type = (int)adev_id->driver_data;
1392 type = (int)pcidev_id->driver_data;
1396 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1400 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1406 ssp->phys_base = res->start;
1407 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1408 if (IS_ERR(ssp->mmio_base))
1412 pdata->tx_param = pdev->dev.parent;
1413 pdata->rx_param = pdev->dev.parent;
1414 pdata->dma_filter = pxa2xx_spi_idma_filter;
1417 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1418 ssp->irq = platform_get_irq(pdev, 0);
1421 ssp->port_id = pxa2xx_spi_get_port_id(adev);
1423 pdata->num_chipselect = 1;
1424 pdata->enable_dma = true;
1429 #else /* !CONFIG_PCI */
1430 static inline struct pxa2xx_spi_master *
1431 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1437 static int pxa2xx_spi_probe(struct platform_device *pdev)
1439 struct device *dev = &pdev->dev;
1440 struct pxa2xx_spi_master *platform_info;
1441 struct spi_master *master;
1442 struct driver_data *drv_data;
1443 struct ssp_device *ssp;
1444 const struct lpss_config *config;
1448 platform_info = dev_get_platdata(dev);
1449 if (!platform_info) {
1450 platform_info = pxa2xx_spi_init_pdata(pdev);
1451 if (!platform_info) {
1452 dev_err(&pdev->dev, "missing platform data\n");
1457 ssp = pxa_ssp_request(pdev->id, pdev->name);
1459 ssp = &platform_info->ssp;
1461 if (!ssp->mmio_base) {
1462 dev_err(&pdev->dev, "failed to get ssp\n");
1466 master = spi_alloc_master(dev, sizeof(struct driver_data));
1468 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1472 drv_data = spi_master_get_devdata(master);
1473 drv_data->master = master;
1474 drv_data->master_info = platform_info;
1475 drv_data->pdev = pdev;
1476 drv_data->ssp = ssp;
1478 master->dev.parent = &pdev->dev;
1479 master->dev.of_node = pdev->dev.of_node;
1480 /* the spi->mode bits understood by this driver: */
1481 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1483 master->bus_num = ssp->port_id;
1484 master->dma_alignment = DMA_ALIGNMENT;
1485 master->cleanup = cleanup;
1486 master->setup = setup;
1487 master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1488 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1489 master->auto_runtime_pm = true;
1491 drv_data->ssp_type = ssp->type;
1493 drv_data->ioaddr = ssp->mmio_base;
1494 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1495 if (pxa25x_ssp_comp(drv_data)) {
1496 switch (drv_data->ssp_type) {
1497 case QUARK_X1000_SSP:
1498 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1501 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1505 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1506 drv_data->dma_cr1 = 0;
1507 drv_data->clear_sr = SSSR_ROR;
1508 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1510 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1511 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1512 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1513 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1514 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1517 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1520 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1521 goto out_error_master_alloc;
1524 /* Setup DMA if requested */
1525 if (platform_info->enable_dma) {
1526 status = pxa2xx_spi_dma_setup(drv_data);
1528 dev_dbg(dev, "no DMA channels available, using PIO\n");
1529 platform_info->enable_dma = false;
1533 /* Enable SOC clock */
1534 clk_prepare_enable(ssp->clk);
1536 master->max_speed_hz = clk_get_rate(ssp->clk);
1538 /* Load default SSP configuration */
1539 pxa2xx_spi_write(drv_data, SSCR0, 0);
1540 switch (drv_data->ssp_type) {
1541 case QUARK_X1000_SSP:
1542 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT)
1543 | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1544 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1546 /* using the Motorola SPI protocol and use 8 bit frame */
1547 pxa2xx_spi_write(drv_data, SSCR0,
1548 QUARK_X1000_SSCR0_Motorola
1549 | QUARK_X1000_SSCR0_DataSize(8));
1552 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1553 SSCR1_TxTresh(TX_THRESH_DFLT);
1554 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1555 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1556 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1560 if (!pxa25x_ssp_comp(drv_data))
1561 pxa2xx_spi_write(drv_data, SSTO, 0);
1563 if (!is_quark_x1000_ssp(drv_data))
1564 pxa2xx_spi_write(drv_data, SSPSP, 0);
1566 if (is_lpss_ssp(drv_data))
1567 lpss_ssp_setup(drv_data);
1569 if (is_lpss_ssp(drv_data)) {
1570 lpss_ssp_setup(drv_data);
1571 config = lpss_get_config(drv_data);
1572 if (config->reg_capabilities >= 0) {
1573 tmp = __lpss_ssp_read_priv(drv_data,
1574 config->reg_capabilities);
1575 tmp &= LPSS_CAPS_CS_EN_MASK;
1576 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1577 platform_info->num_chipselect = ffz(tmp);
1580 master->num_chipselect = platform_info->num_chipselect;
1582 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1583 (unsigned long)drv_data);
1585 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1586 pm_runtime_use_autosuspend(&pdev->dev);
1587 pm_runtime_set_active(&pdev->dev);
1588 pm_runtime_enable(&pdev->dev);
1590 /* Register with the SPI framework */
1591 platform_set_drvdata(pdev, drv_data);
1592 status = devm_spi_register_master(&pdev->dev, master);
1594 dev_err(&pdev->dev, "problem registering spi master\n");
1595 goto out_error_clock_enabled;
1600 out_error_clock_enabled:
1601 clk_disable_unprepare(ssp->clk);
1602 pxa2xx_spi_dma_release(drv_data);
1603 free_irq(ssp->irq, drv_data);
1605 out_error_master_alloc:
1606 spi_master_put(master);
1611 static int pxa2xx_spi_remove(struct platform_device *pdev)
1613 struct driver_data *drv_data = platform_get_drvdata(pdev);
1614 struct ssp_device *ssp;
1618 ssp = drv_data->ssp;
1620 pm_runtime_get_sync(&pdev->dev);
1622 /* Disable the SSP at the peripheral and SOC level */
1623 pxa2xx_spi_write(drv_data, SSCR0, 0);
1624 clk_disable_unprepare(ssp->clk);
1627 if (drv_data->master_info->enable_dma)
1628 pxa2xx_spi_dma_release(drv_data);
1630 pm_runtime_put_noidle(&pdev->dev);
1631 pm_runtime_disable(&pdev->dev);
1634 free_irq(ssp->irq, drv_data);
1642 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1646 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1647 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1650 #ifdef CONFIG_PM_SLEEP
1651 static int pxa2xx_spi_suspend(struct device *dev)
1653 struct driver_data *drv_data = dev_get_drvdata(dev);
1654 struct ssp_device *ssp = drv_data->ssp;
1657 status = spi_master_suspend(drv_data->master);
1660 pxa2xx_spi_write(drv_data, SSCR0, 0);
1662 if (!pm_runtime_suspended(dev))
1663 clk_disable_unprepare(ssp->clk);
1668 static int pxa2xx_spi_resume(struct device *dev)
1670 struct driver_data *drv_data = dev_get_drvdata(dev);
1671 struct ssp_device *ssp = drv_data->ssp;
1674 /* Enable the SSP clock */
1675 if (!pm_runtime_suspended(dev))
1676 clk_prepare_enable(ssp->clk);
1678 /* Restore LPSS private register bits */
1679 if (is_lpss_ssp(drv_data))
1680 lpss_ssp_setup(drv_data);
1682 /* Start the queue running */
1683 status = spi_master_resume(drv_data->master);
1685 dev_err(dev, "problem starting queue (%d)\n", status);
1694 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1696 struct driver_data *drv_data = dev_get_drvdata(dev);
1698 clk_disable_unprepare(drv_data->ssp->clk);
1702 static int pxa2xx_spi_runtime_resume(struct device *dev)
1704 struct driver_data *drv_data = dev_get_drvdata(dev);
1706 clk_prepare_enable(drv_data->ssp->clk);
1711 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1712 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1713 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1714 pxa2xx_spi_runtime_resume, NULL)
1717 static struct platform_driver driver = {
1719 .name = "pxa2xx-spi",
1720 .pm = &pxa2xx_spi_pm_ops,
1721 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1723 .probe = pxa2xx_spi_probe,
1724 .remove = pxa2xx_spi_remove,
1725 .shutdown = pxa2xx_spi_shutdown,
1728 static int __init pxa2xx_spi_init(void)
1730 return platform_driver_register(&driver);
1732 subsys_initcall(pxa2xx_spi_init);
1734 static void __exit pxa2xx_spi_exit(void)
1736 platform_driver_unregister(&driver);
1738 module_exit(pxa2xx_spi_exit);