drivers/spi/spi-orion.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Marvell Orion SPI controller driver
   4  *
   5  * Author: Shadi Ammouri <shadi@marvell.com>
   6  * Copyright (C) 2007-2008 Marvell Ltd.
   7  */
   8
   9 #include <linux/interrupt.h>
  10 #include <linux/delay.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/module.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/of.h>
  18 #include <linux/of_address.h>
  19 #include <linux/clk.h>
  20 #include <linux/sizes.h>
  21 #include <asm/unaligned.h>
  22
  23 #define DRIVER_NAME                     "orion_spi"
  24
  25 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */
  26 #define SPI_AUTOSUSPEND_TIMEOUT         200
  27
  28 /* Some SoCs using this driver support up to 8 chip selects.
  29  * It is up to the implementer to only use the chip selects
  30  * that are available.
  31  */
  32 #define ORION_NUM_CHIPSELECTS           8
  33
  34 #define ORION_SPI_WAIT_RDY_MAX_LOOP     2000 /* in usec */
  35
  36 #define ORION_SPI_IF_CTRL_REG           0x00
  37 #define ORION_SPI_IF_CONFIG_REG         0x04
  38 #define ORION_SPI_IF_RXLSBF             BIT(14)
  39 #define ORION_SPI_IF_TXLSBF             BIT(13)
  40 #define ORION_SPI_DATA_OUT_REG          0x08
  41 #define ORION_SPI_DATA_IN_REG           0x0c
  42 #define ORION_SPI_INT_CAUSE_REG         0x10
  43 #define ORION_SPI_TIMING_PARAMS_REG     0x18
  44
  45 /* Register for the "Direct Mode" */
  46 #define SPI_DIRECT_WRITE_CONFIG_REG     0x20
  47
  48 #define ORION_SPI_TMISO_SAMPLE_MASK     (0x3 << 6)
  49 #define ORION_SPI_TMISO_SAMPLE_1        (1 << 6)
  50 #define ORION_SPI_TMISO_SAMPLE_2        (2 << 6)
  51
  52 #define ORION_SPI_MODE_CPOL             (1 << 11)
  53 #define ORION_SPI_MODE_CPHA             (1 << 12)
  54 #define ORION_SPI_IF_8_16_BIT_MODE      (1 << 5)
  55 #define ORION_SPI_CLK_PRESCALE_MASK     0x1F
  56 #define ARMADA_SPI_CLK_PRESCALE_MASK    0xDF
  57 #define ORION_SPI_MODE_MASK             (ORION_SPI_MODE_CPOL | \
  58                                          ORION_SPI_MODE_CPHA)
  59 #define ORION_SPI_CS_MASK       0x1C
  60 #define ORION_SPI_CS_SHIFT      2
  61 #define ORION_SPI_CS(cs)        ((cs << ORION_SPI_CS_SHIFT) & \
  62                                         ORION_SPI_CS_MASK)
  63
  64 enum orion_spi_type {
  65         ORION_SPI,
  66         ARMADA_SPI,
  67 };
  68
  69 struct orion_spi_dev {
  70         enum orion_spi_type     typ;
  71         /*
  72          * min_divisor and max_hz should be exclusive, the only we can
  73          * have both is for managing the armada-370-spi case with old
  74          * device tree
  75          */
  76         unsigned long           max_hz;
  77         unsigned int            min_divisor;
  78         unsigned int            max_divisor;
  79         u32                     prescale_mask;
  80         bool                    is_errata_50mhz_ac;
  81 };
  82
  83 struct orion_direct_acc {
  84         void __iomem            *vaddr;
  85         u32                     size;
  86 };
  87
  88 struct orion_child_options {
  89         struct orion_direct_acc direct_access;
  90 };
  91
  92 struct orion_spi {
  93         struct spi_controller   *host;
  94         void __iomem            *base;
  95         struct clk              *clk;
  96         struct clk              *axi_clk;
  97         const struct orion_spi_dev *devdata;
  98         struct device           *dev;
  99
 100         struct orion_child_options      child[ORION_NUM_CHIPSELECTS];
 101 };
 102
 103 #ifdef CONFIG_PM
 104 static int orion_spi_runtime_suspend(struct device *dev);
 105 static int orion_spi_runtime_resume(struct device *dev);
 106 #endif
 107
 108 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
 109 {
 110         return orion_spi->base + reg;
 111 }
 112
 113 static inline void
 114 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
 115 {
 116         void __iomem *reg_addr = spi_reg(orion_spi, reg);
 117         u32 val;
 118
 119         val = readl(reg_addr);
 120         val |= mask;
 121         writel(val, reg_addr);
 122 }
 123
 124 static inline void
 125 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
 126 {
 127         void __iomem *reg_addr = spi_reg(orion_spi, reg);
 128         u32 val;
 129
 130         val = readl(reg_addr);
 131         val &= ~mask;
 132         writel(val, reg_addr);
 133 }
 134
 135 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
 136 {
 137         u32 tclk_hz;
 138         u32 rate;
 139         u32 prescale;
 140         u32 reg;
 141         struct orion_spi *orion_spi;
 142         const struct orion_spi_dev *devdata;
 143
 144         orion_spi = spi_controller_get_devdata(spi->controller);
 145         devdata = orion_spi->devdata;
 146
 147         tclk_hz = clk_get_rate(orion_spi->clk);
 148
 149         if (devdata->typ == ARMADA_SPI) {
 150                 /*
 151                  * Given the core_clk (tclk_hz) and the target rate (speed) we
 152                  * determine the best values for SPR (in [0 .. 15]) and SPPR (in
 153                  * [0..7]) such that
 154                  *
 155                  *      core_clk / (SPR * 2 ** SPPR)
 156                  *
 157                  * is as big as possible but not bigger than speed.
 158                  */
 159
 160                 /* best integer divider: */
 161                 unsigned divider = DIV_ROUND_UP(tclk_hz, speed);
 162                 unsigned spr, sppr;
 163
 164                 if (divider < 16) {
 165                         /* This is the easy case, divider is less than 16 */
 166                         spr = divider;
 167                         sppr = 0;
 168
 169                 } else {
 170                         unsigned two_pow_sppr;
 171                         /*
 172                          * Find the highest bit set in divider. This and the
 173                          * three next bits define SPR (apart from rounding).
 174                          * SPPR is then the number of zero bits that must be
 175                          * appended:
 176                          */
 177                         sppr = fls(divider) - 4;
 178
 179                         /*
 180                          * As SPR only has 4 bits, we have to round divider up
 181                          * to the next multiple of 2 ** sppr.
 182                          */
 183                         two_pow_sppr = 1 << sppr;
 184                         divider = (divider + two_pow_sppr - 1) & -two_pow_sppr;
 185
 186                         /*
 187                          * recalculate sppr as rounding up divider might have
 188                          * increased it enough to change the position of the
 189                          * highest set bit. In this case the bit that now
 190                          * doesn't make it into SPR is 0, so there is no need to
 191                          * round again.
 192                          */
 193                         sppr = fls(divider) - 4;
 194                         spr = divider >> sppr;
 195
 196                         /*
 197                          * Now do range checking. SPR is constructed to have a
 198                          * width of 4 bits, so this is fine for sure. So we
 199                          * still need to check for sppr to fit into 3 bits:
 200                          */
 201                         if (sppr > 7)
 202                                 return -EINVAL;
 203                 }
 204
 205                 prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr;
 206         } else {
 207                 /*
 208                  * the supported rates are: 4,6,8...30
 209                  * round up as we look for equal or less speed
 210                  */
 211                 rate = DIV_ROUND_UP(tclk_hz, speed);
 212                 rate = roundup(rate, 2);
 213
 214                 /* check if requested speed is too small */
 215                 if (rate > 30)
 216                         return -EINVAL;
 217
 218                 if (rate < 4)
 219                         rate = 4;
 220
 221                 /* Convert the rate to SPI clock divisor value. */
 222                 prescale = 0x10 + rate/2;
 223         }
 224
 225         reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
 226         reg = ((reg & ~devdata->prescale_mask) | prescale);
 227         writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
 228
 229         return 0;
 230 }
 231
 232 static void
 233 orion_spi_mode_set(struct spi_device *spi)
 234 {
 235         u32 reg;
 236         struct orion_spi *orion_spi;
 237
 238         orion_spi = spi_controller_get_devdata(spi->controller);
 239
 240         reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
 241         reg &= ~ORION_SPI_MODE_MASK;
 242         if (spi->mode & SPI_CPOL)
 243                 reg |= ORION_SPI_MODE_CPOL;
 244         if (spi->mode & SPI_CPHA)
 245                 reg |= ORION_SPI_MODE_CPHA;
 246         if (spi->mode & SPI_LSB_FIRST)
 247                 reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF;
 248         else
 249                 reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF);
 250
 251         writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
 252 }
 253
 254 static void
 255 orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed)
 256 {
 257         u32 reg;
 258         struct orion_spi *orion_spi;
 259
 260         orion_spi = spi_controller_get_devdata(spi->controller);
 261
 262         /*
 263          * Erratum description: (Erratum NO. FE-9144572) The device
 264          * SPI interface supports frequencies of up to 50 MHz.
 265          * However, due to this erratum, when the device core clock is
 266          * 250 MHz and the SPI interfaces is configured for 50MHz SPI
 267          * clock and CPOL=CPHA=1 there might occur data corruption on
 268          * reads from the SPI device.
 269          * Erratum Workaround:
 270          * Work in one of the following configurations:
 271          * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
 272          * Register".
 273          * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
 274          * Register" before setting the interface.
 275          */
 276         reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
 277         reg &= ~ORION_SPI_TMISO_SAMPLE_MASK;
 278
 279         if (clk_get_rate(orion_spi->clk) == 250000000 &&
 280                         speed == 50000000 && spi->mode & SPI_CPOL &&
 281                         spi->mode & SPI_CPHA)
 282                 reg |= ORION_SPI_TMISO_SAMPLE_2;
 283         else
 284                 reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */
 285
 286         writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
 287 }
 288
 289 /*
 290  * called only when no transfer is active on the bus
 291  */
 292 static int
 293 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 294 {
 295         struct orion_spi *orion_spi;
 296         unsigned int speed = spi->max_speed_hz;
 297         unsigned int bits_per_word = spi->bits_per_word;
 298         int     rc;
 299
 300         orion_spi = spi_controller_get_devdata(spi->controller);
 301
 302         if ((t != NULL) && t->speed_hz)
 303                 speed = t->speed_hz;
 304
 305         if ((t != NULL) && t->bits_per_word)
 306                 bits_per_word = t->bits_per_word;
 307
 308         orion_spi_mode_set(spi);
 309
 310         if (orion_spi->devdata->is_errata_50mhz_ac)
 311                 orion_spi_50mhz_ac_timing_erratum(spi, speed);
 312
 313         rc = orion_spi_baudrate_set(spi, speed);
 314         if (rc)
 315                 return rc;
 316
 317         if (bits_per_word == 16)
 318                 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
 319                                   ORION_SPI_IF_8_16_BIT_MODE);
 320         else
 321                 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
 322                                   ORION_SPI_IF_8_16_BIT_MODE);
 323
 324         return 0;
 325 }
 326
 327 static void orion_spi_set_cs(struct spi_device *spi, bool enable)
 328 {
 329         struct orion_spi *orion_spi;
 330         void __iomem *ctrl_reg;
 331         u32 val;
 332
 333         orion_spi = spi_controller_get_devdata(spi->controller);
 334         ctrl_reg = spi_reg(orion_spi, ORION_SPI_IF_CTRL_REG);
 335
 336         val = readl(ctrl_reg);
 337
 338         /* Clear existing chip-select and assertion state */
 339         val &= ~(ORION_SPI_CS_MASK | 0x1);
 340
 341         /*
 342          * If this line is using a GPIO to control chip select, this internal
 343          * .set_cs() function will still be called, so we clear any previous
 344          * chip select. The CS we activate will not have any elecrical effect,
 345          * as it is handled by a GPIO, but that doesn't matter. What we need
 346          * is to deassert the old chip select and assert some other chip select.
 347          */
 348         val |= ORION_SPI_CS(spi_get_chipselect(spi, 0));
 349
 350         /*
 351          * Chip select logic is inverted from spi_set_cs(). For lines using a
 352          * GPIO to do chip select SPI_CS_HIGH is enforced and inversion happens
 353          * in the GPIO library, but we don't care about that, because in those
 354          * cases we are dealing with an unused native CS anyways so the polarity
 355          * doesn't matter.
 356          */
 357         if (!enable)
 358                 val |= 0x1;
 359
 360         /*
 361          * To avoid toggling unwanted chip selects update the register
 362          * with a single write.
 363          */
 364         writel(val, ctrl_reg);
 365 }
 366
 367 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
 368 {
 369         int i;
 370
 371         for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
 372                 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
 373                         return 1;
 374
 375                 udelay(1);
 376         }
 377
 378         return -1;
 379 }
 380
 381 static inline int
 382 orion_spi_write_read_8bit(struct spi_device *spi,
 383                           const u8 **tx_buf, u8 **rx_buf)
 384 {
 385         void __iomem *tx_reg, *rx_reg, *int_reg;
 386         struct orion_spi *orion_spi;
 387         bool cs_single_byte;
 388
 389         cs_single_byte = spi->mode & SPI_CS_WORD;
 390
 391         orion_spi = spi_controller_get_devdata(spi->controller);
 392
 393         if (cs_single_byte)
 394                 orion_spi_set_cs(spi, 0);
 395
 396         tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
 397         rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
 398         int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
 399
 400         /* clear the interrupt cause register */
 401         writel(0x0, int_reg);
 402
 403         if (tx_buf && *tx_buf)
 404                 writel(*(*tx_buf)++, tx_reg);
 405         else
 406                 writel(0, tx_reg);
 407
 408         if (orion_spi_wait_till_ready(orion_spi) < 0) {
 409                 if (cs_single_byte) {
 410                         orion_spi_set_cs(spi, 1);
 411                         /* Satisfy some SLIC devices requirements */
 412                         udelay(4);
 413                 }
 414                 dev_err(&spi->dev, "TXS timed out\n");
 415                 return -1;
 416         }
 417
 418         if (rx_buf && *rx_buf)
 419                 *(*rx_buf)++ = readl(rx_reg);
 420
 421         if (cs_single_byte) {
 422                 orion_spi_set_cs(spi, 1);
 423                 /* Satisfy some SLIC devices requirements */
 424                 udelay(4);
 425         }
 426
 427         return 1;
 428 }
 429
 430 static inline int
 431 orion_spi_write_read_16bit(struct spi_device *spi,
 432                            const u16 **tx_buf, u16 **rx_buf)
 433 {
 434         void __iomem *tx_reg, *rx_reg, *int_reg;
 435         struct orion_spi *orion_spi;
 436
 437         if (spi->mode & SPI_CS_WORD) {
 438                 dev_err(&spi->dev, "SPI_CS_WORD is only supported for 8 bit words\n");
 439                 return -1;
 440         }
 441
 442         orion_spi = spi_controller_get_devdata(spi->controller);
 443         tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
 444         rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
 445         int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
 446
 447         /* clear the interrupt cause register */
 448         writel(0x0, int_reg);
 449
 450         if (tx_buf && *tx_buf)
 451                 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
 452         else
 453                 writel(0, tx_reg);
 454
 455         if (orion_spi_wait_till_ready(orion_spi) < 0) {
 456                 dev_err(&spi->dev, "TXS timed out\n");
 457                 return -1;
 458         }
 459
 460         if (rx_buf && *rx_buf)
 461                 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
 462
 463         return 1;
 464 }
 465
 466 static unsigned int
 467 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
 468 {
 469         unsigned int count;
 470         int word_len;
 471         struct orion_spi *orion_spi;
 472         int cs = spi_get_chipselect(spi, 0);
 473         void __iomem *vaddr;
 474
 475         word_len = spi->bits_per_word;
 476         count = xfer->len;
 477
 478         orion_spi = spi_controller_get_devdata(spi->controller);
 479
 480         /*
 481          * Use SPI direct write mode if base address is available
 482          * and SPI_CS_WORD flag is not set.
 483          * Otherwise fall back to PIO mode for this transfer.
 484          */
 485         vaddr = orion_spi->child[cs].direct_access.vaddr;
 486
 487         if (vaddr && xfer->tx_buf && word_len == 8 && (spi->mode & SPI_CS_WORD) == 0) {
 488                 unsigned int cnt = count / 4;
 489                 unsigned int rem = count % 4;
 490
 491                 /*
 492                  * Send the TX-data to the SPI device via the direct
 493                  * mapped address window
 494                  */
 495                 iowrite32_rep(vaddr, xfer->tx_buf, cnt);
 496                 if (rem) {
 497                         u32 *buf = (u32 *)xfer->tx_buf;
 498
 499                         iowrite8_rep(vaddr, &buf[cnt], rem);
 500                 }
 501
 502                 return count;
 503         }
 504
 505         if (word_len == 8) {
 506                 const u8 *tx = xfer->tx_buf;
 507                 u8 *rx = xfer->rx_buf;
 508
 509                 do {
 510                         if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
 511                                 goto out;
 512                         count--;
 513                         spi_delay_exec(&xfer->word_delay, xfer);
 514                 } while (count);
 515         } else if (word_len == 16) {
 516                 const u16 *tx = xfer->tx_buf;
 517                 u16 *rx = xfer->rx_buf;
 518
 519                 do {
 520                         if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
 521                                 goto out;
 522                         count -= 2;
 523                         spi_delay_exec(&xfer->word_delay, xfer);
 524                 } while (count);
 525         }
 526
 527 out:
 528         return xfer->len - count;
 529 }
 530
 531 static int orion_spi_transfer_one(struct spi_controller *host,
 532                                         struct spi_device *spi,
 533                                         struct spi_transfer *t)
 534 {
 535         int status = 0;
 536
 537         status = orion_spi_setup_transfer(spi, t);
 538         if (status < 0)
 539                 return status;
 540
 541         if (t->len)
 542                 orion_spi_write_read(spi, t);
 543
 544         return status;
 545 }
 546
 547 static int orion_spi_setup(struct spi_device *spi)
 548 {
 549         int ret;
 550 #ifdef CONFIG_PM
 551         struct orion_spi *orion_spi = spi_controller_get_devdata(spi->controller);
 552         struct device *dev = orion_spi->dev;
 553
 554         orion_spi_runtime_resume(dev);
 555 #endif
 556
 557         ret = orion_spi_setup_transfer(spi, NULL);
 558
 559 #ifdef CONFIG_PM
 560         orion_spi_runtime_suspend(dev);
 561 #endif
 562
 563         return ret;
 564 }
 565
 566 static int orion_spi_reset(struct orion_spi *orion_spi)
 567 {
 568         /* Verify that the CS is deasserted */
 569         orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
 570
 571         /* Don't deassert CS between the direct mapped SPI transfers */
 572         writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG));
 573
 574         return 0;
 575 }
 576
 577 static const struct orion_spi_dev orion_spi_dev_data = {
 578         .typ = ORION_SPI,
 579         .min_divisor = 4,
 580         .max_divisor = 30,
 581         .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK,
 582 };
 583
 584 static const struct orion_spi_dev armada_370_spi_dev_data = {
 585         .typ = ARMADA_SPI,
 586         .min_divisor = 4,
 587         .max_divisor = 1920,
 588         .max_hz = 50000000,
 589         .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
 590 };
 591
 592 static const struct orion_spi_dev armada_xp_spi_dev_data = {
 593         .typ = ARMADA_SPI,
 594         .max_hz = 50000000,
 595         .max_divisor = 1920,
 596         .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
 597 };
 598
 599 static const struct orion_spi_dev armada_375_spi_dev_data = {
 600         .typ = ARMADA_SPI,
 601         .min_divisor = 15,
 602         .max_divisor = 1920,
 603         .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
 604 };
 605
 606 static const struct orion_spi_dev armada_380_spi_dev_data = {
 607         .typ = ARMADA_SPI,
 608         .max_hz = 50000000,
 609         .max_divisor = 1920,
 610         .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
 611         .is_errata_50mhz_ac = true,
 612 };
 613
 614 static const struct of_device_id orion_spi_of_match_table[] = {
 615         {
 616                 .compatible = "marvell,orion-spi",
 617                 .data = &orion_spi_dev_data,
 618         },
 619         {
 620                 .compatible = "marvell,armada-370-spi",
 621                 .data = &armada_370_spi_dev_data,
 622         },
 623         {
 624                 .compatible = "marvell,armada-375-spi",
 625                 .data = &armada_375_spi_dev_data,
 626         },
 627         {
 628                 .compatible = "marvell,armada-380-spi",
 629                 .data = &armada_380_spi_dev_data,
 630         },
 631         {
 632                 .compatible = "marvell,armada-390-spi",
 633                 .data = &armada_xp_spi_dev_data,
 634         },
 635         {
 636                 .compatible = "marvell,armada-xp-spi",
 637                 .data = &armada_xp_spi_dev_data,
 638         },
 639
 640         {}
 641 };
 642 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
 643
 644 static int orion_spi_probe(struct platform_device *pdev)
 645 {
 646         const struct orion_spi_dev *devdata;
 647         struct spi_controller *host;
 648         struct orion_spi *spi;
 649         struct resource *r;
 650         unsigned long tclk_hz;
 651         int status = 0;
 652         struct device_node *np;
 653
 654         host = spi_alloc_host(&pdev->dev, sizeof(*spi));
 655         if (host == NULL) {
 656                 dev_dbg(&pdev->dev, "host allocation failed\n");
 657                 return -ENOMEM;
 658         }
 659
 660         if (pdev->id != -1)
 661                 host->bus_num = pdev->id;
 662         if (pdev->dev.of_node) {
 663                 u32 cell_index;
 664
 665                 if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
 666                                           &cell_index))
 667                         host->bus_num = cell_index;
 668         }
 669
 670         /* we support all 4 SPI modes and LSB first option */
 671         host->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST | SPI_CS_WORD;
 672         host->set_cs = orion_spi_set_cs;
 673         host->transfer_one = orion_spi_transfer_one;
 674         host->num_chipselect = ORION_NUM_CHIPSELECTS;
 675         host->setup = orion_spi_setup;
 676         host->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
 677         host->auto_runtime_pm = true;
 678         host->use_gpio_descriptors = true;
 679         host->flags = SPI_CONTROLLER_GPIO_SS;
 680
 681         platform_set_drvdata(pdev, host);
 682
 683         spi = spi_controller_get_devdata(host);
 684         spi->host = host;
 685         spi->dev = &pdev->dev;
 686
 687         devdata = device_get_match_data(&pdev->dev);
 688         devdata = devdata ? devdata : &orion_spi_dev_data;
 689         spi->devdata = devdata;
 690
 691         spi->clk = devm_clk_get(&pdev->dev, NULL);
 692         if (IS_ERR(spi->clk)) {
 693                 status = PTR_ERR(spi->clk);
 694                 goto out;
 695         }
 696
 697         status = clk_prepare_enable(spi->clk);
 698         if (status)
 699                 goto out;
 700
 701         /* The following clock is only used by some SoCs */
 702         spi->axi_clk = devm_clk_get(&pdev->dev, "axi");
 703         if (PTR_ERR(spi->axi_clk) == -EPROBE_DEFER) {
 704                 status = -EPROBE_DEFER;
 705                 goto out_rel_clk;
 706         }
 707         if (!IS_ERR(spi->axi_clk))
 708                 clk_prepare_enable(spi->axi_clk);
 709
 710         tclk_hz = clk_get_rate(spi->clk);
 711
 712         /*
 713          * With old device tree, armada-370-spi could be used with
 714          * Armada XP, however for this SoC the maximum frequency is
 715          * 50MHz instead of tclk/4. On Armada 370, tclk cannot be
 716          * higher than 200MHz. So, in order to be able to handle both
 717          * SoCs, we can take the minimum of 50MHz and tclk/4.
 718          */
 719         if (of_device_is_compatible(pdev->dev.of_node,
 720                                         "marvell,armada-370-spi"))
 721                 host->max_speed_hz = min(devdata->max_hz,
 722                                 DIV_ROUND_UP(tclk_hz, devdata->min_divisor));
 723         else if (devdata->min_divisor)
 724                 host->max_speed_hz =
 725                         DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
 726         else
 727                 host->max_speed_hz = devdata->max_hz;
 728         host->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
 729
 730         spi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
 731         if (IS_ERR(spi->base)) {
 732                 status = PTR_ERR(spi->base);
 733                 goto out_rel_axi_clk;
 734         }
 735
 736         for_each_available_child_of_node(pdev->dev.of_node, np) {
 737                 struct orion_direct_acc *dir_acc;
 738                 u32 cs;
 739
 740                 /* Get chip-select number from the "reg" property */
 741                 status = of_property_read_u32(np, "reg", &cs);
 742                 if (status) {
 743                         dev_err(&pdev->dev,
 744                                 "%pOF has no valid 'reg' property (%d)\n",
 745                                 np, status);
 746                         continue;
 747                 }
 748
 749                 /*
 750                  * Check if an address is configured for this SPI device. If
 751                  * not, the MBus mapping via the 'ranges' property in the 'soc'
 752                  * node is not configured and this device should not use the
 753                  * direct mode. In this case, just continue with the next
 754                  * device.
 755                  */
 756                 status = of_address_to_resource(pdev->dev.of_node, cs + 1, r);
 757                 if (status)
 758                         continue;
 759
 760                 /*
 761                  * Only map one page for direct access. This is enough for the
 762                  * simple TX transfer which only writes to the first word.
 763                  * This needs to get extended for the direct SPI NOR / SPI NAND
 764                  * support, once this gets implemented.
 765                  */
 766                 dir_acc = &spi->child[cs].direct_access;
 767                 dir_acc->vaddr = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE);
 768                 if (!dir_acc->vaddr) {
 769                         status = -ENOMEM;
 770                         of_node_put(np);
 771                         goto out_rel_axi_clk;
 772                 }
 773                 dir_acc->size = PAGE_SIZE;
 774
 775                 dev_info(&pdev->dev, "CS%d configured for direct access\n", cs);
 776         }
 777
 778         pm_runtime_set_active(&pdev->dev);
 779         pm_runtime_use_autosuspend(&pdev->dev);
 780         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
 781         pm_runtime_enable(&pdev->dev);
 782
 783         status = orion_spi_reset(spi);
 784         if (status < 0)
 785                 goto out_rel_pm;
 786
 787         host->dev.of_node = pdev->dev.of_node;
 788         status = spi_register_controller(host);
 789         if (status < 0)
 790                 goto out_rel_pm;
 791
 792         return status;
 793
 794 out_rel_pm:
 795         pm_runtime_disable(&pdev->dev);
 796 out_rel_axi_clk:
 797         clk_disable_unprepare(spi->axi_clk);
 798 out_rel_clk:
 799         clk_disable_unprepare(spi->clk);
 800 out:
 801         spi_controller_put(host);
 802         return status;
 803 }
 804
 805
 806 static void orion_spi_remove(struct platform_device *pdev)
 807 {
 808         struct spi_controller *host = platform_get_drvdata(pdev);
 809         struct orion_spi *spi = spi_controller_get_devdata(host);
 810
 811         pm_runtime_get_sync(&pdev->dev);
 812         clk_disable_unprepare(spi->axi_clk);
 813         clk_disable_unprepare(spi->clk);
 814
 815         spi_unregister_controller(host);
 816         pm_runtime_disable(&pdev->dev);
 817 }
 818
 819 MODULE_ALIAS("platform:" DRIVER_NAME);
 820
 821 #ifdef CONFIG_PM
 822 static int orion_spi_runtime_suspend(struct device *dev)
 823 {
 824         struct spi_controller *host = dev_get_drvdata(dev);
 825         struct orion_spi *spi = spi_controller_get_devdata(host);
 826
 827         clk_disable_unprepare(spi->axi_clk);
 828         clk_disable_unprepare(spi->clk);
 829         return 0;
 830 }
 831
 832 static int orion_spi_runtime_resume(struct device *dev)
 833 {
 834         struct spi_controller *host = dev_get_drvdata(dev);
 835         struct orion_spi *spi = spi_controller_get_devdata(host);
 836
 837         if (!IS_ERR(spi->axi_clk))
 838                 clk_prepare_enable(spi->axi_clk);
 839         return clk_prepare_enable(spi->clk);
 840 }
 841 #endif
 842
 843 static const struct dev_pm_ops orion_spi_pm_ops = {
 844         SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
 845                            orion_spi_runtime_resume,
 846                            NULL)
 847 };
 848
 849 static struct platform_driver orion_spi_driver = {
 850         .driver = {
 851                 .name   = DRIVER_NAME,
 852                 .pm     = &orion_spi_pm_ops,
 853                 .of_match_table = of_match_ptr(orion_spi_of_match_table),
 854         },
 855         .probe          = orion_spi_probe,
 856         .remove_new     = orion_spi_remove,
 857 };
 858
 859 module_platform_driver(orion_spi_driver);
 860
 861 MODULE_DESCRIPTION("Orion SPI driver");
 862 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
 863 MODULE_LICENSE("GPL");