drivers/spi/spi-omap2-mcspi.c

   1 /*
   2  * OMAP2 McSPI controller driver
   3  *
   4  * Copyright (C) 2005, 2006 Nokia Corporation
   5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   6  *              Juha Yrj�l� <juha.yrjola@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/module.h>
  27 #include <linux/device.h>
  28 #include <linux/delay.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/dmaengine.h>
  31 #include <linux/omap-dma.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/err.h>
  34 #include <linux/clk.h>
  35 #include <linux/io.h>
  36 #include <linux/slab.h>
  37 #include <linux/pm_runtime.h>
  38 #include <linux/of.h>
  39 #include <linux/of_device.h>
  40 #include <linux/gcd.h>
  41
  42 #include <linux/spi/spi.h>
  43
  44 #include <linux/platform_data/spi-omap2-mcspi.h>
  45
  46 #define OMAP2_MCSPI_MAX_FREQ            48000000
  47 #define OMAP2_MCSPI_MAX_FIFODEPTH       64
  48 #define OMAP2_MCSPI_MAX_FIFOWCNT        0xFFFF
  49 #define SPI_AUTOSUSPEND_TIMEOUT         2000
  50
  51 #define OMAP2_MCSPI_REVISION            0x00
  52 #define OMAP2_MCSPI_SYSSTATUS           0x14
  53 #define OMAP2_MCSPI_IRQSTATUS           0x18
  54 #define OMAP2_MCSPI_IRQENABLE           0x1c
  55 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
  56 #define OMAP2_MCSPI_SYST                0x24
  57 #define OMAP2_MCSPI_MODULCTRL           0x28
  58 #define OMAP2_MCSPI_XFERLEVEL           0x7c
  59
  60 /* per-channel banks, 0x14 bytes each, first is: */
  61 #define OMAP2_MCSPI_CHCONF0             0x2c
  62 #define OMAP2_MCSPI_CHSTAT0             0x30
  63 #define OMAP2_MCSPI_CHCTRL0             0x34
  64 #define OMAP2_MCSPI_TX0                 0x38
  65 #define OMAP2_MCSPI_RX0                 0x3c
  66
  67 /* per-register bitmasks: */
  68 #define OMAP2_MCSPI_IRQSTATUS_EOW       BIT(17)
  69
  70 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
  71 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
  72 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
  73
  74 #define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
  75 #define OMAP2_MCSPI_CHCONF_POL          BIT(1)
  76 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  77 #define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
  78 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  79 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
  80 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
  81 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  82 #define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
  83 #define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
  84 #define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
  85 #define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
  86 #define OMAP2_MCSPI_CHCONF_IS           BIT(18)
  87 #define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
  88 #define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
  89 #define OMAP2_MCSPI_CHCONF_FFET         BIT(27)
  90 #define OMAP2_MCSPI_CHCONF_FFER         BIT(28)
  91
  92 #define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
  93 #define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
  94 #define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
  95 #define OMAP2_MCSPI_CHSTAT_TXFFE        BIT(3)
  96
  97 #define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
  98
  99 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
 100
 101 /* We have 2 DMA channels per CS, one for RX and one for TX */
 102 struct omap2_mcspi_dma {
 103         struct dma_chan *dma_tx;
 104         struct dma_chan *dma_rx;
 105
 106         int dma_tx_sync_dev;
 107         int dma_rx_sync_dev;
 108
 109         struct completion dma_tx_completion;
 110         struct completion dma_rx_completion;
 111
 112         char dma_rx_ch_name[14];
 113         char dma_tx_ch_name[14];
 114 };
 115
 116 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 117  * cache operations; better heuristics consider wordsize and bitrate.
 118  */
 119 #define DMA_MIN_BYTES                   160
 120
 121
 122 /*
 123  * Used for context save and restore, structure members to be updated whenever
 124  * corresponding registers are modified.
 125  */
 126 struct omap2_mcspi_regs {
 127         u32 modulctrl;
 128         u32 wakeupenable;
 129         struct list_head cs;
 130 };
 131
 132 struct omap2_mcspi {
 133         struct spi_master       *master;
 134         /* Virtual base address of the controller */
 135         void __iomem            *base;
 136         unsigned long           phys;
 137         /* SPI1 has 4 channels, while SPI2 has 2 */
 138         struct omap2_mcspi_dma  *dma_channels;
 139         struct device           *dev;
 140         struct omap2_mcspi_regs ctx;
 141         int                     fifo_depth;
 142         unsigned int            pin_dir:1;
 143 };
 144
 145 struct omap2_mcspi_cs {
 146         void __iomem            *base;
 147         unsigned long           phys;
 148         int                     word_len;
 149         u16                     mode;
 150         struct list_head        node;
 151         /* Context save and restore shadow register */
 152         u32                     chconf0;
 153 };
 154
 155 static inline void mcspi_write_reg(struct spi_master *master,
 156                 int idx, u32 val)
 157 {
 158         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 159
 160         writel_relaxed(val, mcspi->base + idx);
 161 }
 162
 163 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 164 {
 165         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 166
 167         return readl_relaxed(mcspi->base + idx);
 168 }
 169
 170 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 171                 int idx, u32 val)
 172 {
 173         struct omap2_mcspi_cs   *cs = spi->controller_state;
 174
 175         writel_relaxed(val, cs->base +  idx);
 176 }
 177
 178 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 179 {
 180         struct omap2_mcspi_cs   *cs = spi->controller_state;
 181
 182         return readl_relaxed(cs->base + idx);
 183 }
 184
 185 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
 186 {
 187         struct omap2_mcspi_cs *cs = spi->controller_state;
 188
 189         return cs->chconf0;
 190 }
 191
 192 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
 193 {
 194         struct omap2_mcspi_cs *cs = spi->controller_state;
 195
 196         cs->chconf0 = val;
 197         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
 198         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 199 }
 200
 201 static inline int mcspi_bytes_per_word(int word_len)
 202 {
 203         if (word_len <= 8)
 204                 return 1;
 205         else if (word_len <= 16)
 206                 return 2;
 207         else /* word_len <= 32 */
 208                 return 4;
 209 }
 210
 211 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 212                 int is_read, int enable)
 213 {
 214         u32 l, rw;
 215
 216         l = mcspi_cached_chconf0(spi);
 217
 218         if (is_read) /* 1 is read, 0 write */
 219                 rw = OMAP2_MCSPI_CHCONF_DMAR;
 220         else
 221                 rw = OMAP2_MCSPI_CHCONF_DMAW;
 222
 223         if (enable)
 224                 l |= rw;
 225         else
 226                 l &= ~rw;
 227
 228         mcspi_write_chconf0(spi, l);
 229 }
 230
 231 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 232 {
 233         u32 l;
 234
 235         l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
 236         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
 237         /* Flash post-writes */
 238         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
 239 }
 240
 241 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
 242 {
 243         u32 l;
 244
 245         l = mcspi_cached_chconf0(spi);
 246         if (cs_active)
 247                 l |= OMAP2_MCSPI_CHCONF_FORCE;
 248         else
 249                 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
 250
 251         mcspi_write_chconf0(spi, l);
 252 }
 253
 254 static void omap2_mcspi_set_master_mode(struct spi_master *master)
 255 {
 256         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
 257         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 258         u32 l;
 259
 260         /*
 261          * Setup when switching from (reset default) slave mode
 262          * to single-channel master mode
 263          */
 264         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
 265         l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
 266         l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
 267         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
 268
 269         ctx->modulctrl = l;
 270 }
 271
 272 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
 273                                 struct spi_transfer *t, int enable)
 274 {
 275         struct spi_master *master = spi->master;
 276         struct omap2_mcspi_cs *cs = spi->controller_state;
 277         struct omap2_mcspi *mcspi;
 278         unsigned int wcnt;
 279         int max_fifo_depth, fifo_depth, bytes_per_word;
 280         u32 chconf, xferlevel;
 281
 282         mcspi = spi_master_get_devdata(master);
 283
 284         chconf = mcspi_cached_chconf0(spi);
 285         if (enable) {
 286                 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
 287                 if (t->len % bytes_per_word != 0)
 288                         goto disable_fifo;
 289
 290                 if (t->rx_buf != NULL && t->tx_buf != NULL)
 291                         max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
 292                 else
 293                         max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
 294
 295                 fifo_depth = gcd(t->len, max_fifo_depth);
 296                 if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0)
 297                         goto disable_fifo;
 298
 299                 wcnt = t->len / bytes_per_word;
 300                 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
 301                         goto disable_fifo;
 302
 303                 xferlevel = wcnt << 16;
 304                 if (t->rx_buf != NULL) {
 305                         chconf |= OMAP2_MCSPI_CHCONF_FFER;
 306                         xferlevel |= (fifo_depth - 1) << 8;
 307                 }
 308                 if (t->tx_buf != NULL) {
 309                         chconf |= OMAP2_MCSPI_CHCONF_FFET;
 310                         xferlevel |= fifo_depth - 1;
 311                 }
 312
 313                 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
 314                 mcspi_write_chconf0(spi, chconf);
 315                 mcspi->fifo_depth = fifo_depth;
 316
 317                 return;
 318         }
 319
 320 disable_fifo:
 321         if (t->rx_buf != NULL)
 322                 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
 323
 324         if (t->tx_buf != NULL)
 325                 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
 326
 327         mcspi_write_chconf0(spi, chconf);
 328         mcspi->fifo_depth = 0;
 329 }
 330
 331 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
 332 {
 333         struct spi_master       *spi_cntrl = mcspi->master;
 334         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 335         struct omap2_mcspi_cs   *cs;
 336
 337         /* McSPI: context restore */
 338         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
 339         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
 340
 341         list_for_each_entry(cs, &ctx->cs, node)
 342                 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
 343 }
 344
 345 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
 346 {
 347         unsigned long timeout;
 348
 349         timeout = jiffies + msecs_to_jiffies(1000);
 350         while (!(readl_relaxed(reg) & bit)) {
 351                 if (time_after(jiffies, timeout)) {
 352                         if (!(readl_relaxed(reg) & bit))
 353                                 return -ETIMEDOUT;
 354                         else
 355                                 return 0;
 356                 }
 357                 cpu_relax();
 358         }
 359         return 0;
 360 }
 361
 362 static void omap2_mcspi_rx_callback(void *data)
 363 {
 364         struct spi_device *spi = data;
 365         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 366         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 367
 368         /* We must disable the DMA RX request */
 369         omap2_mcspi_set_dma_req(spi, 1, 0);
 370
 371         complete(&mcspi_dma->dma_rx_completion);
 372 }
 373
 374 static void omap2_mcspi_tx_callback(void *data)
 375 {
 376         struct spi_device *spi = data;
 377         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 378         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 379
 380         /* We must disable the DMA TX request */
 381         omap2_mcspi_set_dma_req(spi, 0, 0);
 382
 383         complete(&mcspi_dma->dma_tx_completion);
 384 }
 385
 386 static void omap2_mcspi_tx_dma(struct spi_device *spi,
 387                                 struct spi_transfer *xfer,
 388                                 struct dma_slave_config cfg)
 389 {
 390         struct omap2_mcspi      *mcspi;
 391         struct omap2_mcspi_dma  *mcspi_dma;
 392         unsigned int            count;
 393
 394         mcspi = spi_master_get_devdata(spi->master);
 395         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 396         count = xfer->len;
 397
 398         if (mcspi_dma->dma_tx) {
 399                 struct dma_async_tx_descriptor *tx;
 400                 struct scatterlist sg;
 401
 402                 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
 403
 404                 sg_init_table(&sg, 1);
 405                 sg_dma_address(&sg) = xfer->tx_dma;
 406                 sg_dma_len(&sg) = xfer->len;
 407
 408                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
 409                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 410                 if (tx) {
 411                         tx->callback = omap2_mcspi_tx_callback;
 412                         tx->callback_param = spi;
 413                         dmaengine_submit(tx);
 414                 } else {
 415                         /* FIXME: fall back to PIO? */
 416                 }
 417         }
 418         dma_async_issue_pending(mcspi_dma->dma_tx);
 419         omap2_mcspi_set_dma_req(spi, 0, 1);
 420
 421 }
 422
 423 static unsigned
 424 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
 425                                 struct dma_slave_config cfg,
 426                                 unsigned es)
 427 {
 428         struct omap2_mcspi      *mcspi;
 429         struct omap2_mcspi_dma  *mcspi_dma;
 430         unsigned int            count, dma_count;
 431         u32                     l;
 432         int                     elements = 0;
 433         int                     word_len, element_count;
 434         struct omap2_mcspi_cs   *cs = spi->controller_state;
 435         mcspi = spi_master_get_devdata(spi->master);
 436         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 437         count = xfer->len;
 438         dma_count = xfer->len;
 439
 440         if (mcspi->fifo_depth == 0)
 441                 dma_count -= es;
 442
 443         word_len = cs->word_len;
 444         l = mcspi_cached_chconf0(spi);
 445
 446         if (word_len <= 8)
 447                 element_count = count;
 448         else if (word_len <= 16)
 449                 element_count = count >> 1;
 450         else /* word_len <= 32 */
 451                 element_count = count >> 2;
 452
 453         if (mcspi_dma->dma_rx) {
 454                 struct dma_async_tx_descriptor *tx;
 455                 struct scatterlist sg;
 456
 457                 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
 458
 459                 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
 460                         dma_count -= es;
 461
 462                 sg_init_table(&sg, 1);
 463                 sg_dma_address(&sg) = xfer->rx_dma;
 464                 sg_dma_len(&sg) = dma_count;
 465
 466                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
 467                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
 468                                 DMA_CTRL_ACK);
 469                 if (tx) {
 470                         tx->callback = omap2_mcspi_rx_callback;
 471                         tx->callback_param = spi;
 472                         dmaengine_submit(tx);
 473                 } else {
 474                                 /* FIXME: fall back to PIO? */
 475                 }
 476         }
 477
 478         dma_async_issue_pending(mcspi_dma->dma_rx);
 479         omap2_mcspi_set_dma_req(spi, 1, 1);
 480
 481         wait_for_completion(&mcspi_dma->dma_rx_completion);
 482         dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
 483                          DMA_FROM_DEVICE);
 484
 485         if (mcspi->fifo_depth > 0)
 486                 return count;
 487
 488         omap2_mcspi_set_enable(spi, 0);
 489
 490         elements = element_count - 1;
 491
 492         if (l & OMAP2_MCSPI_CHCONF_TURBO) {
 493                 elements--;
 494
 495                 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 496                                    & OMAP2_MCSPI_CHSTAT_RXS)) {
 497                         u32 w;
 498
 499                         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 500                         if (word_len <= 8)
 501                                 ((u8 *)xfer->rx_buf)[elements++] = w;
 502                         else if (word_len <= 16)
 503                                 ((u16 *)xfer->rx_buf)[elements++] = w;
 504                         else /* word_len <= 32 */
 505                                 ((u32 *)xfer->rx_buf)[elements++] = w;
 506                 } else {
 507                         int bytes_per_word = mcspi_bytes_per_word(word_len);
 508                         dev_err(&spi->dev, "DMA RX penultimate word empty\n");
 509                         count -= (bytes_per_word << 1);
 510                         omap2_mcspi_set_enable(spi, 1);
 511                         return count;
 512                 }
 513         }
 514         if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 515                                 & OMAP2_MCSPI_CHSTAT_RXS)) {
 516                 u32 w;
 517
 518                 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 519                 if (word_len <= 8)
 520                         ((u8 *)xfer->rx_buf)[elements] = w;
 521                 else if (word_len <= 16)
 522                         ((u16 *)xfer->rx_buf)[elements] = w;
 523                 else /* word_len <= 32 */
 524                         ((u32 *)xfer->rx_buf)[elements] = w;
 525         } else {
 526                 dev_err(&spi->dev, "DMA RX last word empty\n");
 527                 count -= mcspi_bytes_per_word(word_len);
 528         }
 529         omap2_mcspi_set_enable(spi, 1);
 530         return count;
 531 }
 532
 533 static unsigned
 534 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 535 {
 536         struct omap2_mcspi      *mcspi;
 537         struct omap2_mcspi_cs   *cs = spi->controller_state;
 538         struct omap2_mcspi_dma  *mcspi_dma;
 539         unsigned int            count;
 540         u32                     l;
 541         u8                      *rx;
 542         const u8                *tx;
 543         struct dma_slave_config cfg;
 544         enum dma_slave_buswidth width;
 545         unsigned es;
 546         u32                     burst;
 547         void __iomem            *chstat_reg;
 548         void __iomem            *irqstat_reg;
 549         int                     wait_res;
 550
 551         mcspi = spi_master_get_devdata(spi->master);
 552         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 553         l = mcspi_cached_chconf0(spi);
 554
 555
 556         if (cs->word_len <= 8) {
 557                 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 558                 es = 1;
 559         } else if (cs->word_len <= 16) {
 560                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 561                 es = 2;
 562         } else {
 563                 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 564                 es = 4;
 565         }
 566
 567         count = xfer->len;
 568         burst = 1;
 569
 570         if (mcspi->fifo_depth > 0) {
 571                 if (count > mcspi->fifo_depth)
 572                         burst = mcspi->fifo_depth / es;
 573                 else
 574                         burst = count / es;
 575         }
 576
 577         memset(&cfg, 0, sizeof(cfg));
 578         cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
 579         cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
 580         cfg.src_addr_width = width;
 581         cfg.dst_addr_width = width;
 582         cfg.src_maxburst = burst;
 583         cfg.dst_maxburst = burst;
 584
 585         rx = xfer->rx_buf;
 586         tx = xfer->tx_buf;
 587
 588         if (tx != NULL)
 589                 omap2_mcspi_tx_dma(spi, xfer, cfg);
 590
 591         if (rx != NULL)
 592                 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
 593
 594         if (tx != NULL) {
 595                 wait_for_completion(&mcspi_dma->dma_tx_completion);
 596                 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
 597                                  DMA_TO_DEVICE);
 598
 599                 if (mcspi->fifo_depth > 0) {
 600                         irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
 601
 602                         if (mcspi_wait_for_reg_bit(irqstat_reg,
 603                                                 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
 604                                 dev_err(&spi->dev, "EOW timed out\n");
 605
 606                         mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
 607                                         OMAP2_MCSPI_IRQSTATUS_EOW);
 608                 }
 609
 610                 /* for TX_ONLY mode, be sure all words have shifted out */
 611                 if (rx == NULL) {
 612                         chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
 613                         if (mcspi->fifo_depth > 0) {
 614                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
 615                                                 OMAP2_MCSPI_CHSTAT_TXFFE);
 616                                 if (wait_res < 0)
 617                                         dev_err(&spi->dev, "TXFFE timed out\n");
 618                         } else {
 619                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
 620                                                 OMAP2_MCSPI_CHSTAT_TXS);
 621                                 if (wait_res < 0)
 622                                         dev_err(&spi->dev, "TXS timed out\n");
 623                         }
 624                         if (wait_res >= 0 &&
 625                                 (mcspi_wait_for_reg_bit(chstat_reg,
 626                                         OMAP2_MCSPI_CHSTAT_EOT) < 0))
 627                                 dev_err(&spi->dev, "EOT timed out\n");
 628                 }
 629         }
 630         return count;
 631 }
 632
 633 static unsigned
 634 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 635 {
 636         struct omap2_mcspi      *mcspi;
 637         struct omap2_mcspi_cs   *cs = spi->controller_state;
 638         unsigned int            count, c;
 639         u32                     l;
 640         void __iomem            *base = cs->base;
 641         void __iomem            *tx_reg;
 642         void __iomem            *rx_reg;
 643         void __iomem            *chstat_reg;
 644         int                     word_len;
 645
 646         mcspi = spi_master_get_devdata(spi->master);
 647         count = xfer->len;
 648         c = count;
 649         word_len = cs->word_len;
 650
 651         l = mcspi_cached_chconf0(spi);
 652
 653         /* We store the pre-calculated register addresses on stack to speed
 654          * up the transfer loop. */
 655         tx_reg          = base + OMAP2_MCSPI_TX0;
 656         rx_reg          = base + OMAP2_MCSPI_RX0;
 657         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
 658
 659         if (c < (word_len>>3))
 660                 return 0;
 661
 662         if (word_len <= 8) {
 663                 u8              *rx;
 664                 const u8        *tx;
 665
 666                 rx = xfer->rx_buf;
 667                 tx = xfer->tx_buf;
 668
 669                 do {
 670                         c -= 1;
 671                         if (tx != NULL) {
 672                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 673                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 674                                         dev_err(&spi->dev, "TXS timed out\n");
 675                                         goto out;
 676                                 }
 677                                 dev_vdbg(&spi->dev, "write-%d %02x\n",
 678                                                 word_len, *tx);
 679                                 writel_relaxed(*tx++, tx_reg);
 680                         }
 681                         if (rx != NULL) {
 682                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 683                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 684                                         dev_err(&spi->dev, "RXS timed out\n");
 685                                         goto out;
 686                                 }
 687
 688                                 if (c == 1 && tx == NULL &&
 689                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 690                                         omap2_mcspi_set_enable(spi, 0);
 691                                         *rx++ = readl_relaxed(rx_reg);
 692                                         dev_vdbg(&spi->dev, "read-%d %02x\n",
 693                                                     word_len, *(rx - 1));
 694                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 695                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 696                                                 dev_err(&spi->dev,
 697                                                         "RXS timed out\n");
 698                                                 goto out;
 699                                         }
 700                                         c = 0;
 701                                 } else if (c == 0 && tx == NULL) {
 702                                         omap2_mcspi_set_enable(spi, 0);
 703                                 }
 704
 705                                 *rx++ = readl_relaxed(rx_reg);
 706                                 dev_vdbg(&spi->dev, "read-%d %02x\n",
 707                                                 word_len, *(rx - 1));
 708                         }
 709                 } while (c);
 710         } else if (word_len <= 16) {
 711                 u16             *rx;
 712                 const u16       *tx;
 713
 714                 rx = xfer->rx_buf;
 715                 tx = xfer->tx_buf;
 716                 do {
 717                         c -= 2;
 718                         if (tx != NULL) {
 719                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 720                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 721                                         dev_err(&spi->dev, "TXS timed out\n");
 722                                         goto out;
 723                                 }
 724                                 dev_vdbg(&spi->dev, "write-%d %04x\n",
 725                                                 word_len, *tx);
 726                                 writel_relaxed(*tx++, tx_reg);
 727                         }
 728                         if (rx != NULL) {
 729                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 730                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 731                                         dev_err(&spi->dev, "RXS timed out\n");
 732                                         goto out;
 733                                 }
 734
 735                                 if (c == 2 && tx == NULL &&
 736                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 737                                         omap2_mcspi_set_enable(spi, 0);
 738                                         *rx++ = readl_relaxed(rx_reg);
 739                                         dev_vdbg(&spi->dev, "read-%d %04x\n",
 740                                                     word_len, *(rx - 1));
 741                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 742                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 743                                                 dev_err(&spi->dev,
 744                                                         "RXS timed out\n");
 745                                                 goto out;
 746                                         }
 747                                         c = 0;
 748                                 } else if (c == 0 && tx == NULL) {
 749                                         omap2_mcspi_set_enable(spi, 0);
 750                                 }
 751
 752                                 *rx++ = readl_relaxed(rx_reg);
 753                                 dev_vdbg(&spi->dev, "read-%d %04x\n",
 754                                                 word_len, *(rx - 1));
 755                         }
 756                 } while (c >= 2);
 757         } else if (word_len <= 32) {
 758                 u32             *rx;
 759                 const u32       *tx;
 760
 761                 rx = xfer->rx_buf;
 762                 tx = xfer->tx_buf;
 763                 do {
 764                         c -= 4;
 765                         if (tx != NULL) {
 766                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 767                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 768                                         dev_err(&spi->dev, "TXS timed out\n");
 769                                         goto out;
 770                                 }
 771                                 dev_vdbg(&spi->dev, "write-%d %08x\n",
 772                                                 word_len, *tx);
 773                                 writel_relaxed(*tx++, tx_reg);
 774                         }
 775                         if (rx != NULL) {
 776                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 777                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 778                                         dev_err(&spi->dev, "RXS timed out\n");
 779                                         goto out;
 780                                 }
 781
 782                                 if (c == 4 && tx == NULL &&
 783                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 784                                         omap2_mcspi_set_enable(spi, 0);
 785                                         *rx++ = readl_relaxed(rx_reg);
 786                                         dev_vdbg(&spi->dev, "read-%d %08x\n",
 787                                                     word_len, *(rx - 1));
 788                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 789                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 790                                                 dev_err(&spi->dev,
 791                                                         "RXS timed out\n");
 792                                                 goto out;
 793                                         }
 794                                         c = 0;
 795                                 } else if (c == 0 && tx == NULL) {
 796                                         omap2_mcspi_set_enable(spi, 0);
 797                                 }
 798
 799                                 *rx++ = readl_relaxed(rx_reg);
 800                                 dev_vdbg(&spi->dev, "read-%d %08x\n",
 801                                                 word_len, *(rx - 1));
 802                         }
 803                 } while (c >= 4);
 804         }
 805
 806         /* for TX_ONLY mode, be sure all words have shifted out */
 807         if (xfer->rx_buf == NULL) {
 808                 if (mcspi_wait_for_reg_bit(chstat_reg,
 809                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 810                         dev_err(&spi->dev, "TXS timed out\n");
 811                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
 812                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 813                         dev_err(&spi->dev, "EOT timed out\n");
 814
 815                 /* disable chan to purge rx datas received in TX_ONLY transfer,
 816                  * otherwise these rx datas will affect the direct following
 817                  * RX_ONLY transfer.
 818                  */
 819                 omap2_mcspi_set_enable(spi, 0);
 820         }
 821 out:
 822         omap2_mcspi_set_enable(spi, 1);
 823         return count - c;
 824 }
 825
 826 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
 827 {
 828         u32 div;
 829
 830         for (div = 0; div < 15; div++)
 831                 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
 832                         return div;
 833
 834         return 15;
 835 }
 836
 837 /* called only when no transfer is active to this device */
 838 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 839                 struct spi_transfer *t)
 840 {
 841         struct omap2_mcspi_cs *cs = spi->controller_state;
 842         struct omap2_mcspi *mcspi;
 843         struct spi_master *spi_cntrl;
 844         u32 l = 0, div = 0;
 845         u8 word_len = spi->bits_per_word;
 846         u32 speed_hz = spi->max_speed_hz;
 847
 848         mcspi = spi_master_get_devdata(spi->master);
 849         spi_cntrl = mcspi->master;
 850
 851         if (t != NULL && t->bits_per_word)
 852                 word_len = t->bits_per_word;
 853
 854         cs->word_len = word_len;
 855
 856         if (t && t->speed_hz)
 857                 speed_hz = t->speed_hz;
 858
 859         speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
 860         div = omap2_mcspi_calc_divisor(speed_hz);
 861
 862         l = mcspi_cached_chconf0(spi);
 863
 864         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
 865          * REVISIT: this controller could support SPI_3WIRE mode.
 866          */
 867         if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
 868                 l &= ~OMAP2_MCSPI_CHCONF_IS;
 869                 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
 870                 l |= OMAP2_MCSPI_CHCONF_DPE0;
 871         } else {
 872                 l |= OMAP2_MCSPI_CHCONF_IS;
 873                 l |= OMAP2_MCSPI_CHCONF_DPE1;
 874                 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
 875         }
 876
 877         /* wordlength */
 878         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 879         l |= (word_len - 1) << 7;
 880
 881         /* set chipselect polarity; manage with FORCE */
 882         if (!(spi->mode & SPI_CS_HIGH))
 883                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
 884         else
 885                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 886
 887         /* set clock divisor */
 888         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 889         l |= div << 2;
 890
 891         /* set SPI mode 0..3 */
 892         if (spi->mode & SPI_CPOL)
 893                 l |= OMAP2_MCSPI_CHCONF_POL;
 894         else
 895                 l &= ~OMAP2_MCSPI_CHCONF_POL;
 896         if (spi->mode & SPI_CPHA)
 897                 l |= OMAP2_MCSPI_CHCONF_PHA;
 898         else
 899                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
 900
 901         mcspi_write_chconf0(spi, l);
 902
 903         cs->mode = spi->mode;
 904
 905         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
 906                         OMAP2_MCSPI_MAX_FREQ >> div,
 907                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
 908                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
 909
 910         return 0;
 911 }
 912
 913 /*
 914  * Note that we currently allow DMA only if we get a channel
 915  * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
 916  */
 917 static int omap2_mcspi_request_dma(struct spi_device *spi)
 918 {
 919         struct spi_master       *master = spi->master;
 920         struct omap2_mcspi      *mcspi;
 921         struct omap2_mcspi_dma  *mcspi_dma;
 922         dma_cap_mask_t mask;
 923         unsigned sig;
 924
 925         mcspi = spi_master_get_devdata(master);
 926         mcspi_dma = mcspi->dma_channels + spi->chip_select;
 927
 928         init_completion(&mcspi_dma->dma_rx_completion);
 929         init_completion(&mcspi_dma->dma_tx_completion);
 930
 931         dma_cap_zero(mask);
 932         dma_cap_set(DMA_SLAVE, mask);
 933         sig = mcspi_dma->dma_rx_sync_dev;
 934
 935         mcspi_dma->dma_rx =
 936                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
 937                                                  &sig, &master->dev,
 938                                                  mcspi_dma->dma_rx_ch_name);
 939         if (!mcspi_dma->dma_rx)
 940                 goto no_dma;
 941
 942         sig = mcspi_dma->dma_tx_sync_dev;
 943         mcspi_dma->dma_tx =
 944                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
 945                                                  &sig, &master->dev,
 946                                                  mcspi_dma->dma_tx_ch_name);
 947
 948         if (!mcspi_dma->dma_tx) {
 949                 dma_release_channel(mcspi_dma->dma_rx);
 950                 mcspi_dma->dma_rx = NULL;
 951                 goto no_dma;
 952         }
 953
 954         return 0;
 955
 956 no_dma:
 957         dev_warn(&spi->dev, "not using DMA for McSPI\n");
 958         return -EAGAIN;
 959 }
 960
 961 static int omap2_mcspi_setup(struct spi_device *spi)
 962 {
 963         int                     ret;
 964         struct omap2_mcspi      *mcspi = spi_master_get_devdata(spi->master);
 965         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 966         struct omap2_mcspi_dma  *mcspi_dma;
 967         struct omap2_mcspi_cs   *cs = spi->controller_state;
 968
 969         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 970
 971         if (!cs) {
 972                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 973                 if (!cs)
 974                         return -ENOMEM;
 975                 cs->base = mcspi->base + spi->chip_select * 0x14;
 976                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
 977                 cs->mode = 0;
 978                 cs->chconf0 = 0;
 979                 spi->controller_state = cs;
 980                 /* Link this to context save list */
 981                 list_add_tail(&cs->node, &ctx->cs);
 982         }
 983
 984         if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
 985                 ret = omap2_mcspi_request_dma(spi);
 986                 if (ret < 0 && ret != -EAGAIN)
 987                         return ret;
 988         }
 989
 990         ret = pm_runtime_get_sync(mcspi->dev);
 991         if (ret < 0)
 992                 return ret;
 993
 994         ret = omap2_mcspi_setup_transfer(spi, NULL);
 995         pm_runtime_mark_last_busy(mcspi->dev);
 996         pm_runtime_put_autosuspend(mcspi->dev);
 997
 998         return ret;
 999 }
1000
1001 static void omap2_mcspi_cleanup(struct spi_device *spi)
1002 {
1003         struct omap2_mcspi      *mcspi;
1004         struct omap2_mcspi_dma  *mcspi_dma;
1005         struct omap2_mcspi_cs   *cs;
1006
1007         mcspi = spi_master_get_devdata(spi->master);
1008
1009         if (spi->controller_state) {
1010                 /* Unlink controller state from context save list */
1011                 cs = spi->controller_state;
1012                 list_del(&cs->node);
1013
1014                 kfree(cs);
1015         }
1016
1017         if (spi->chip_select < spi->master->num_chipselect) {
1018                 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1019
1020                 if (mcspi_dma->dma_rx) {
1021                         dma_release_channel(mcspi_dma->dma_rx);
1022                         mcspi_dma->dma_rx = NULL;
1023                 }
1024                 if (mcspi_dma->dma_tx) {
1025                         dma_release_channel(mcspi_dma->dma_tx);
1026                         mcspi_dma->dma_tx = NULL;
1027                 }
1028         }
1029 }
1030
1031 static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
1032 {
1033
1034         /* We only enable one channel at a time -- the one whose message is
1035          * -- although this controller would gladly
1036          * arbitrate among multiple channels.  This corresponds to "single
1037          * channel" master mode.  As a side effect, we need to manage the
1038          * chipselect with the FORCE bit ... CS != channel enable.
1039          */
1040
1041         struct spi_device               *spi;
1042         struct spi_transfer             *t = NULL;
1043         struct spi_master               *master;
1044         struct omap2_mcspi_dma          *mcspi_dma;
1045         int                             cs_active = 0;
1046         struct omap2_mcspi_cs           *cs;
1047         struct omap2_mcspi_device_config *cd;
1048         int                             par_override = 0;
1049         int                             status = 0;
1050         u32                             chconf;
1051
1052         spi = m->spi;
1053         master = spi->master;
1054         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1055         cs = spi->controller_state;
1056         cd = spi->controller_data;
1057
1058         /*
1059          * The slave driver could have changed spi->mode in which case
1060          * it will be different from cs->mode (the current hardware setup).
1061          * If so, set par_override (even though its not a parity issue) so
1062          * omap2_mcspi_setup_transfer will be called to configure the hardware
1063          * with the correct mode on the first iteration of the loop below.
1064          */
1065         if (spi->mode != cs->mode)
1066                 par_override = 1;
1067
1068         omap2_mcspi_set_enable(spi, 0);
1069         list_for_each_entry(t, &m->transfers, transfer_list) {
1070                 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
1071                         status = -EINVAL;
1072                         break;
1073                 }
1074                 if (par_override || t->speed_hz || t->bits_per_word) {
1075                         par_override = 1;
1076                         status = omap2_mcspi_setup_transfer(spi, t);
1077                         if (status < 0)
1078                                 break;
1079                         if (!t->speed_hz && !t->bits_per_word)
1080                                 par_override = 0;
1081                 }
1082                 if (cd && cd->cs_per_word) {
1083                         chconf = mcspi->ctx.modulctrl;
1084                         chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1085                         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1086                         mcspi->ctx.modulctrl =
1087                                 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1088                 }
1089
1090
1091                 if (!cs_active) {
1092                         omap2_mcspi_force_cs(spi, 1);
1093                         cs_active = 1;
1094                 }
1095
1096                 chconf = mcspi_cached_chconf0(spi);
1097                 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1098                 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1099
1100                 if (t->tx_buf == NULL)
1101                         chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1102                 else if (t->rx_buf == NULL)
1103                         chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1104
1105                 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1106                         /* Turbo mode is for more than one word */
1107                         if (t->len > ((cs->word_len + 7) >> 3))
1108                                 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1109                 }
1110
1111                 mcspi_write_chconf0(spi, chconf);
1112
1113                 if (t->len) {
1114                         unsigned        count;
1115
1116                         if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1117                             (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
1118                                 omap2_mcspi_set_fifo(spi, t, 1);
1119
1120                         omap2_mcspi_set_enable(spi, 1);
1121
1122                         /* RX_ONLY mode needs dummy data in TX reg */
1123                         if (t->tx_buf == NULL)
1124                                 writel_relaxed(0, cs->base
1125                                                 + OMAP2_MCSPI_TX0);
1126
1127                         if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1128                             (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
1129                                 count = omap2_mcspi_txrx_dma(spi, t);
1130                         else
1131                                 count = omap2_mcspi_txrx_pio(spi, t);
1132                         m->actual_length += count;
1133
1134                         if (count != t->len) {
1135                                 status = -EIO;
1136                                 break;
1137                         }
1138                 }
1139
1140                 if (t->delay_usecs)
1141                         udelay(t->delay_usecs);
1142
1143                 /* ignore the "leave it on after last xfer" hint */
1144                 if (t->cs_change) {
1145                         omap2_mcspi_force_cs(spi, 0);
1146                         cs_active = 0;
1147                 }
1148
1149                 omap2_mcspi_set_enable(spi, 0);
1150
1151                 if (mcspi->fifo_depth > 0)
1152                         omap2_mcspi_set_fifo(spi, t, 0);
1153         }
1154         /* Restore defaults if they were overriden */
1155         if (par_override) {
1156                 par_override = 0;
1157                 status = omap2_mcspi_setup_transfer(spi, NULL);
1158         }
1159
1160         if (cs_active)
1161                 omap2_mcspi_force_cs(spi, 0);
1162
1163         if (cd && cd->cs_per_word) {
1164                 chconf = mcspi->ctx.modulctrl;
1165                 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1166                 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1167                 mcspi->ctx.modulctrl =
1168                         mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1169         }
1170
1171         omap2_mcspi_set_enable(spi, 0);
1172
1173         if (mcspi->fifo_depth > 0 && t)
1174                 omap2_mcspi_set_fifo(spi, t, 0);
1175
1176         m->status = status;
1177 }
1178
1179 static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1180                 struct spi_message *m)
1181 {
1182         struct spi_device       *spi;
1183         struct omap2_mcspi      *mcspi;
1184         struct omap2_mcspi_dma  *mcspi_dma;
1185         struct spi_transfer     *t;
1186
1187         spi = m->spi;
1188         mcspi = spi_master_get_devdata(master);
1189         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1190         m->actual_length = 0;
1191         m->status = 0;
1192
1193         /* reject invalid messages and transfers */
1194         if (list_empty(&m->transfers))
1195                 return -EINVAL;
1196         list_for_each_entry(t, &m->transfers, transfer_list) {
1197                 const void      *tx_buf = t->tx_buf;
1198                 void            *rx_buf = t->rx_buf;
1199                 unsigned        len = t->len;
1200
1201                 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1202                                 || (len && !(rx_buf || tx_buf))) {
1203                         dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1204                                         t->speed_hz,
1205                                         len,
1206                                         tx_buf ? "tx" : "",
1207                                         rx_buf ? "rx" : "",
1208                                         t->bits_per_word);
1209                         return -EINVAL;
1210                 }
1211                 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
1212                         dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
1213                                         t->speed_hz,
1214                                         OMAP2_MCSPI_MAX_FREQ >> 15);
1215                         return -EINVAL;
1216                 }
1217
1218                 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1219                         continue;
1220
1221                 if (mcspi_dma->dma_tx && tx_buf != NULL) {
1222                         t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1223                                         len, DMA_TO_DEVICE);
1224                         if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1225                                 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1226                                                 'T', len);
1227                                 return -EINVAL;
1228                         }
1229                 }
1230                 if (mcspi_dma->dma_rx && rx_buf != NULL) {
1231                         t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1232                                         DMA_FROM_DEVICE);
1233                         if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1234                                 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1235                                                 'R', len);
1236                                 if (tx_buf != NULL)
1237                                         dma_unmap_single(mcspi->dev, t->tx_dma,
1238                                                         len, DMA_TO_DEVICE);
1239                                 return -EINVAL;
1240                         }
1241                 }
1242         }
1243
1244         omap2_mcspi_work(mcspi, m);
1245         spi_finalize_current_message(master);
1246         return 0;
1247 }
1248
1249 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1250 {
1251         struct spi_master       *master = mcspi->master;
1252         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1253         int                     ret = 0;
1254
1255         ret = pm_runtime_get_sync(mcspi->dev);
1256         if (ret < 0)
1257                 return ret;
1258
1259         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1260                         OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1261         ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1262
1263         omap2_mcspi_set_master_mode(master);
1264         pm_runtime_mark_last_busy(mcspi->dev);
1265         pm_runtime_put_autosuspend(mcspi->dev);
1266         return 0;
1267 }
1268
1269 static int omap_mcspi_runtime_resume(struct device *dev)
1270 {
1271         struct omap2_mcspi      *mcspi;
1272         struct spi_master       *master;
1273
1274         master = dev_get_drvdata(dev);
1275         mcspi = spi_master_get_devdata(master);
1276         omap2_mcspi_restore_ctx(mcspi);
1277
1278         return 0;
1279 }
1280
1281 static struct omap2_mcspi_platform_config omap2_pdata = {
1282         .regs_offset = 0,
1283 };
1284
1285 static struct omap2_mcspi_platform_config omap4_pdata = {
1286         .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1287 };
1288
1289 static const struct of_device_id omap_mcspi_of_match[] = {
1290         {
1291                 .compatible = "ti,omap2-mcspi",
1292                 .data = &omap2_pdata,
1293         },
1294         {
1295                 .compatible = "ti,omap4-mcspi",
1296                 .data = &omap4_pdata,
1297         },
1298         { },
1299 };
1300 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1301
1302 static int omap2_mcspi_probe(struct platform_device *pdev)
1303 {
1304         struct spi_master       *master;
1305         const struct omap2_mcspi_platform_config *pdata;
1306         struct omap2_mcspi      *mcspi;
1307         struct resource         *r;
1308         int                     status = 0, i;
1309         u32                     regs_offset = 0;
1310         static int              bus_num = 1;
1311         struct device_node      *node = pdev->dev.of_node;
1312         const struct of_device_id *match;
1313
1314         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1315         if (master == NULL) {
1316                 dev_dbg(&pdev->dev, "master allocation failed\n");
1317                 return -ENOMEM;
1318         }
1319
1320         /* the spi->mode bits understood by this driver: */
1321         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1322         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1323         master->setup = omap2_mcspi_setup;
1324         master->auto_runtime_pm = true;
1325         master->transfer_one_message = omap2_mcspi_transfer_one_message;
1326         master->cleanup = omap2_mcspi_cleanup;
1327         master->dev.of_node = node;
1328
1329         platform_set_drvdata(pdev, master);
1330
1331         mcspi = spi_master_get_devdata(master);
1332         mcspi->master = master;
1333
1334         match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1335         if (match) {
1336                 u32 num_cs = 1; /* default number of chipselect */
1337                 pdata = match->data;
1338
1339                 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1340                 master->num_chipselect = num_cs;
1341                 master->bus_num = bus_num++;
1342                 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1343                         mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1344         } else {
1345                 pdata = dev_get_platdata(&pdev->dev);
1346                 master->num_chipselect = pdata->num_cs;
1347                 if (pdev->id != -1)
1348                         master->bus_num = pdev->id;
1349                 mcspi->pin_dir = pdata->pin_dir;
1350         }
1351         regs_offset = pdata->regs_offset;
1352
1353         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1354         if (r == NULL) {
1355                 status = -ENODEV;
1356                 goto free_master;
1357         }
1358
1359         r->start += regs_offset;
1360         r->end += regs_offset;
1361         mcspi->phys = r->start;
1362
1363         mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1364         if (IS_ERR(mcspi->base)) {
1365                 status = PTR_ERR(mcspi->base);
1366                 goto free_master;
1367         }
1368
1369         mcspi->dev = &pdev->dev;
1370
1371         INIT_LIST_HEAD(&mcspi->ctx.cs);
1372
1373         mcspi->dma_channels = kcalloc(master->num_chipselect,
1374                         sizeof(struct omap2_mcspi_dma),
1375                         GFP_KERNEL);
1376
1377         if (mcspi->dma_channels == NULL)
1378                 goto free_master;
1379
1380         for (i = 0; i < master->num_chipselect; i++) {
1381                 char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name;
1382                 char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name;
1383                 struct resource *dma_res;
1384
1385                 sprintf(dma_rx_ch_name, "rx%d", i);
1386                 if (!pdev->dev.of_node) {
1387                         dma_res =
1388                                 platform_get_resource_byname(pdev,
1389                                                              IORESOURCE_DMA,
1390                                                              dma_rx_ch_name);
1391                         if (!dma_res) {
1392                                 dev_dbg(&pdev->dev,
1393                                         "cannot get DMA RX channel\n");
1394                                 status = -ENODEV;
1395                                 break;
1396                         }
1397
1398                         mcspi->dma_channels[i].dma_rx_sync_dev =
1399                                 dma_res->start;
1400                 }
1401                 sprintf(dma_tx_ch_name, "tx%d", i);
1402                 if (!pdev->dev.of_node) {
1403                         dma_res =
1404                                 platform_get_resource_byname(pdev,
1405                                                              IORESOURCE_DMA,
1406                                                              dma_tx_ch_name);
1407                         if (!dma_res) {
1408                                 dev_dbg(&pdev->dev,
1409                                         "cannot get DMA TX channel\n");
1410                                 status = -ENODEV;
1411                                 break;
1412                         }
1413
1414                         mcspi->dma_channels[i].dma_tx_sync_dev =
1415                                 dma_res->start;
1416                 }
1417         }
1418
1419         if (status < 0)
1420                 goto dma_chnl_free;
1421
1422         pm_runtime_use_autosuspend(&pdev->dev);
1423         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1424         pm_runtime_enable(&pdev->dev);
1425
1426         status = omap2_mcspi_master_setup(mcspi);
1427         if (status < 0)
1428                 goto disable_pm;
1429
1430         status = devm_spi_register_master(&pdev->dev, master);
1431         if (status < 0)
1432                 goto disable_pm;
1433
1434         return status;
1435
1436 disable_pm:
1437         pm_runtime_disable(&pdev->dev);
1438 dma_chnl_free:
1439         kfree(mcspi->dma_channels);
1440 free_master:
1441         spi_master_put(master);
1442         return status;
1443 }
1444
1445 static int omap2_mcspi_remove(struct platform_device *pdev)
1446 {
1447         struct spi_master       *master;
1448         struct omap2_mcspi      *mcspi;
1449         struct omap2_mcspi_dma  *dma_channels;
1450
1451         master = platform_get_drvdata(pdev);
1452         mcspi = spi_master_get_devdata(master);
1453         dma_channels = mcspi->dma_channels;
1454
1455         pm_runtime_put_sync(mcspi->dev);
1456         pm_runtime_disable(&pdev->dev);
1457
1458         kfree(dma_channels);
1459
1460         return 0;
1461 }
1462
1463 /* work with hotplug and coldplug */
1464 MODULE_ALIAS("platform:omap2_mcspi");
1465
1466 #ifdef  CONFIG_SUSPEND
1467 /*
1468  * When SPI wake up from off-mode, CS is in activate state. If it was in
1469  * unactive state when driver was suspend, then force it to unactive state at
1470  * wake up.
1471  */
1472 static int omap2_mcspi_resume(struct device *dev)
1473 {
1474         struct spi_master       *master = dev_get_drvdata(dev);
1475         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1476         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1477         struct omap2_mcspi_cs   *cs;
1478
1479         pm_runtime_get_sync(mcspi->dev);
1480         list_for_each_entry(cs, &ctx->cs, node) {
1481                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1482                         /*
1483                          * We need to toggle CS state for OMAP take this
1484                          * change in account.
1485                          */
1486                         cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1487                         writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1488                         cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1489                         writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1490                 }
1491         }
1492         pm_runtime_mark_last_busy(mcspi->dev);
1493         pm_runtime_put_autosuspend(mcspi->dev);
1494         return 0;
1495 }
1496 #else
1497 #define omap2_mcspi_resume      NULL
1498 #endif
1499
1500 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1501         .resume = omap2_mcspi_resume,
1502         .runtime_resume = omap_mcspi_runtime_resume,
1503 };
1504
1505 static struct platform_driver omap2_mcspi_driver = {
1506         .driver = {
1507                 .name =         "omap2_mcspi",
1508                 .owner =        THIS_MODULE,
1509                 .pm =           &omap2_mcspi_pm_ops,
1510                 .of_match_table = omap_mcspi_of_match,
1511         },
1512         .probe =        omap2_mcspi_probe,
1513         .remove =       omap2_mcspi_remove,
1514 };
1515
1516 module_platform_driver(omap2_mcspi_driver);
1517 MODULE_LICENSE("GPL");