2 * MicroWire interface driver for OMAP
4 * Copyright 2003 MontaVista Software Inc. <source@mvista.com>
6 * Ported to 2.6 OMAP uwire interface.
7 * Copyright (C) 2004 Texas Instruments.
9 * Generalization patches by Juha Yrjola <juha.yrjola@nokia.com>
11 * Copyright (C) 2005 David Brownell (ported to 2.6 SPI interface)
12 * Copyright (C) 2006 Nokia
14 * Many updates by Imre Deak <imre.deak@nokia.com>
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 #include <linux/kernel.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/platform_device.h>
40 #include <linux/workqueue.h>
41 #include <linux/interrupt.h>
42 #include <linux/err.h>
43 #include <linux/clk.h>
44 #include <linux/slab.h>
46 #include <linux/spi/spi.h>
47 #include <linux/spi/spi_bitbang.h>
48 #include <linux/module.h>
51 #include <mach/hardware.h>
53 #include <asm/mach-types.h>
57 #include <mach/omap7xx.h> /* OMAP7XX_IO_CONF registers */
60 /* FIXME address is now a platform device resource,
61 * and irqs should show there too...
63 #define UWIRE_BASE_PHYS 0xFFFB3000
65 /* uWire Registers: */
66 #define UWIRE_IO_SIZE 0x20
67 #define UWIRE_TDR 0x00
68 #define UWIRE_RDR 0x00
69 #define UWIRE_CSR 0x01
70 #define UWIRE_SR1 0x02
71 #define UWIRE_SR2 0x03
72 #define UWIRE_SR3 0x04
73 #define UWIRE_SR4 0x05
74 #define UWIRE_SR5 0x06
77 #define RDRB (1 << 15)
78 #define CSRB (1 << 14)
79 #define START (1 << 13)
80 #define CS_CMD (1 << 12)
83 #define UWIRE_READ_FALLING_EDGE 0x0001
84 #define UWIRE_READ_RISING_EDGE 0x0000
85 #define UWIRE_WRITE_FALLING_EDGE 0x0000
86 #define UWIRE_WRITE_RISING_EDGE 0x0002
87 #define UWIRE_CS_ACTIVE_LOW 0x0000
88 #define UWIRE_CS_ACTIVE_HIGH 0x0004
89 #define UWIRE_FREQ_DIV_2 0x0000
90 #define UWIRE_FREQ_DIV_4 0x0008
91 #define UWIRE_FREQ_DIV_8 0x0010
92 #define UWIRE_CHK_READY 0x0020
93 #define UWIRE_CLK_INVERTED 0x0040
97 struct spi_bitbang bitbang;
102 unsigned bits_per_word;
106 /* REVISIT compile time constant for idx_shift? */
108 * Or, put it in a structure which is used throughout the driver;
109 * that avoids having to issue two loads for each bit of static data.
111 static unsigned int uwire_idx_shift;
112 static void __iomem *uwire_base;
114 static inline void uwire_write_reg(int idx, u16 val)
116 __raw_writew(val, uwire_base + (idx << uwire_idx_shift));
119 static inline u16 uwire_read_reg(int idx)
121 return __raw_readw(uwire_base + (idx << uwire_idx_shift));
124 static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags)
129 if (flags & UWIRE_CLK_INVERTED)
141 w = uwire_read_reg(reg);
142 w &= ~(0x3f << shift);
144 uwire_write_reg(reg, w);
147 static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch)
151 unsigned long max_jiffies = jiffies + HZ;
154 w = uwire_read_reg(UWIRE_CSR);
155 if ((w & mask) == val)
157 if (time_after(jiffies, max_jiffies)) {
158 printk(KERN_ERR "%s: timeout. reg=%#06x "
159 "mask=%#06x val=%#06x\n",
160 __func__, w, mask, val);
164 if (might_not_catch && c > 64)
170 static void uwire_set_clk1_div(int div1_idx)
174 w = uwire_read_reg(UWIRE_SR3);
177 uwire_write_reg(UWIRE_SR3, w);
180 static void uwire_chipselect(struct spi_device *spi, int value)
182 struct uwire_state *ust = spi->controller_state;
187 BUG_ON(wait_uwire_csr_flag(CSRB, 0, 0));
189 w = uwire_read_reg(UWIRE_CSR);
190 old_cs = (w >> 10) & 0x03;
191 if (value == BITBANG_CS_INACTIVE || old_cs != spi->chip_select) {
192 /* Deselect this CS, or the previous CS */
194 uwire_write_reg(UWIRE_CSR, w);
196 /* activate specfied chipselect */
197 if (value == BITBANG_CS_ACTIVE) {
198 uwire_set_clk1_div(ust->div1_idx);
200 if (spi->mode & SPI_CPOL)
201 uwire_write_reg(UWIRE_SR4, 1);
203 uwire_write_reg(UWIRE_SR4, 0);
205 w = spi->chip_select << 10;
207 uwire_write_reg(UWIRE_CSR, w);
211 static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
213 struct uwire_state *ust = spi->controller_state;
214 unsigned len = t->len;
215 unsigned bits = ust->bits_per_word;
220 if (!t->tx_buf && !t->rx_buf)
223 /* Microwire doesn't read and write concurrently */
224 if (t->tx_buf && t->rx_buf)
227 w = spi->chip_select << 10;
231 const u8 *buf = t->tx_buf;
233 /* NOTE: DMA could be used for TX transfers */
235 /* write one or two bytes at a time */
237 /* tx bit 15 is first sent; we byteswap multibyte words
238 * (msb-first) on the way out from memory.
249 pr_debug("%s: write-%d =%04x\n",
250 dev_name(&spi->dev), bits, val);
252 if (wait_uwire_csr_flag(CSRB, 0, 0))
255 uwire_write_reg(UWIRE_TDR, val);
258 val = START | w | (bits << 5);
260 uwire_write_reg(UWIRE_CSR, val);
263 /* Wait till write actually starts.
264 * This is needed with MPU clock 60+ MHz.
265 * REVISIT: we may not have time to catch it...
267 if (wait_uwire_csr_flag(CSRB, CSRB, 1))
273 /* REVISIT: save this for later to get more i/o overlap */
274 if (wait_uwire_csr_flag(CSRB, 0, 0))
277 } else if (t->rx_buf) {
280 /* read one or two bytes at a time */
288 val = START | w | (bits << 0);
289 uwire_write_reg(UWIRE_CSR, val);
292 /* Wait till read actually starts */
293 (void) wait_uwire_csr_flag(CSRB, CSRB, 1);
295 if (wait_uwire_csr_flag(RDRB | CSRB,
299 /* rx bit 0 is last received; multibyte words will
300 * be properly byteswapped on the way to memory.
302 val = uwire_read_reg(UWIRE_RDR);
303 val &= (1 << bits) - 1;
309 pr_debug("%s: read-%d =%04x\n",
310 dev_name(&spi->dev), bits, val);
320 static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
322 struct uwire_state *ust = spi->controller_state;
323 struct uwire_spi *uwire;
333 uwire = spi_master_get_devdata(spi->master);
335 if (spi->chip_select > 3) {
336 pr_debug("%s: cs%d?\n", dev_name(&spi->dev), spi->chip_select);
341 bits = spi->bits_per_word;
342 if (t != NULL && t->bits_per_word)
343 bits = t->bits_per_word;
346 pr_debug("%s: wordsize %d?\n", dev_name(&spi->dev), bits);
350 ust->bits_per_word = bits;
352 /* mode 0..3, clock inverted separately;
353 * standard nCS signaling;
354 * don't treat DI=high as "not ready"
356 if (spi->mode & SPI_CS_HIGH)
357 flags |= UWIRE_CS_ACTIVE_HIGH;
359 if (spi->mode & SPI_CPOL)
360 flags |= UWIRE_CLK_INVERTED;
362 switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
365 flags |= UWIRE_WRITE_FALLING_EDGE | UWIRE_READ_RISING_EDGE;
369 flags |= UWIRE_WRITE_RISING_EDGE | UWIRE_READ_FALLING_EDGE;
373 /* assume it's already enabled */
374 rate = clk_get_rate(uwire->ck);
376 hz = spi->max_speed_hz;
377 if (t != NULL && t->speed_hz)
381 pr_debug("%s: zero speed?\n", dev_name(&spi->dev));
386 /* F_INT = mpu_xor_clk / DIV1 */
387 for (div1_idx = 0; div1_idx < 4; div1_idx++) {
403 div2 = (rate / div1 + hz - 1) / hz;
408 pr_debug("%s: lowest clock %ld, need %d\n",
409 dev_name(&spi->dev), rate / 10 / 8, hz);
414 /* we have to cache this and reset in uwire_chipselect as this is a
415 * global parameter and another uwire device can change it under
417 ust->div1_idx = div1_idx;
418 uwire_set_clk1_div(div1_idx);
426 flags |= UWIRE_FREQ_DIV_2;
431 flags |= UWIRE_FREQ_DIV_4;
438 flags |= UWIRE_FREQ_DIV_8;
442 omap_uwire_configure_mode(spi->chip_select, flags);
443 pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n",
445 clk_get_rate(uwire->ck) / 1000,
452 static int uwire_setup(struct spi_device *spi)
454 struct uwire_state *ust = spi->controller_state;
457 ust = kzalloc(sizeof(*ust), GFP_KERNEL);
460 spi->controller_state = ust;
463 return uwire_setup_transfer(spi, NULL);
466 static void uwire_cleanup(struct spi_device *spi)
468 kfree(spi->controller_state);
471 static void uwire_off(struct uwire_spi *uwire)
473 uwire_write_reg(UWIRE_SR3, 0);
474 clk_disable(uwire->ck);
476 spi_master_put(uwire->bitbang.master);
479 static int uwire_probe(struct platform_device *pdev)
481 struct spi_master *master;
482 struct uwire_spi *uwire;
485 master = spi_alloc_master(&pdev->dev, sizeof *uwire);
489 uwire = spi_master_get_devdata(master);
491 uwire_base = ioremap(UWIRE_BASE_PHYS, UWIRE_IO_SIZE);
493 dev_dbg(&pdev->dev, "can't ioremap UWIRE\n");
494 spi_master_put(master);
498 dev_set_drvdata(&pdev->dev, uwire);
500 uwire->ck = clk_get(&pdev->dev, "fck");
501 if (IS_ERR(uwire->ck)) {
502 status = PTR_ERR(uwire->ck);
503 dev_dbg(&pdev->dev, "no functional clock?\n");
504 spi_master_put(master);
507 clk_enable(uwire->ck);
509 if (cpu_is_omap7xx())
514 uwire_write_reg(UWIRE_SR3, 1);
516 /* the spi->mode bits understood by this driver: */
517 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
519 master->flags = SPI_MASTER_HALF_DUPLEX;
521 master->bus_num = 2; /* "official" */
522 master->num_chipselect = 4;
523 master->setup = uwire_setup;
524 master->cleanup = uwire_cleanup;
526 uwire->bitbang.master = master;
527 uwire->bitbang.chipselect = uwire_chipselect;
528 uwire->bitbang.setup_transfer = uwire_setup_transfer;
529 uwire->bitbang.txrx_bufs = uwire_txrx;
531 status = spi_bitbang_start(&uwire->bitbang);
539 static int uwire_remove(struct platform_device *pdev)
541 struct uwire_spi *uwire = dev_get_drvdata(&pdev->dev);
544 // FIXME remove all child devices, somewhere ...
546 status = spi_bitbang_stop(&uwire->bitbang);
552 /* work with hotplug and coldplug */
553 MODULE_ALIAS("platform:omap_uwire");
555 static struct platform_driver uwire_driver = {
557 .name = "omap_uwire",
558 .owner = THIS_MODULE,
560 .remove = uwire_remove,
561 // suspend ... unuse ck
565 static int __init omap_uwire_init(void)
567 /* FIXME move these into the relevant board init code. also, include
568 * H3 support; it uses tsc2101 like H2 (on a different chipselect).
571 if (machine_is_omap_h2()) {
572 /* defaults: W21 SDO, U18 SDI, V19 SCL */
573 omap_cfg_reg(N14_1610_UWIRE_CS0);
574 omap_cfg_reg(N15_1610_UWIRE_CS1);
576 if (machine_is_omap_perseus2()) {
577 /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */
578 int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000;
579 omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9);
582 return platform_driver_probe(&uwire_driver, uwire_probe);
585 static void __exit omap_uwire_exit(void)
587 platform_driver_unregister(&uwire_driver);
590 subsys_initcall(omap_uwire_init);
591 module_exit(omap_uwire_exit);
593 MODULE_LICENSE("GPL");