drivers/spi/spi-octeon.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2011, 2012 Cavium, Inc.
   7  */
   8
   9 #include <linux/platform_device.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/spi/spi.h>
  12 #include <linux/module.h>
  13 #include <linux/delay.h>
  14 #include <linux/io.h>
  15 #include <linux/of.h>
  16
  17 #include <asm/octeon/octeon.h>
  18 #include <asm/octeon/cvmx-mpi-defs.h>
  19
  20 #define OCTEON_SPI_CFG 0
  21 #define OCTEON_SPI_STS 0x08
  22 #define OCTEON_SPI_TX 0x10
  23 #define OCTEON_SPI_DAT0 0x80
  24
  25 #define OCTEON_SPI_MAX_BYTES 9
  26
  27 #define OCTEON_SPI_MAX_CLOCK_HZ 16000000
  28
  29 struct octeon_spi {
  30         u64 register_base;
  31         u64 last_cfg;
  32         u64 cs_enax;
  33 };
  34
  35 struct octeon_spi_setup {
  36         u32 max_speed_hz;
  37         u8 chip_select;
  38         u8 mode;
  39         u8 bits_per_word;
  40 };
  41
  42 static void octeon_spi_wait_ready(struct octeon_spi *p)
  43 {
  44         union cvmx_mpi_sts mpi_sts;
  45         unsigned int loops = 0;
  46
  47         do {
  48                 if (loops++)
  49                         __delay(500);
  50                 mpi_sts.u64 = cvmx_read_csr(p->register_base + OCTEON_SPI_STS);
  51         } while (mpi_sts.s.busy);
  52 }
  53
  54 static int octeon_spi_do_transfer(struct octeon_spi *p,
  55                                   struct spi_message *msg,
  56                                   struct spi_transfer *xfer,
  57                                   bool last_xfer)
  58 {
  59         union cvmx_mpi_cfg mpi_cfg;
  60         union cvmx_mpi_tx mpi_tx;
  61         unsigned int clkdiv;
  62         unsigned int speed_hz;
  63         int mode;
  64         bool cpha, cpol;
  65         const u8 *tx_buf;
  66         u8 *rx_buf;
  67         int len;
  68         int i;
  69
  70         struct octeon_spi_setup *msg_setup = spi_get_ctldata(msg->spi);
  71
  72         speed_hz = msg_setup->max_speed_hz;
  73         mode = msg_setup->mode;
  74         cpha = mode & SPI_CPHA;
  75         cpol = mode & SPI_CPOL;
  76
  77         if (xfer->speed_hz)
  78                 speed_hz = xfer->speed_hz;
  79
  80         if (speed_hz > OCTEON_SPI_MAX_CLOCK_HZ)
  81                 speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
  82
  83         clkdiv = octeon_get_io_clock_rate() / (2 * speed_hz);
  84
  85         mpi_cfg.u64 = 0;
  86
  87         mpi_cfg.s.clkdiv = clkdiv;
  88         mpi_cfg.s.cshi = (mode & SPI_CS_HIGH) ? 1 : 0;
  89         mpi_cfg.s.lsbfirst = (mode & SPI_LSB_FIRST) ? 1 : 0;
  90         mpi_cfg.s.wireor = (mode & SPI_3WIRE) ? 1 : 0;
  91         mpi_cfg.s.idlelo = cpha != cpol;
  92         mpi_cfg.s.cslate = cpha ? 1 : 0;
  93         mpi_cfg.s.enable = 1;
  94
  95         if (msg_setup->chip_select < 4)
  96                 p->cs_enax |= 1ull << (12 + msg_setup->chip_select);
  97         mpi_cfg.u64 |= p->cs_enax;
  98
  99         if (mpi_cfg.u64 != p->last_cfg) {
 100                 p->last_cfg = mpi_cfg.u64;
 101                 cvmx_write_csr(p->register_base + OCTEON_SPI_CFG, mpi_cfg.u64);
 102         }
 103         tx_buf = xfer->tx_buf;
 104         rx_buf = xfer->rx_buf;
 105         len = xfer->len;
 106         while (len > OCTEON_SPI_MAX_BYTES) {
 107                 for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
 108                         u8 d;
 109                         if (tx_buf)
 110                                 d = *tx_buf++;
 111                         else
 112                                 d = 0;
 113                         cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d);
 114                 }
 115                 mpi_tx.u64 = 0;
 116                 mpi_tx.s.csid = msg_setup->chip_select;
 117                 mpi_tx.s.leavecs = 1;
 118                 mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0;
 119                 mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES;
 120                 cvmx_write_csr(p->register_base + OCTEON_SPI_TX, mpi_tx.u64);
 121
 122                 octeon_spi_wait_ready(p);
 123                 if (rx_buf)
 124                         for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
 125                                 u64 v = cvmx_read_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i));
 126                                 *rx_buf++ = (u8)v;
 127                         }
 128                 len -= OCTEON_SPI_MAX_BYTES;
 129         }
 130
 131         for (i = 0; i < len; i++) {
 132                 u8 d;
 133                 if (tx_buf)
 134                         d = *tx_buf++;
 135                 else
 136                         d = 0;
 137                 cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d);
 138         }
 139
 140         mpi_tx.u64 = 0;
 141         mpi_tx.s.csid = msg_setup->chip_select;
 142         if (last_xfer)
 143                 mpi_tx.s.leavecs = xfer->cs_change;
 144         else
 145                 mpi_tx.s.leavecs = !xfer->cs_change;
 146         mpi_tx.s.txnum = tx_buf ? len : 0;
 147         mpi_tx.s.totnum = len;
 148         cvmx_write_csr(p->register_base + OCTEON_SPI_TX, mpi_tx.u64);
 149
 150         octeon_spi_wait_ready(p);
 151         if (rx_buf)
 152                 for (i = 0; i < len; i++) {
 153                         u64 v = cvmx_read_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i));
 154                         *rx_buf++ = (u8)v;
 155                 }
 156
 157         if (xfer->delay_usecs)
 158                 udelay(xfer->delay_usecs);
 159
 160         return xfer->len;
 161 }
 162
 163 static int octeon_spi_transfer_one_message(struct spi_master *master,
 164                                            struct spi_message *msg)
 165 {
 166         struct octeon_spi *p = spi_master_get_devdata(master);
 167         unsigned int total_len = 0;
 168         int status = 0;
 169         struct spi_transfer *xfer;
 170
 171         /*
 172          * We better have set the configuration via a call to .setup
 173          * before we get here.
 174          */
 175         if (spi_get_ctldata(msg->spi) == NULL) {
 176                 status = -EINVAL;
 177                 goto err;
 178         }
 179
 180         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 181                 bool last_xfer = &xfer->transfer_list == msg->transfers.prev;
 182                 int r = octeon_spi_do_transfer(p, msg, xfer, last_xfer);
 183                 if (r < 0) {
 184                         status = r;
 185                         goto err;
 186                 }
 187                 total_len += r;
 188         }
 189 err:
 190         msg->status = status;
 191         msg->actual_length = total_len;
 192         spi_finalize_current_message(master);
 193         return status;
 194 }
 195
 196 static struct octeon_spi_setup *octeon_spi_new_setup(struct spi_device *spi)
 197 {
 198         struct octeon_spi_setup *setup = kzalloc(sizeof(*setup), GFP_KERNEL);
 199         if (!setup)
 200                 return NULL;
 201
 202         setup->max_speed_hz = spi->max_speed_hz;
 203         setup->chip_select = spi->chip_select;
 204         setup->mode = spi->mode;
 205         setup->bits_per_word = spi->bits_per_word;
 206         return setup;
 207 }
 208
 209 static int octeon_spi_setup(struct spi_device *spi)
 210 {
 211         struct octeon_spi_setup *new_setup;
 212         struct octeon_spi_setup *old_setup = spi_get_ctldata(spi);
 213
 214         new_setup = octeon_spi_new_setup(spi);
 215         if (!new_setup)
 216                 return -ENOMEM;
 217
 218         spi_set_ctldata(spi, new_setup);
 219         kfree(old_setup);
 220
 221         return 0;
 222 }
 223
 224 static void octeon_spi_cleanup(struct spi_device *spi)
 225 {
 226         struct octeon_spi_setup *old_setup = spi_get_ctldata(spi);
 227         spi_set_ctldata(spi, NULL);
 228         kfree(old_setup);
 229 }
 230
 231 static int octeon_spi_probe(struct platform_device *pdev)
 232 {
 233         struct resource *res_mem;
 234         struct spi_master *master;
 235         struct octeon_spi *p;
 236         int err = -ENOENT;
 237
 238         master = spi_alloc_master(&pdev->dev, sizeof(struct octeon_spi));
 239         if (!master)
 240                 return -ENOMEM;
 241         p = spi_master_get_devdata(master);
 242         platform_set_drvdata(pdev, master);
 243
 244         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 245
 246         if (res_mem == NULL) {
 247                 dev_err(&pdev->dev, "found no memory resource\n");
 248                 err = -ENXIO;
 249                 goto fail;
 250         }
 251         if (!devm_request_mem_region(&pdev->dev, res_mem->start,
 252                                      resource_size(res_mem), res_mem->name)) {
 253                 dev_err(&pdev->dev, "request_mem_region failed\n");
 254                 goto fail;
 255         }
 256         p->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start,
 257                                              resource_size(res_mem));
 258
 259         /* Dynamic bus numbering */
 260         master->bus_num = -1;
 261         master->num_chipselect = 4;
 262         master->mode_bits = SPI_CPHA |
 263                             SPI_CPOL |
 264                             SPI_CS_HIGH |
 265                             SPI_LSB_FIRST |
 266                             SPI_3WIRE;
 267
 268         master->setup = octeon_spi_setup;
 269         master->cleanup = octeon_spi_cleanup;
 270         master->transfer_one_message = octeon_spi_transfer_one_message;
 271         master->bits_per_word_mask = SPI_BPW_MASK(8);
 272
 273         master->dev.of_node = pdev->dev.of_node;
 274         err = devm_spi_register_master(&pdev->dev, master);
 275         if (err) {
 276                 dev_err(&pdev->dev, "register master failed: %d\n", err);
 277                 goto fail;
 278         }
 279
 280         dev_info(&pdev->dev, "OCTEON SPI bus driver\n");
 281
 282         return 0;
 283 fail:
 284         spi_master_put(master);
 285         return err;
 286 }
 287
 288 static int octeon_spi_remove(struct platform_device *pdev)
 289 {
 290         struct spi_master *master = platform_get_drvdata(pdev);
 291         struct octeon_spi *p = spi_master_get_devdata(master);
 292         u64 register_base = p->register_base;
 293
 294         /* Clear the CSENA* and put everything in a known state. */
 295         cvmx_write_csr(register_base + OCTEON_SPI_CFG, 0);
 296
 297         return 0;
 298 }
 299
 300 static struct of_device_id octeon_spi_match[] = {
 301         { .compatible = "cavium,octeon-3010-spi", },
 302         {},
 303 };
 304 MODULE_DEVICE_TABLE(of, octeon_spi_match);
 305
 306 static struct platform_driver octeon_spi_driver = {
 307         .driver = {
 308                 .name           = "spi-octeon",
 309                 .owner          = THIS_MODULE,
 310                 .of_match_table = octeon_spi_match,
 311         },
 312         .probe          = octeon_spi_probe,
 313         .remove         = octeon_spi_remove,
 314 };
 315
 316 module_platform_driver(octeon_spi_driver);
 317
 318 MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
 319 MODULE_AUTHOR("David Daney");
 320 MODULE_LICENSE("GPL");