1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Leilk Liu <leilk.liu@mediatek.com>
8 #include <linux/device.h>
10 #include <linux/interrupt.h>
12 #include <linux/ioport.h>
13 #include <linux/module.h>
15 #include <linux/of_gpio.h>
16 #include <linux/platform_device.h>
17 #include <linux/platform_data/spi-mt65xx.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/spi/spi.h>
20 #include <linux/dma-mapping.h>
22 #define SPI_CFG0_REG 0x0000
23 #define SPI_CFG1_REG 0x0004
24 #define SPI_TX_SRC_REG 0x0008
25 #define SPI_RX_DST_REG 0x000c
26 #define SPI_TX_DATA_REG 0x0010
27 #define SPI_RX_DATA_REG 0x0014
28 #define SPI_CMD_REG 0x0018
29 #define SPI_STATUS0_REG 0x001c
30 #define SPI_PAD_SEL_REG 0x0024
31 #define SPI_CFG2_REG 0x0028
32 #define SPI_TX_SRC_REG_64 0x002c
33 #define SPI_RX_DST_REG_64 0x0030
35 #define SPI_CFG0_SCK_HIGH_OFFSET 0
36 #define SPI_CFG0_SCK_LOW_OFFSET 8
37 #define SPI_CFG0_CS_HOLD_OFFSET 16
38 #define SPI_CFG0_CS_SETUP_OFFSET 24
39 #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
40 #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
42 #define SPI_CFG1_CS_IDLE_OFFSET 0
43 #define SPI_CFG1_PACKET_LOOP_OFFSET 8
44 #define SPI_CFG1_PACKET_LENGTH_OFFSET 16
45 #define SPI_CFG1_GET_TICK_DLY_OFFSET 30
47 #define SPI_CFG1_CS_IDLE_MASK 0xff
48 #define SPI_CFG1_PACKET_LOOP_MASK 0xff00
49 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
50 #define SPI_CFG2_SCK_HIGH_OFFSET 0
51 #define SPI_CFG2_SCK_LOW_OFFSET 16
53 #define SPI_CMD_ACT BIT(0)
54 #define SPI_CMD_RESUME BIT(1)
55 #define SPI_CMD_RST BIT(2)
56 #define SPI_CMD_PAUSE_EN BIT(4)
57 #define SPI_CMD_DEASSERT BIT(5)
58 #define SPI_CMD_SAMPLE_SEL BIT(6)
59 #define SPI_CMD_CS_POL BIT(7)
60 #define SPI_CMD_CPHA BIT(8)
61 #define SPI_CMD_CPOL BIT(9)
62 #define SPI_CMD_RX_DMA BIT(10)
63 #define SPI_CMD_TX_DMA BIT(11)
64 #define SPI_CMD_TXMSBF BIT(12)
65 #define SPI_CMD_RXMSBF BIT(13)
66 #define SPI_CMD_RX_ENDIAN BIT(14)
67 #define SPI_CMD_TX_ENDIAN BIT(15)
68 #define SPI_CMD_FINISH_IE BIT(16)
69 #define SPI_CMD_PAUSE_IE BIT(17)
71 #define MT8173_SPI_MAX_PAD_SEL 3
73 #define MTK_SPI_PAUSE_INT_STATUS 0x2
75 #define MTK_SPI_IDLE 0
76 #define MTK_SPI_PAUSED 1
78 #define MTK_SPI_MAX_FIFO_SIZE 32U
79 #define MTK_SPI_PACKET_SIZE 1024
80 #define MTK_SPI_32BITS_MASK (0xffffffff)
82 #define DMA_ADDR_EXT_BITS (36)
83 #define DMA_ADDR_DEF_BITS (32)
85 struct mtk_spi_compatible {
87 /* Must explicitly send dummy Tx bytes to do Rx only transfer */
89 /* some IC design adjust cfg register to enhance time accuracy */
91 /* some IC support DMA addr extension */
100 struct clk *parent_clk, *sel_clk, *spi_clk;
101 struct spi_transfer *cur_transfer;
104 struct scatterlist *tx_sgl, *rx_sgl;
105 u32 tx_sgl_len, rx_sgl_len;
106 const struct mtk_spi_compatible *dev_comp;
109 static const struct mtk_spi_compatible mtk_common_compat;
111 static const struct mtk_spi_compatible mt2712_compat = {
115 static const struct mtk_spi_compatible mt6765_compat = {
116 .need_pad_sel = true,
118 .enhance_timing = true,
122 static const struct mtk_spi_compatible mt7622_compat = {
124 .enhance_timing = true,
127 static const struct mtk_spi_compatible mt8173_compat = {
128 .need_pad_sel = true,
132 static const struct mtk_spi_compatible mt8183_compat = {
133 .need_pad_sel = true,
135 .enhance_timing = true,
139 * A piece of default chip info unless the platform
142 static const struct mtk_chip_config mtk_default_chip_info = {
146 static const struct of_device_id mtk_spi_of_match[] = {
147 { .compatible = "mediatek,mt2701-spi",
148 .data = (void *)&mtk_common_compat,
150 { .compatible = "mediatek,mt2712-spi",
151 .data = (void *)&mt2712_compat,
153 { .compatible = "mediatek,mt6589-spi",
154 .data = (void *)&mtk_common_compat,
156 { .compatible = "mediatek,mt6765-spi",
157 .data = (void *)&mt6765_compat,
159 { .compatible = "mediatek,mt7622-spi",
160 .data = (void *)&mt7622_compat,
162 { .compatible = "mediatek,mt7629-spi",
163 .data = (void *)&mt7622_compat,
165 { .compatible = "mediatek,mt8135-spi",
166 .data = (void *)&mtk_common_compat,
168 { .compatible = "mediatek,mt8173-spi",
169 .data = (void *)&mt8173_compat,
171 { .compatible = "mediatek,mt8183-spi",
172 .data = (void *)&mt8183_compat,
174 { .compatible = "mediatek,mt8192-spi",
175 .data = (void *)&mt6765_compat,
179 MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
181 static void mtk_spi_reset(struct mtk_spi *mdata)
185 /* set the software reset bit in SPI_CMD_REG. */
186 reg_val = readl(mdata->base + SPI_CMD_REG);
187 reg_val |= SPI_CMD_RST;
188 writel(reg_val, mdata->base + SPI_CMD_REG);
190 reg_val = readl(mdata->base + SPI_CMD_REG);
191 reg_val &= ~SPI_CMD_RST;
192 writel(reg_val, mdata->base + SPI_CMD_REG);
195 static int mtk_spi_prepare_message(struct spi_master *master,
196 struct spi_message *msg)
200 struct spi_device *spi = msg->spi;
201 struct mtk_chip_config *chip_config = spi->controller_data;
202 struct mtk_spi *mdata = spi_master_get_devdata(master);
204 cpha = spi->mode & SPI_CPHA ? 1 : 0;
205 cpol = spi->mode & SPI_CPOL ? 1 : 0;
207 reg_val = readl(mdata->base + SPI_CMD_REG);
209 reg_val |= SPI_CMD_CPHA;
211 reg_val &= ~SPI_CMD_CPHA;
213 reg_val |= SPI_CMD_CPOL;
215 reg_val &= ~SPI_CMD_CPOL;
217 /* set the mlsbx and mlsbtx */
218 if (spi->mode & SPI_LSB_FIRST) {
219 reg_val &= ~SPI_CMD_TXMSBF;
220 reg_val &= ~SPI_CMD_RXMSBF;
222 reg_val |= SPI_CMD_TXMSBF;
223 reg_val |= SPI_CMD_RXMSBF;
226 /* set the tx/rx endian */
227 #ifdef __LITTLE_ENDIAN
228 reg_val &= ~SPI_CMD_TX_ENDIAN;
229 reg_val &= ~SPI_CMD_RX_ENDIAN;
231 reg_val |= SPI_CMD_TX_ENDIAN;
232 reg_val |= SPI_CMD_RX_ENDIAN;
235 if (mdata->dev_comp->enhance_timing) {
236 /* set CS polarity */
237 if (spi->mode & SPI_CS_HIGH)
238 reg_val |= SPI_CMD_CS_POL;
240 reg_val &= ~SPI_CMD_CS_POL;
242 if (chip_config->sample_sel)
243 reg_val |= SPI_CMD_SAMPLE_SEL;
245 reg_val &= ~SPI_CMD_SAMPLE_SEL;
248 /* set finish and pause interrupt always enable */
249 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
251 /* disable dma mode */
252 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
254 /* disable deassert mode */
255 reg_val &= ~SPI_CMD_DEASSERT;
257 writel(reg_val, mdata->base + SPI_CMD_REG);
260 if (mdata->dev_comp->need_pad_sel)
261 writel(mdata->pad_sel[spi->chip_select],
262 mdata->base + SPI_PAD_SEL_REG);
267 static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
270 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
272 if (spi->mode & SPI_CS_HIGH)
275 reg_val = readl(mdata->base + SPI_CMD_REG);
277 reg_val |= SPI_CMD_PAUSE_EN;
278 writel(reg_val, mdata->base + SPI_CMD_REG);
280 reg_val &= ~SPI_CMD_PAUSE_EN;
281 writel(reg_val, mdata->base + SPI_CMD_REG);
282 mdata->state = MTK_SPI_IDLE;
283 mtk_spi_reset(mdata);
287 static void mtk_spi_prepare_transfer(struct spi_master *master,
288 struct spi_transfer *xfer)
290 u32 spi_clk_hz, div, sck_time, reg_val;
291 struct mtk_spi *mdata = spi_master_get_devdata(master);
293 spi_clk_hz = clk_get_rate(mdata->spi_clk);
294 if (xfer->speed_hz < spi_clk_hz / 2)
295 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
299 sck_time = (div + 1) / 2;
301 if (mdata->dev_comp->enhance_timing) {
302 reg_val = readl(mdata->base + SPI_CFG2_REG);
303 reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET);
304 reg_val |= (((sck_time - 1) & 0xffff)
305 << SPI_CFG2_SCK_HIGH_OFFSET);
306 reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET);
307 reg_val |= (((sck_time - 1) & 0xffff)
308 << SPI_CFG2_SCK_LOW_OFFSET);
309 writel(reg_val, mdata->base + SPI_CFG2_REG);
311 reg_val = readl(mdata->base + SPI_CFG0_REG);
312 reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET);
313 reg_val |= (((sck_time - 1) & 0xff)
314 << SPI_CFG0_SCK_HIGH_OFFSET);
315 reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET);
316 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
317 writel(reg_val, mdata->base + SPI_CFG0_REG);
321 static void mtk_spi_setup_packet(struct spi_master *master)
323 u32 packet_size, packet_loop, reg_val;
324 struct mtk_spi *mdata = spi_master_get_devdata(master);
326 packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
327 packet_loop = mdata->xfer_len / packet_size;
329 reg_val = readl(mdata->base + SPI_CFG1_REG);
330 reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
331 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
332 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
333 writel(reg_val, mdata->base + SPI_CFG1_REG);
336 static void mtk_spi_enable_transfer(struct spi_master *master)
339 struct mtk_spi *mdata = spi_master_get_devdata(master);
341 cmd = readl(mdata->base + SPI_CMD_REG);
342 if (mdata->state == MTK_SPI_IDLE)
345 cmd |= SPI_CMD_RESUME;
346 writel(cmd, mdata->base + SPI_CMD_REG);
349 static int mtk_spi_get_mult_delta(u32 xfer_len)
353 if (xfer_len > MTK_SPI_PACKET_SIZE)
354 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
361 static void mtk_spi_update_mdata_len(struct spi_master *master)
364 struct mtk_spi *mdata = spi_master_get_devdata(master);
366 if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
367 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
368 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
369 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
370 mdata->rx_sgl_len = mult_delta;
371 mdata->tx_sgl_len -= mdata->xfer_len;
373 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
374 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
375 mdata->tx_sgl_len = mult_delta;
376 mdata->rx_sgl_len -= mdata->xfer_len;
378 } else if (mdata->tx_sgl_len) {
379 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
380 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
381 mdata->tx_sgl_len = mult_delta;
382 } else if (mdata->rx_sgl_len) {
383 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
384 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
385 mdata->rx_sgl_len = mult_delta;
389 static void mtk_spi_setup_dma_addr(struct spi_master *master,
390 struct spi_transfer *xfer)
392 struct mtk_spi *mdata = spi_master_get_devdata(master);
395 writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK),
396 mdata->base + SPI_TX_SRC_REG);
397 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
398 if (mdata->dev_comp->dma_ext)
399 writel((u32)(xfer->tx_dma >> 32),
400 mdata->base + SPI_TX_SRC_REG_64);
405 writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK),
406 mdata->base + SPI_RX_DST_REG);
407 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
408 if (mdata->dev_comp->dma_ext)
409 writel((u32)(xfer->rx_dma >> 32),
410 mdata->base + SPI_RX_DST_REG_64);
415 static int mtk_spi_fifo_transfer(struct spi_master *master,
416 struct spi_device *spi,
417 struct spi_transfer *xfer)
421 struct mtk_spi *mdata = spi_master_get_devdata(master);
423 mdata->cur_transfer = xfer;
424 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
425 mdata->num_xfered = 0;
426 mtk_spi_prepare_transfer(master, xfer);
427 mtk_spi_setup_packet(master);
431 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
434 ioread32_rep(mdata->base + SPI_RX_DATA_REG, xfer->rx_buf, cnt);
436 remainder = xfer->len % 4;
440 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder);
441 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
444 reg_val = readl(mdata->base + SPI_RX_DATA_REG);
445 memcpy(xfer->rx_buf + (cnt * 4), ®_val, remainder);
449 mtk_spi_enable_transfer(master);
454 static int mtk_spi_dma_transfer(struct spi_master *master,
455 struct spi_device *spi,
456 struct spi_transfer *xfer)
459 struct mtk_spi *mdata = spi_master_get_devdata(master);
461 mdata->tx_sgl = NULL;
462 mdata->rx_sgl = NULL;
463 mdata->tx_sgl_len = 0;
464 mdata->rx_sgl_len = 0;
465 mdata->cur_transfer = xfer;
466 mdata->num_xfered = 0;
468 mtk_spi_prepare_transfer(master, xfer);
470 cmd = readl(mdata->base + SPI_CMD_REG);
472 cmd |= SPI_CMD_TX_DMA;
474 cmd |= SPI_CMD_RX_DMA;
475 writel(cmd, mdata->base + SPI_CMD_REG);
478 mdata->tx_sgl = xfer->tx_sg.sgl;
480 mdata->rx_sgl = xfer->rx_sg.sgl;
483 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
484 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
487 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
488 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
491 mtk_spi_update_mdata_len(master);
492 mtk_spi_setup_packet(master);
493 mtk_spi_setup_dma_addr(master, xfer);
494 mtk_spi_enable_transfer(master);
499 static int mtk_spi_transfer_one(struct spi_master *master,
500 struct spi_device *spi,
501 struct spi_transfer *xfer)
503 if (master->can_dma(master, spi, xfer))
504 return mtk_spi_dma_transfer(master, spi, xfer);
506 return mtk_spi_fifo_transfer(master, spi, xfer);
509 static bool mtk_spi_can_dma(struct spi_master *master,
510 struct spi_device *spi,
511 struct spi_transfer *xfer)
513 /* Buffers for DMA transactions must be 4-byte aligned */
514 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE &&
515 (unsigned long)xfer->tx_buf % 4 == 0 &&
516 (unsigned long)xfer->rx_buf % 4 == 0);
519 static int mtk_spi_set_hw_cs_timing(struct spi_device *spi,
520 struct spi_delay *setup,
521 struct spi_delay *hold,
522 struct spi_delay *inactive)
524 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
525 u16 setup_dly, hold_dly, inactive_dly;
528 if ((setup && setup->unit != SPI_DELAY_UNIT_SCK) ||
529 (hold && hold->unit != SPI_DELAY_UNIT_SCK) ||
530 (inactive && inactive->unit != SPI_DELAY_UNIT_SCK)) {
532 "Invalid delay unit, should be SPI_DELAY_UNIT_SCK\n");
536 setup_dly = setup ? setup->value : 1;
537 hold_dly = hold ? hold->value : 1;
538 inactive_dly = inactive ? inactive->value : 1;
540 reg_val = readl(mdata->base + SPI_CFG0_REG);
541 if (mdata->dev_comp->enhance_timing) {
542 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
543 reg_val |= (((hold_dly - 1) & 0xffff)
544 << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
545 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
546 reg_val |= (((setup_dly - 1) & 0xffff)
547 << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
549 reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET);
550 reg_val |= (((hold_dly - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
551 reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET);
552 reg_val |= (((setup_dly - 1) & 0xff)
553 << SPI_CFG0_CS_SETUP_OFFSET);
555 writel(reg_val, mdata->base + SPI_CFG0_REG);
557 reg_val = readl(mdata->base + SPI_CFG1_REG);
558 reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
559 reg_val |= (((inactive_dly - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
560 writel(reg_val, mdata->base + SPI_CFG1_REG);
565 static int mtk_spi_setup(struct spi_device *spi)
567 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
569 if (!spi->controller_data)
570 spi->controller_data = (void *)&mtk_default_chip_info;
572 if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio))
573 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
578 static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
580 u32 cmd, reg_val, cnt, remainder, len;
581 struct spi_master *master = dev_id;
582 struct mtk_spi *mdata = spi_master_get_devdata(master);
583 struct spi_transfer *trans = mdata->cur_transfer;
585 reg_val = readl(mdata->base + SPI_STATUS0_REG);
586 if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
587 mdata->state = MTK_SPI_PAUSED;
589 mdata->state = MTK_SPI_IDLE;
591 if (!master->can_dma(master, master->cur_msg->spi, trans)) {
593 cnt = mdata->xfer_len / 4;
594 ioread32_rep(mdata->base + SPI_RX_DATA_REG,
595 trans->rx_buf + mdata->num_xfered, cnt);
596 remainder = mdata->xfer_len % 4;
598 reg_val = readl(mdata->base + SPI_RX_DATA_REG);
599 memcpy(trans->rx_buf +
607 mdata->num_xfered += mdata->xfer_len;
608 if (mdata->num_xfered == trans->len) {
609 spi_finalize_current_transfer(master);
613 len = trans->len - mdata->num_xfered;
614 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len);
615 mtk_spi_setup_packet(master);
617 cnt = mdata->xfer_len / 4;
618 iowrite32_rep(mdata->base + SPI_TX_DATA_REG,
619 trans->tx_buf + mdata->num_xfered, cnt);
621 remainder = mdata->xfer_len % 4;
625 trans->tx_buf + (cnt * 4) + mdata->num_xfered,
627 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
630 mtk_spi_enable_transfer(master);
636 trans->tx_dma += mdata->xfer_len;
638 trans->rx_dma += mdata->xfer_len;
640 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
641 mdata->tx_sgl = sg_next(mdata->tx_sgl);
643 trans->tx_dma = sg_dma_address(mdata->tx_sgl);
644 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
647 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
648 mdata->rx_sgl = sg_next(mdata->rx_sgl);
650 trans->rx_dma = sg_dma_address(mdata->rx_sgl);
651 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
655 if (!mdata->tx_sgl && !mdata->rx_sgl) {
656 /* spi disable dma */
657 cmd = readl(mdata->base + SPI_CMD_REG);
658 cmd &= ~SPI_CMD_TX_DMA;
659 cmd &= ~SPI_CMD_RX_DMA;
660 writel(cmd, mdata->base + SPI_CMD_REG);
662 spi_finalize_current_transfer(master);
666 mtk_spi_update_mdata_len(master);
667 mtk_spi_setup_packet(master);
668 mtk_spi_setup_dma_addr(master, trans);
669 mtk_spi_enable_transfer(master);
674 static int mtk_spi_probe(struct platform_device *pdev)
676 struct spi_master *master;
677 struct mtk_spi *mdata;
678 const struct of_device_id *of_id;
679 int i, irq, ret, addr_bits;
681 master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
683 dev_err(&pdev->dev, "failed to alloc spi master\n");
687 master->auto_runtime_pm = true;
688 master->dev.of_node = pdev->dev.of_node;
689 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
691 master->set_cs = mtk_spi_set_cs;
692 master->prepare_message = mtk_spi_prepare_message;
693 master->transfer_one = mtk_spi_transfer_one;
694 master->can_dma = mtk_spi_can_dma;
695 master->setup = mtk_spi_setup;
696 master->set_cs_timing = mtk_spi_set_hw_cs_timing;
698 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
700 dev_err(&pdev->dev, "failed to probe of_node\n");
705 mdata = spi_master_get_devdata(master);
706 mdata->dev_comp = of_id->data;
708 if (mdata->dev_comp->enhance_timing)
709 master->mode_bits |= SPI_CS_HIGH;
711 if (mdata->dev_comp->must_tx)
712 master->flags = SPI_MASTER_MUST_TX;
714 if (mdata->dev_comp->need_pad_sel) {
715 mdata->pad_num = of_property_count_u32_elems(
717 "mediatek,pad-select");
718 if (mdata->pad_num < 0) {
720 "No 'mediatek,pad-select' property\n");
725 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num,
726 sizeof(u32), GFP_KERNEL);
727 if (!mdata->pad_sel) {
732 for (i = 0; i < mdata->pad_num; i++) {
733 of_property_read_u32_index(pdev->dev.of_node,
734 "mediatek,pad-select",
735 i, &mdata->pad_sel[i]);
736 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) {
737 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n",
738 i, mdata->pad_sel[i]);
745 platform_set_drvdata(pdev, master);
746 mdata->base = devm_platform_ioremap_resource(pdev, 0);
747 if (IS_ERR(mdata->base)) {
748 ret = PTR_ERR(mdata->base);
752 irq = platform_get_irq(pdev, 0);
758 if (!pdev->dev.dma_mask)
759 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
761 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
762 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
764 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
768 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
769 if (IS_ERR(mdata->parent_clk)) {
770 ret = PTR_ERR(mdata->parent_clk);
771 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
775 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
776 if (IS_ERR(mdata->sel_clk)) {
777 ret = PTR_ERR(mdata->sel_clk);
778 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
782 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
783 if (IS_ERR(mdata->spi_clk)) {
784 ret = PTR_ERR(mdata->spi_clk);
785 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
789 ret = clk_prepare_enable(mdata->spi_clk);
791 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
795 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
797 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
798 clk_disable_unprepare(mdata->spi_clk);
802 clk_disable_unprepare(mdata->spi_clk);
804 pm_runtime_enable(&pdev->dev);
806 if (mdata->dev_comp->need_pad_sel) {
807 if (mdata->pad_num != master->num_chipselect) {
809 "pad_num does not match num_chipselect(%d != %d)\n",
810 mdata->pad_num, master->num_chipselect);
812 goto err_disable_runtime_pm;
815 if (!master->cs_gpios && master->num_chipselect > 1) {
817 "cs_gpios not specified and num_chipselect > 1\n");
819 goto err_disable_runtime_pm;
822 if (master->cs_gpios) {
823 for (i = 0; i < master->num_chipselect; i++) {
824 ret = devm_gpio_request(&pdev->dev,
826 dev_name(&pdev->dev));
829 "can't get CS GPIO %i\n", i);
830 goto err_disable_runtime_pm;
836 if (mdata->dev_comp->dma_ext)
837 addr_bits = DMA_ADDR_EXT_BITS;
839 addr_bits = DMA_ADDR_DEF_BITS;
840 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits));
842 dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n",
845 ret = devm_spi_register_master(&pdev->dev, master);
847 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
848 goto err_disable_runtime_pm;
853 err_disable_runtime_pm:
854 pm_runtime_disable(&pdev->dev);
856 spi_master_put(master);
861 static int mtk_spi_remove(struct platform_device *pdev)
863 struct spi_master *master = platform_get_drvdata(pdev);
864 struct mtk_spi *mdata = spi_master_get_devdata(master);
866 pm_runtime_disable(&pdev->dev);
868 mtk_spi_reset(mdata);
873 #ifdef CONFIG_PM_SLEEP
874 static int mtk_spi_suspend(struct device *dev)
877 struct spi_master *master = dev_get_drvdata(dev);
878 struct mtk_spi *mdata = spi_master_get_devdata(master);
880 ret = spi_master_suspend(master);
884 if (!pm_runtime_suspended(dev))
885 clk_disable_unprepare(mdata->spi_clk);
890 static int mtk_spi_resume(struct device *dev)
893 struct spi_master *master = dev_get_drvdata(dev);
894 struct mtk_spi *mdata = spi_master_get_devdata(master);
896 if (!pm_runtime_suspended(dev)) {
897 ret = clk_prepare_enable(mdata->spi_clk);
899 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
904 ret = spi_master_resume(master);
906 clk_disable_unprepare(mdata->spi_clk);
910 #endif /* CONFIG_PM_SLEEP */
913 static int mtk_spi_runtime_suspend(struct device *dev)
915 struct spi_master *master = dev_get_drvdata(dev);
916 struct mtk_spi *mdata = spi_master_get_devdata(master);
918 clk_disable_unprepare(mdata->spi_clk);
923 static int mtk_spi_runtime_resume(struct device *dev)
925 struct spi_master *master = dev_get_drvdata(dev);
926 struct mtk_spi *mdata = spi_master_get_devdata(master);
929 ret = clk_prepare_enable(mdata->spi_clk);
931 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
937 #endif /* CONFIG_PM */
939 static const struct dev_pm_ops mtk_spi_pm = {
940 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
941 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
942 mtk_spi_runtime_resume, NULL)
945 static struct platform_driver mtk_spi_driver = {
949 .of_match_table = mtk_spi_of_match,
951 .probe = mtk_spi_probe,
952 .remove = mtk_spi_remove,
955 module_platform_driver(mtk_spi_driver);
957 MODULE_DESCRIPTION("MTK SPI Controller driver");
958 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
959 MODULE_LICENSE("GPL v2");
960 MODULE_ALIAS("platform:mtk-spi");