1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
11 int spi_mem_exec_op(struct spi_slave *slave,
12 const struct spi_mem_op *op)
15 const u8 *tx_buf = NULL;
23 if (op->data.nbytes) {
24 if (op->data.dir == SPI_MEM_DATA_IN)
25 rx_buf = op->data.buf.in;
27 tx_buf = op->data.buf.out;
30 op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
31 op_buf = calloc(1, op_len);
33 ret = spi_claim_bus(slave);
37 op_buf[pos++] = op->cmd.opcode;
39 if (op->addr.nbytes) {
40 for (i = 0; i < op->addr.nbytes; i++)
41 op_buf[pos + i] = op->addr.val >>
42 (8 * (op->addr.nbytes - i - 1));
44 pos += op->addr.nbytes;
48 memset(op_buf + pos, 0xff, op->dummy.nbytes);
50 /* 1st transfer: opcode + address + dummy cycles */
51 flag = SPI_XFER_BEGIN;
52 /* Make sure to set END bit if no tx or rx data messages follow */
53 if (!tx_buf && !rx_buf)
56 ret = spi_xfer(slave, op_len * 8, op_buf, NULL, flag);
60 /* 2nd transfer: rx or tx data path */
61 if (tx_buf || rx_buf) {
62 ret = spi_xfer(slave, op->data.nbytes * 8, tx_buf,
63 rx_buf, SPI_XFER_END);
68 spi_release_bus(slave);
70 for (i = 0; i < pos; i++)
71 debug("%02x ", op_buf[i]);
73 tx_buf || rx_buf ? op->data.nbytes : 0,
74 tx_buf || rx_buf ? (tx_buf ? "out" : "in") : "-");
75 for (i = 0; i < op->data.nbytes; i++)
76 debug("%02x ", tx_buf ? tx_buf[i] : rx_buf[i]);
77 debug("[ret %d]\n", ret);
87 int spi_mem_adjust_op_size(struct spi_slave *slave,
88 struct spi_mem_op *op)
92 len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
93 if (slave->max_write_size && len > slave->max_write_size)
96 if (op->data.dir == SPI_MEM_DATA_IN) {
97 if (slave->max_read_size)
98 op->data.nbytes = min(op->data.nbytes,
99 slave->max_read_size);
100 } else if (slave->max_write_size) {
101 op->data.nbytes = min(op->data.nbytes,
102 slave->max_write_size - len);
105 if (!op->data.nbytes)
111 static int spi_check_buswidth_req(struct spi_slave *slave, u8 buswidth, bool tx)
113 u32 mode = slave->mode;
120 if ((tx && (mode & (SPI_TX_DUAL | SPI_TX_QUAD))) ||
121 (!tx && (mode & (SPI_RX_DUAL | SPI_RX_QUAD))))
127 if ((tx && (mode & SPI_TX_QUAD)) ||
128 (!tx && (mode & SPI_RX_QUAD)))
133 if ((tx && (mode & SPI_TX_OCTAL)) ||
134 (!tx && (mode & SPI_RX_OCTAL)))
146 bool spi_mem_supports_op(struct spi_slave *slave, const struct spi_mem_op *op)
148 if (spi_check_buswidth_req(slave, op->cmd.buswidth, true))
151 if (op->addr.nbytes &&
152 spi_check_buswidth_req(slave, op->addr.buswidth, true))
155 if (op->dummy.nbytes &&
156 spi_check_buswidth_req(slave, op->dummy.buswidth, true))
159 if (op->data.nbytes &&
160 spi_check_buswidth_req(slave, op->data.buswidth,
161 op->data.dir == SPI_MEM_DATA_OUT))
164 if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
167 if (op->cmd.nbytes != 1)