1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel PCH/PCU SPI flash driver.
5 * Copyright (C) 2016 - 2022, Intel Corporation
6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
9 #include <linux/iopoll.h>
10 #include <linux/module.h>
12 #include <linux/mtd/partitions.h>
13 #include <linux/mtd/spi-nor.h>
15 #include <linux/spi/flash.h>
16 #include <linux/spi/spi.h>
17 #include <linux/spi/spi-mem.h>
19 #include "spi-intel.h"
21 /* Offsets are from @ispi->base */
24 #define HSFSTS_CTL 0x04
25 #define HSFSTS_CTL_FSMIE BIT(31)
26 #define HSFSTS_CTL_FDBC_SHIFT 24
27 #define HSFSTS_CTL_FDBC_MASK (0x3f << HSFSTS_CTL_FDBC_SHIFT)
29 #define HSFSTS_CTL_FCYCLE_SHIFT 17
30 #define HSFSTS_CTL_FCYCLE_MASK (0x0f << HSFSTS_CTL_FCYCLE_SHIFT)
31 /* HW sequencer opcodes */
32 #define HSFSTS_CTL_FCYCLE_READ (0x00 << HSFSTS_CTL_FCYCLE_SHIFT)
33 #define HSFSTS_CTL_FCYCLE_WRITE (0x02 << HSFSTS_CTL_FCYCLE_SHIFT)
34 #define HSFSTS_CTL_FCYCLE_ERASE (0x03 << HSFSTS_CTL_FCYCLE_SHIFT)
35 #define HSFSTS_CTL_FCYCLE_ERASE_64K (0x04 << HSFSTS_CTL_FCYCLE_SHIFT)
36 #define HSFSTS_CTL_FCYCLE_RDID (0x06 << HSFSTS_CTL_FCYCLE_SHIFT)
37 #define HSFSTS_CTL_FCYCLE_WRSR (0x07 << HSFSTS_CTL_FCYCLE_SHIFT)
38 #define HSFSTS_CTL_FCYCLE_RDSR (0x08 << HSFSTS_CTL_FCYCLE_SHIFT)
40 #define HSFSTS_CTL_FGO BIT(16)
41 #define HSFSTS_CTL_FLOCKDN BIT(15)
42 #define HSFSTS_CTL_FDV BIT(14)
43 #define HSFSTS_CTL_SCIP BIT(5)
44 #define HSFSTS_CTL_AEL BIT(2)
45 #define HSFSTS_CTL_FCERR BIT(1)
46 #define HSFSTS_CTL_FDONE BIT(0)
50 #define FDATA(n) (0x10 + ((n) * 4))
54 #define FREG(n) (0x54 + ((n) * 4))
55 #define FREG_BASE_MASK 0x3fff
56 #define FREG_LIMIT_SHIFT 16
57 #define FREG_LIMIT_MASK (0x03fff << FREG_LIMIT_SHIFT)
59 /* Offset is from @ispi->pregs */
60 #define PR(n) ((n) * 4)
61 #define PR_WPE BIT(31)
62 #define PR_LIMIT_SHIFT 16
63 #define PR_LIMIT_MASK (0x3fff << PR_LIMIT_SHIFT)
64 #define PR_RPE BIT(15)
65 #define PR_BASE_MASK 0x3fff
67 /* Offsets are from @ispi->sregs */
68 #define SSFSTS_CTL 0x00
69 #define SSFSTS_CTL_FSMIE BIT(23)
70 #define SSFSTS_CTL_DS BIT(22)
71 #define SSFSTS_CTL_DBC_SHIFT 16
72 #define SSFSTS_CTL_SPOP BIT(11)
73 #define SSFSTS_CTL_ACS BIT(10)
74 #define SSFSTS_CTL_SCGO BIT(9)
75 #define SSFSTS_CTL_COP_SHIFT 12
76 #define SSFSTS_CTL_FRS BIT(7)
77 #define SSFSTS_CTL_DOFRS BIT(6)
78 #define SSFSTS_CTL_AEL BIT(4)
79 #define SSFSTS_CTL_FCERR BIT(3)
80 #define SSFSTS_CTL_FDONE BIT(2)
81 #define SSFSTS_CTL_SCIP BIT(0)
83 #define PREOP_OPTYPE 0x04
87 #define OPTYPE_READ_NO_ADDR 0
88 #define OPTYPE_WRITE_NO_ADDR 1
89 #define OPTYPE_READ_WITH_ADDR 2
90 #define OPTYPE_WRITE_WITH_ADDR 3
94 #define BYT_SSFSTS_CTL 0x90
95 #define BYT_FREG_NUM 5
99 #define LPT_SSFSTS_CTL 0x90
100 #define LPT_FREG_NUM 5
104 #define BXT_SSFSTS_CTL 0xa0
105 #define BXT_FREG_NUM 12
109 #define CNL_FREG_NUM 6
114 #define ERASE_OPCODE_SHIFT 8
115 #define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
116 #define ERASE_64K_OPCODE_SHIFT 16
117 #define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
119 #define INTEL_SPI_TIMEOUT 5000 /* ms */
120 #define INTEL_SPI_FIFO_SZ 64
123 * struct intel_spi - Driver private data
124 * @dev: Device pointer
125 * @info: Pointer to board specific info
126 * @base: Beginning of MMIO space
127 * @pregs: Start of protection registers
128 * @sregs: Start of software sequencer registers
129 * @master: Pointer to the SPI controller structure
130 * @nregions: Maximum number of regions
131 * @pr_num: Maximum number of protected range registers
132 * @locked: Is SPI setting locked
133 * @swseq_reg: Use SW sequencer in register reads/writes
134 * @swseq_erase: Use SW sequencer in erase operation
135 * @atomic_preopcode: Holds preopcode when atomic sequence is requested
136 * @opcodes: Opcodes which are supported. This are programmed by BIOS
137 * before it locks down the controller.
138 * @mem_ops: Pointer to SPI MEM ops supported by the controller
142 const struct intel_spi_boardinfo *info;
146 struct spi_controller *master;
154 const struct intel_spi_mem_op *mem_ops;
157 struct intel_spi_mem_op {
158 struct spi_mem_op mem_op;
160 int (*exec_op)(struct intel_spi *ispi,
161 const struct intel_spi_mem_op *iop,
162 const struct spi_mem_op *op);
165 static bool writeable;
166 module_param(writeable, bool, 0);
167 MODULE_PARM_DESC(writeable, "Enable write access to SPI flash chip (default=0)");
169 static void intel_spi_dump_regs(struct intel_spi *ispi)
174 dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG));
176 value = readl(ispi->base + HSFSTS_CTL);
177 dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value);
178 if (value & HSFSTS_CTL_FLOCKDN)
179 dev_dbg(ispi->dev, "-> Locked\n");
181 dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR));
182 dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK));
184 for (i = 0; i < 16; i++)
185 dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n",
186 i, readl(ispi->base + FDATA(i)));
188 dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC));
190 for (i = 0; i < ispi->nregions; i++)
191 dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i,
192 readl(ispi->base + FREG(i)));
193 for (i = 0; i < ispi->pr_num; i++)
194 dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i,
195 readl(ispi->pregs + PR(i)));
198 value = readl(ispi->sregs + SSFSTS_CTL);
199 dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value);
200 dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n",
201 readl(ispi->sregs + PREOP_OPTYPE));
202 dev_dbg(ispi->dev, "OPMENU0=0x%08x\n",
203 readl(ispi->sregs + OPMENU0));
204 dev_dbg(ispi->dev, "OPMENU1=0x%08x\n",
205 readl(ispi->sregs + OPMENU1));
208 dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC));
209 dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC));
211 dev_dbg(ispi->dev, "Protected regions:\n");
212 for (i = 0; i < ispi->pr_num; i++) {
215 value = readl(ispi->pregs + PR(i));
216 if (!(value & (PR_WPE | PR_RPE)))
219 limit = (value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
220 base = value & PR_BASE_MASK;
222 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n",
223 i, base << 12, (limit << 12) | 0xfff,
224 value & PR_WPE ? 'W' : '.', value & PR_RPE ? 'R' : '.');
227 dev_dbg(ispi->dev, "Flash regions:\n");
228 for (i = 0; i < ispi->nregions; i++) {
229 u32 region, base, limit;
231 region = readl(ispi->base + FREG(i));
232 base = region & FREG_BASE_MASK;
233 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
235 if (base >= limit || (i > 0 && limit == 0))
236 dev_dbg(ispi->dev, " %02d disabled\n", i);
238 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n",
239 i, base << 12, (limit << 12) | 0xfff);
242 dev_dbg(ispi->dev, "Using %cW sequencer for register access\n",
243 ispi->swseq_reg ? 'S' : 'H');
244 dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n",
245 ispi->swseq_erase ? 'S' : 'H');
248 /* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */
249 static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size)
254 if (size > INTEL_SPI_FIFO_SZ)
258 bytes = min_t(size_t, size, 4);
259 memcpy_fromio(buf, ispi->base + FDATA(i), bytes);
268 /* Writes max INTEL_SPI_FIFO_SZ bytes to the device fifo */
269 static int intel_spi_write_block(struct intel_spi *ispi, const void *buf,
275 if (size > INTEL_SPI_FIFO_SZ)
279 bytes = min_t(size_t, size, 4);
280 memcpy_toio(ispi->base + FDATA(i), buf, bytes);
289 static int intel_spi_wait_hw_busy(struct intel_spi *ispi)
293 return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,
294 !(val & HSFSTS_CTL_SCIP), 0,
295 INTEL_SPI_TIMEOUT * 1000);
298 static int intel_spi_wait_sw_busy(struct intel_spi *ispi)
302 return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,
303 !(val & SSFSTS_CTL_SCIP), 0,
304 INTEL_SPI_TIMEOUT * 1000);
307 static bool intel_spi_set_writeable(struct intel_spi *ispi)
309 if (!ispi->info->set_writeable)
312 return ispi->info->set_writeable(ispi->base, ispi->info->data);
315 static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype)
321 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++)
322 if (ispi->opcodes[i] == opcode)
328 /* The lock is off, so just use index 0 */
329 writel(opcode, ispi->sregs + OPMENU0);
330 preop = readw(ispi->sregs + PREOP_OPTYPE);
331 writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE);
336 static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, size_t len)
341 val = readl(ispi->base + HSFSTS_CTL);
342 val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK);
346 val |= HSFSTS_CTL_FCYCLE_RDID;
349 val |= HSFSTS_CTL_FCYCLE_WRSR;
352 val |= HSFSTS_CTL_FCYCLE_RDSR;
358 if (len > INTEL_SPI_FIFO_SZ)
361 val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT;
362 val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
363 val |= HSFSTS_CTL_FGO;
364 writel(val, ispi->base + HSFSTS_CTL);
366 ret = intel_spi_wait_hw_busy(ispi);
370 status = readl(ispi->base + HSFSTS_CTL);
371 if (status & HSFSTS_CTL_FCERR)
373 else if (status & HSFSTS_CTL_AEL)
379 static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, size_t len,
386 ret = intel_spi_opcode_index(ispi, opcode, optype);
390 if (len > INTEL_SPI_FIFO_SZ)
394 * Always clear it after each SW sequencer operation regardless
395 * of whether it is successful or not.
397 atomic_preopcode = ispi->atomic_preopcode;
398 ispi->atomic_preopcode = 0;
400 /* Only mark 'Data Cycle' bit when there is data to be transferred */
402 val = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS;
403 val |= ret << SSFSTS_CTL_COP_SHIFT;
404 val |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE;
405 val |= SSFSTS_CTL_SCGO;
406 if (atomic_preopcode) {
410 case OPTYPE_WRITE_NO_ADDR:
411 case OPTYPE_WRITE_WITH_ADDR:
412 /* Pick matching preopcode for the atomic sequence */
413 preop = readw(ispi->sregs + PREOP_OPTYPE);
414 if ((preop & 0xff) == atomic_preopcode)
416 else if ((preop >> 8) == atomic_preopcode)
417 val |= SSFSTS_CTL_SPOP;
421 /* Enable atomic sequence */
422 val |= SSFSTS_CTL_ACS;
429 writel(val, ispi->sregs + SSFSTS_CTL);
431 ret = intel_spi_wait_sw_busy(ispi);
435 status = readl(ispi->sregs + SSFSTS_CTL);
436 if (status & SSFSTS_CTL_FCERR)
438 else if (status & SSFSTS_CTL_AEL)
444 static int intel_spi_read_reg(struct intel_spi *ispi,
445 const struct intel_spi_mem_op *iop,
446 const struct spi_mem_op *op)
448 size_t nbytes = op->data.nbytes;
449 u8 opcode = op->cmd.opcode;
452 /* Address of the first chip */
453 writel(0, ispi->base + FADDR);
456 ret = intel_spi_sw_cycle(ispi, opcode, nbytes,
457 OPTYPE_READ_NO_ADDR);
459 ret = intel_spi_hw_cycle(ispi, opcode, nbytes);
464 return intel_spi_read_block(ispi, op->data.buf.in, nbytes);
467 static int intel_spi_write_reg(struct intel_spi *ispi,
468 const struct intel_spi_mem_op *iop,
469 const struct spi_mem_op *op)
471 size_t nbytes = op->data.nbytes;
472 u8 opcode = op->cmd.opcode;
476 * This is handled with atomic operation and preop code in Intel
477 * controller so we only verify that it is available. If the
478 * controller is not locked, program the opcode to the PREOP
479 * register for later use.
481 * When hardware sequencer is used there is no need to program
482 * any opcodes (it handles them automatically as part of a command).
484 if (opcode == SPINOR_OP_WREN) {
487 if (!ispi->swseq_reg)
490 preop = readw(ispi->sregs + PREOP_OPTYPE);
491 if ((preop & 0xff) != opcode && (preop >> 8) != opcode) {
494 writel(opcode, ispi->sregs + PREOP_OPTYPE);
498 * This enables atomic sequence on next SW sycle. Will
499 * be cleared after next operation.
501 ispi->atomic_preopcode = opcode;
506 * We hope that HW sequencer will do the right thing automatically and
507 * with the SW sequencer we cannot use preopcode anyway, so just ignore
508 * the Write Disable operation and pretend it was completed
511 if (opcode == SPINOR_OP_WRDI)
514 writel(0, ispi->base + FADDR);
516 /* Write the value beforehand */
517 ret = intel_spi_write_block(ispi, op->data.buf.out, nbytes);
522 return intel_spi_sw_cycle(ispi, opcode, nbytes,
523 OPTYPE_WRITE_NO_ADDR);
524 return intel_spi_hw_cycle(ispi, opcode, nbytes);
527 static int intel_spi_read(struct intel_spi *ispi,
528 const struct intel_spi_mem_op *iop,
529 const struct spi_mem_op *op)
531 void *read_buf = op->data.buf.in;
532 size_t block_size, nbytes = op->data.nbytes;
533 u32 addr = op->addr.val;
538 * Atomic sequence is not expected with HW sequencer reads. Make
539 * sure it is cleared regardless.
541 if (WARN_ON_ONCE(ispi->atomic_preopcode))
542 ispi->atomic_preopcode = 0;
545 block_size = min_t(size_t, nbytes, INTEL_SPI_FIFO_SZ);
547 /* Read cannot cross 4K boundary */
548 block_size = min_t(loff_t, addr + block_size,
549 round_up(addr + 1, SZ_4K)) - addr;
551 writel(addr, ispi->base + FADDR);
553 val = readl(ispi->base + HSFSTS_CTL);
554 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
555 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
556 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
557 val |= HSFSTS_CTL_FCYCLE_READ;
558 val |= HSFSTS_CTL_FGO;
559 writel(val, ispi->base + HSFSTS_CTL);
561 ret = intel_spi_wait_hw_busy(ispi);
565 status = readl(ispi->base + HSFSTS_CTL);
566 if (status & HSFSTS_CTL_FCERR)
568 else if (status & HSFSTS_CTL_AEL)
572 dev_err(ispi->dev, "read error: %x: %#x\n", addr, status);
576 ret = intel_spi_read_block(ispi, read_buf, block_size);
580 nbytes -= block_size;
582 read_buf += block_size;
588 static int intel_spi_write(struct intel_spi *ispi,
589 const struct intel_spi_mem_op *iop,
590 const struct spi_mem_op *op)
592 size_t block_size, nbytes = op->data.nbytes;
593 const void *write_buf = op->data.buf.out;
594 u32 addr = op->addr.val;
598 /* Not needed with HW sequencer write, make sure it is cleared */
599 ispi->atomic_preopcode = 0;
602 block_size = min_t(size_t, nbytes, INTEL_SPI_FIFO_SZ);
604 /* Write cannot cross 4K boundary */
605 block_size = min_t(loff_t, addr + block_size,
606 round_up(addr + 1, SZ_4K)) - addr;
608 writel(addr, ispi->base + FADDR);
610 val = readl(ispi->base + HSFSTS_CTL);
611 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
612 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
613 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
614 val |= HSFSTS_CTL_FCYCLE_WRITE;
616 ret = intel_spi_write_block(ispi, write_buf, block_size);
618 dev_err(ispi->dev, "failed to write block\n");
622 /* Start the write now */
623 val |= HSFSTS_CTL_FGO;
624 writel(val, ispi->base + HSFSTS_CTL);
626 ret = intel_spi_wait_hw_busy(ispi);
628 dev_err(ispi->dev, "timeout\n");
632 status = readl(ispi->base + HSFSTS_CTL);
633 if (status & HSFSTS_CTL_FCERR)
635 else if (status & HSFSTS_CTL_AEL)
639 dev_err(ispi->dev, "write error: %x: %#x\n", addr, status);
643 nbytes -= block_size;
645 write_buf += block_size;
651 static int intel_spi_erase(struct intel_spi *ispi,
652 const struct intel_spi_mem_op *iop,
653 const struct spi_mem_op *op)
655 u8 opcode = op->cmd.opcode;
656 u32 addr = op->addr.val;
660 writel(addr, ispi->base + FADDR);
662 if (ispi->swseq_erase)
663 return intel_spi_sw_cycle(ispi, opcode, 0,
664 OPTYPE_WRITE_WITH_ADDR);
666 /* Not needed with HW sequencer erase, make sure it is cleared */
667 ispi->atomic_preopcode = 0;
669 val = readl(ispi->base + HSFSTS_CTL);
670 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
671 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
672 val |= HSFSTS_CTL_FGO;
673 val |= iop->replacement_op;
674 writel(val, ispi->base + HSFSTS_CTL);
676 ret = intel_spi_wait_hw_busy(ispi);
680 status = readl(ispi->base + HSFSTS_CTL);
681 if (status & HSFSTS_CTL_FCERR)
683 if (status & HSFSTS_CTL_AEL)
689 static bool intel_spi_cmp_mem_op(const struct intel_spi_mem_op *iop,
690 const struct spi_mem_op *op)
692 if (iop->mem_op.cmd.nbytes != op->cmd.nbytes ||
693 iop->mem_op.cmd.buswidth != op->cmd.buswidth ||
694 iop->mem_op.cmd.dtr != op->cmd.dtr ||
695 iop->mem_op.cmd.opcode != op->cmd.opcode)
698 if (iop->mem_op.addr.nbytes != op->addr.nbytes ||
699 iop->mem_op.addr.dtr != op->addr.dtr)
702 if (iop->mem_op.data.dir != op->data.dir ||
703 iop->mem_op.data.dtr != op->data.dtr)
706 if (iop->mem_op.data.dir != SPI_MEM_NO_DATA) {
707 if (iop->mem_op.data.buswidth != op->data.buswidth)
714 static const struct intel_spi_mem_op *
715 intel_spi_match_mem_op(struct intel_spi *ispi, const struct spi_mem_op *op)
717 const struct intel_spi_mem_op *iop;
719 for (iop = ispi->mem_ops; iop->mem_op.cmd.opcode; iop++) {
720 if (intel_spi_cmp_mem_op(iop, op))
724 return iop->mem_op.cmd.opcode ? iop : NULL;
727 static bool intel_spi_supports_mem_op(struct spi_mem *mem,
728 const struct spi_mem_op *op)
730 struct intel_spi *ispi = spi_master_get_devdata(mem->spi->master);
731 const struct intel_spi_mem_op *iop;
733 iop = intel_spi_match_mem_op(ispi, op);
735 dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode);
740 * For software sequencer check that the opcode is actually
741 * present in the opmenu if it is locked.
743 if (ispi->swseq_reg && ispi->locked) {
746 /* Check if it is in the locked opcodes list */
747 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++) {
748 if (ispi->opcodes[i] == op->cmd.opcode)
752 dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode);
759 static int intel_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
761 struct intel_spi *ispi = spi_master_get_devdata(mem->spi->master);
762 const struct intel_spi_mem_op *iop;
764 iop = intel_spi_match_mem_op(ispi, op);
768 return iop->exec_op(ispi, iop, op);
771 static const char *intel_spi_get_name(struct spi_mem *mem)
773 const struct intel_spi *ispi = spi_master_get_devdata(mem->spi->master);
776 * Return name of the flash controller device to be compatible
777 * with the MTD version.
779 return dev_name(ispi->dev);
782 static const struct spi_controller_mem_ops intel_spi_mem_ops = {
783 .supports_op = intel_spi_supports_mem_op,
784 .exec_op = intel_spi_exec_mem_op,
785 .get_name = intel_spi_get_name,
788 #define INTEL_SPI_OP_ADDR(__nbytes) \
790 .nbytes = __nbytes, \
793 #define INTEL_SPI_OP_NO_DATA \
795 .dir = SPI_MEM_NO_DATA, \
798 #define INTEL_SPI_OP_DATA_IN(__buswidth) \
800 .dir = SPI_MEM_DATA_IN, \
801 .buswidth = __buswidth, \
804 #define INTEL_SPI_OP_DATA_OUT(__buswidth) \
806 .dir = SPI_MEM_DATA_OUT, \
807 .buswidth = __buswidth, \
810 #define INTEL_SPI_MEM_OP(__cmd, __addr, __data, __exec_op) \
817 .exec_op = __exec_op, \
820 #define INTEL_SPI_MEM_OP_REPL(__cmd, __addr, __data, __exec_op, __repl) \
827 .exec_op = __exec_op, \
828 .replacement_op = __repl, \
832 * The controller handles pretty much everything internally based on the
833 * SFDP data but we want to make sure we only support the operations
834 * actually possible. Only check buswidth and transfer direction, the
835 * core validates data.
837 #define INTEL_SPI_GENERIC_OPS \
838 /* Status register operations */ \
839 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), \
840 SPI_MEM_OP_NO_ADDR, \
841 INTEL_SPI_OP_DATA_IN(1), \
842 intel_spi_read_reg), \
843 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1), \
844 SPI_MEM_OP_NO_ADDR, \
845 INTEL_SPI_OP_DATA_IN(1), \
846 intel_spi_read_reg), \
847 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1), \
848 SPI_MEM_OP_NO_ADDR, \
849 INTEL_SPI_OP_DATA_OUT(1), \
850 intel_spi_write_reg), \
852 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \
853 INTEL_SPI_OP_ADDR(3), \
854 INTEL_SPI_OP_DATA_IN(1), \
856 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \
857 INTEL_SPI_OP_ADDR(3), \
858 INTEL_SPI_OP_DATA_IN(2), \
860 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \
861 INTEL_SPI_OP_ADDR(3), \
862 INTEL_SPI_OP_DATA_IN(4), \
864 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \
865 INTEL_SPI_OP_ADDR(4), \
866 INTEL_SPI_OP_DATA_IN(1), \
868 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \
869 INTEL_SPI_OP_ADDR(4), \
870 INTEL_SPI_OP_DATA_IN(2), \
872 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \
873 INTEL_SPI_OP_ADDR(4), \
874 INTEL_SPI_OP_DATA_IN(4), \
877 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \
878 INTEL_SPI_OP_ADDR(3), \
879 INTEL_SPI_OP_DATA_IN(1), \
881 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \
882 INTEL_SPI_OP_ADDR(3), \
883 INTEL_SPI_OP_DATA_IN(2), \
885 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \
886 INTEL_SPI_OP_ADDR(3), \
887 INTEL_SPI_OP_DATA_IN(4), \
889 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \
890 INTEL_SPI_OP_ADDR(4), \
891 INTEL_SPI_OP_DATA_IN(1), \
893 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \
894 INTEL_SPI_OP_ADDR(4), \
895 INTEL_SPI_OP_DATA_IN(2), \
897 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \
898 INTEL_SPI_OP_ADDR(4), \
899 INTEL_SPI_OP_DATA_IN(4), \
901 /* Read with 4-byte address opcode */ \
902 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_4B, 1), \
903 INTEL_SPI_OP_ADDR(4), \
904 INTEL_SPI_OP_DATA_IN(1), \
906 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_4B, 1), \
907 INTEL_SPI_OP_ADDR(4), \
908 INTEL_SPI_OP_DATA_IN(2), \
910 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_4B, 1), \
911 INTEL_SPI_OP_ADDR(4), \
912 INTEL_SPI_OP_DATA_IN(4), \
914 /* Fast read with 4-byte address opcode */ \
915 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST_4B, 1), \
916 INTEL_SPI_OP_ADDR(4), \
917 INTEL_SPI_OP_DATA_IN(1), \
919 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST_4B, 1), \
920 INTEL_SPI_OP_ADDR(4), \
921 INTEL_SPI_OP_DATA_IN(2), \
923 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST_4B, 1), \
924 INTEL_SPI_OP_ADDR(4), \
925 INTEL_SPI_OP_DATA_IN(4), \
927 /* Write operations */ \
928 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_PP, 1), \
929 INTEL_SPI_OP_ADDR(3), \
930 INTEL_SPI_OP_DATA_OUT(1), \
932 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_PP, 1), \
933 INTEL_SPI_OP_ADDR(4), \
934 INTEL_SPI_OP_DATA_OUT(1), \
936 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_PP_4B, 1), \
937 INTEL_SPI_OP_ADDR(4), \
938 INTEL_SPI_OP_DATA_OUT(1), \
940 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 1), \
941 SPI_MEM_OP_NO_ADDR, \
942 SPI_MEM_OP_NO_DATA, \
943 intel_spi_write_reg), \
944 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 1), \
945 SPI_MEM_OP_NO_ADDR, \
946 SPI_MEM_OP_NO_DATA, \
947 intel_spi_write_reg), \
948 /* Erase operations */ \
949 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_BE_4K, 1), \
950 INTEL_SPI_OP_ADDR(3), \
951 SPI_MEM_OP_NO_DATA, \
953 HSFSTS_CTL_FCYCLE_ERASE), \
954 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_BE_4K, 1), \
955 INTEL_SPI_OP_ADDR(4), \
956 SPI_MEM_OP_NO_DATA, \
958 HSFSTS_CTL_FCYCLE_ERASE), \
959 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_BE_4K_4B, 1), \
960 INTEL_SPI_OP_ADDR(4), \
961 SPI_MEM_OP_NO_DATA, \
963 HSFSTS_CTL_FCYCLE_ERASE) \
965 static const struct intel_spi_mem_op generic_mem_ops[] = {
966 INTEL_SPI_GENERIC_OPS,
970 static const struct intel_spi_mem_op erase_64k_mem_ops[] = {
971 INTEL_SPI_GENERIC_OPS,
972 /* 64k sector erase operations */
973 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_SE, 1),
974 INTEL_SPI_OP_ADDR(3),
977 HSFSTS_CTL_FCYCLE_ERASE_64K),
978 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_SE, 1),
979 INTEL_SPI_OP_ADDR(4),
982 HSFSTS_CTL_FCYCLE_ERASE_64K),
983 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_SE_4B, 1),
984 INTEL_SPI_OP_ADDR(4),
987 HSFSTS_CTL_FCYCLE_ERASE_64K),
991 static int intel_spi_init(struct intel_spi *ispi)
993 u32 opmenu0, opmenu1, lvscc, uvscc, val;
994 bool erase_64k = false;
997 switch (ispi->info->type) {
999 ispi->sregs = ispi->base + BYT_SSFSTS_CTL;
1000 ispi->pregs = ispi->base + BYT_PR;
1001 ispi->nregions = BYT_FREG_NUM;
1002 ispi->pr_num = BYT_PR_NUM;
1003 ispi->swseq_reg = true;
1007 ispi->sregs = ispi->base + LPT_SSFSTS_CTL;
1008 ispi->pregs = ispi->base + LPT_PR;
1009 ispi->nregions = LPT_FREG_NUM;
1010 ispi->pr_num = LPT_PR_NUM;
1011 ispi->swseq_reg = true;
1015 ispi->sregs = ispi->base + BXT_SSFSTS_CTL;
1016 ispi->pregs = ispi->base + BXT_PR;
1017 ispi->nregions = BXT_FREG_NUM;
1018 ispi->pr_num = BXT_PR_NUM;
1024 ispi->pregs = ispi->base + CNL_PR;
1025 ispi->nregions = CNL_FREG_NUM;
1026 ispi->pr_num = CNL_PR_NUM;
1033 /* Try to disable write protection if user asked to do so */
1034 if (writeable && !intel_spi_set_writeable(ispi)) {
1035 dev_warn(ispi->dev, "can't disable chip write protection\n");
1039 /* Disable #SMI generation from HW sequencer */
1040 val = readl(ispi->base + HSFSTS_CTL);
1041 val &= ~HSFSTS_CTL_FSMIE;
1042 writel(val, ispi->base + HSFSTS_CTL);
1045 * Determine whether erase operation should use HW or SW sequencer.
1047 * The HW sequencer has a predefined list of opcodes, with only the
1048 * erase opcode being programmable in LVSCC and UVSCC registers.
1049 * If these registers don't contain a valid erase opcode, erase
1050 * cannot be done using HW sequencer.
1052 lvscc = readl(ispi->base + LVSCC);
1053 uvscc = readl(ispi->base + UVSCC);
1054 if (!(lvscc & ERASE_OPCODE_MASK) || !(uvscc & ERASE_OPCODE_MASK))
1055 ispi->swseq_erase = true;
1056 /* SPI controller on Intel BXT supports 64K erase opcode */
1057 if (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase)
1058 if (!(lvscc & ERASE_64K_OPCODE_MASK) ||
1059 !(uvscc & ERASE_64K_OPCODE_MASK))
1062 if (!ispi->sregs && (ispi->swseq_reg || ispi->swseq_erase)) {
1063 dev_err(ispi->dev, "software sequencer not supported, but required\n");
1068 * Some controllers can only do basic operations using hardware
1069 * sequencer. All other operations are supposed to be carried out
1070 * using software sequencer.
1072 if (ispi->swseq_reg) {
1073 /* Disable #SMI generation from SW sequencer */
1074 val = readl(ispi->sregs + SSFSTS_CTL);
1075 val &= ~SSFSTS_CTL_FSMIE;
1076 writel(val, ispi->sregs + SSFSTS_CTL);
1079 /* Check controller's lock status */
1080 val = readl(ispi->base + HSFSTS_CTL);
1081 ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN);
1083 if (ispi->locked && ispi->sregs) {
1085 * BIOS programs allowed opcodes and then locks down the
1086 * register. So read back what opcodes it decided to support.
1087 * That's the set we are going to support as well.
1089 opmenu0 = readl(ispi->sregs + OPMENU0);
1090 opmenu1 = readl(ispi->sregs + OPMENU1);
1092 if (opmenu0 && opmenu1) {
1093 for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {
1094 ispi->opcodes[i] = opmenu0 >> i * 8;
1095 ispi->opcodes[i + 4] = opmenu1 >> i * 8;
1101 dev_dbg(ispi->dev, "Using erase_64k memory operations");
1102 ispi->mem_ops = erase_64k_mem_ops;
1104 dev_dbg(ispi->dev, "Using generic memory operations");
1105 ispi->mem_ops = generic_mem_ops;
1108 intel_spi_dump_regs(ispi);
1112 static bool intel_spi_is_protected(const struct intel_spi *ispi,
1113 unsigned int base, unsigned int limit)
1117 for (i = 0; i < ispi->pr_num; i++) {
1118 u32 pr_base, pr_limit, pr_value;
1120 pr_value = readl(ispi->pregs + PR(i));
1121 if (!(pr_value & (PR_WPE | PR_RPE)))
1124 pr_limit = (pr_value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
1125 pr_base = pr_value & PR_BASE_MASK;
1127 if (pr_base >= base && pr_limit <= limit)
1135 * There will be a single partition holding all enabled flash regions. We
1138 static void intel_spi_fill_partition(struct intel_spi *ispi,
1139 struct mtd_partition *part)
1144 memset(part, 0, sizeof(*part));
1146 /* Start from the mandatory descriptor region */
1148 part->name = "BIOS";
1151 * Now try to find where this partition ends based on the flash
1154 for (i = 1; i < ispi->nregions; i++) {
1155 u32 region, base, limit;
1157 region = readl(ispi->base + FREG(i));
1158 base = region & FREG_BASE_MASK;
1159 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
1161 if (base >= limit || limit == 0)
1165 * If any of the regions have protection bits set, make the
1166 * whole partition read-only to be on the safe side.
1168 * Also if the user did not ask the chip to be writeable
1171 if (!writeable || intel_spi_is_protected(ispi, base, limit))
1172 part->mask_flags |= MTD_WRITEABLE;
1174 end = (limit << 12) + 4096;
1175 if (end > part->size)
1180 static int intel_spi_populate_chip(struct intel_spi *ispi)
1182 struct flash_platform_data *pdata;
1183 struct spi_board_info chip;
1185 pdata = devm_kzalloc(ispi->dev, sizeof(*pdata), GFP_KERNEL);
1189 pdata->nr_parts = 1;
1190 pdata->parts = devm_kcalloc(ispi->dev, sizeof(*pdata->parts),
1191 pdata->nr_parts, GFP_KERNEL);
1195 intel_spi_fill_partition(ispi, pdata->parts);
1197 memset(&chip, 0, sizeof(chip));
1198 snprintf(chip.modalias, 8, "spi-nor");
1199 chip.platform_data = pdata;
1201 return spi_new_device(ispi->master, &chip) ? 0 : -ENODEV;
1205 * intel_spi_probe() - Probe the Intel SPI flash controller
1206 * @dev: Pointer to the parent device
1207 * @mem: MMIO resource
1208 * @info: Platform spefific information
1210 * Probes Intel SPI flash controller and creates the flash chip device.
1211 * Returns %0 on success and negative errno in case of failure.
1213 int intel_spi_probe(struct device *dev, struct resource *mem,
1214 const struct intel_spi_boardinfo *info)
1216 struct spi_controller *master;
1217 struct intel_spi *ispi;
1220 master = devm_spi_alloc_master(dev, sizeof(*ispi));
1224 master->mem_ops = &intel_spi_mem_ops;
1226 ispi = spi_master_get_devdata(master);
1228 ispi->base = devm_ioremap_resource(dev, mem);
1229 if (IS_ERR(ispi->base))
1230 return PTR_ERR(ispi->base);
1233 ispi->master = master;
1236 ret = intel_spi_init(ispi);
1240 ret = devm_spi_register_master(dev, master);
1244 return intel_spi_populate_chip(ispi);
1246 EXPORT_SYMBOL_GPL(intel_spi_probe);
1248 MODULE_DESCRIPTION("Intel PCH/PCU SPI flash core driver");
1249 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1250 MODULE_LICENSE("GPL v2");