drivers/spi/spi-fsl-spi.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Freescale SPI controller driver.
   4  *
   5  * Maintainer: Kumar Gala
   6  *
   7  * Copyright (C) 2006 Polycom, Inc.
   8  * Copyright 2010 Freescale Semiconductor, Inc.
   9  *
  10  * CPM SPI and QE buffer descriptors mode support:
  11  * Copyright (c) 2009  MontaVista Software, Inc.
  12  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  13  *
  14  * GRLIB support:
  15  * Copyright (c) 2012 Aeroflex Gaisler AB.
  16  * Author: Andreas Larsson <andreas@gaisler.com>
  17  */
  18 #include <linux/delay.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/fsl_devices.h>
  21 #include <linux/gpio/consumer.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/module.h>
  27 #include <linux/mutex.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/spi/spi.h>
  34 #include <linux/spi/spi_bitbang.h>
  35 #include <linux/types.h>
  36
  37 #ifdef CONFIG_FSL_SOC
  38 #include <sysdev/fsl_soc.h>
  39 #endif
  40
  41 /* Specific to the MPC8306/MPC8309 */
  42 #define IMMR_SPI_CS_OFFSET 0x14c
  43 #define SPI_BOOT_SEL_BIT   0x80000000
  44
  45 #include "spi-fsl-lib.h"
  46 #include "spi-fsl-cpm.h"
  47 #include "spi-fsl-spi.h"
  48
  49 #define TYPE_FSL        0
  50 #define TYPE_GRLIB      1
  51
  52 struct fsl_spi_match_data {
  53         int type;
  54 };
  55
  56 static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
  57         .type = TYPE_FSL,
  58 };
  59
  60 static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
  61         .type = TYPE_GRLIB,
  62 };
  63
  64 static const struct of_device_id of_fsl_spi_match[] = {
  65         {
  66                 .compatible = "fsl,spi",
  67                 .data = &of_fsl_spi_fsl_config,
  68         },
  69         {
  70                 .compatible = "aeroflexgaisler,spictrl",
  71                 .data = &of_fsl_spi_grlib_config,
  72         },
  73         {}
  74 };
  75 MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
  76
  77 static int fsl_spi_get_type(struct device *dev)
  78 {
  79         const struct of_device_id *match;
  80
  81         if (dev->of_node) {
  82                 match = of_match_node(of_fsl_spi_match, dev->of_node);
  83                 if (match && match->data)
  84                         return ((struct fsl_spi_match_data *)match->data)->type;
  85         }
  86         return TYPE_FSL;
  87 }
  88
  89 static void fsl_spi_change_mode(struct spi_device *spi)
  90 {
  91         struct mpc8xxx_spi *mspi = spi_controller_get_devdata(spi->controller);
  92         struct spi_mpc8xxx_cs *cs = spi->controller_state;
  93         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
  94         __be32 __iomem *mode = &reg_base->mode;
  95         unsigned long flags;
  96
  97         if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
  98                 return;
  99
 100         /* Turn off IRQs locally to minimize time that SPI is disabled. */
 101         local_irq_save(flags);
 102
 103         /* Turn off SPI unit prior changing mode */
 104         mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
 105
 106         /* When in CPM mode, we need to reinit tx and rx. */
 107         if (mspi->flags & SPI_CPM_MODE) {
 108                 fsl_spi_cpm_reinit_txrx(mspi);
 109         }
 110         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
 111         local_irq_restore(flags);
 112 }
 113
 114 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
 115                                       int bits_per_word, int msb_first)
 116 {
 117         *rx_shift = 0;
 118         *tx_shift = 0;
 119         if (msb_first) {
 120                 if (bits_per_word <= 8) {
 121                         *rx_shift = 16;
 122                         *tx_shift = 24;
 123                 } else if (bits_per_word <= 16) {
 124                         *rx_shift = 16;
 125                         *tx_shift = 16;
 126                 }
 127         } else {
 128                 if (bits_per_word <= 8)
 129                         *rx_shift = 8;
 130         }
 131 }
 132
 133 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
 134                                      int bits_per_word, int msb_first)
 135 {
 136         *rx_shift = 0;
 137         *tx_shift = 0;
 138         if (bits_per_word <= 16) {
 139                 if (msb_first) {
 140                         *rx_shift = 16; /* LSB in bit 16 */
 141                         *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
 142                 } else {
 143                         *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
 144                 }
 145         }
 146 }
 147
 148 static void mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
 149                                        struct spi_device *spi,
 150                                        struct mpc8xxx_spi *mpc8xxx_spi,
 151                                        int bits_per_word)
 152 {
 153         cs->rx_shift = 0;
 154         cs->tx_shift = 0;
 155         if (bits_per_word <= 8) {
 156                 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
 157                 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
 158         } else if (bits_per_word <= 16) {
 159                 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
 160                 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
 161         } else if (bits_per_word <= 32) {
 162                 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
 163                 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
 164         }
 165
 166         if (mpc8xxx_spi->set_shifts)
 167                 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
 168                                         bits_per_word,
 169                                         !(spi->mode & SPI_LSB_FIRST));
 170
 171         mpc8xxx_spi->rx_shift = cs->rx_shift;
 172         mpc8xxx_spi->tx_shift = cs->tx_shift;
 173         mpc8xxx_spi->get_rx = cs->get_rx;
 174         mpc8xxx_spi->get_tx = cs->get_tx;
 175 }
 176
 177 static int fsl_spi_setup_transfer(struct spi_device *spi,
 178                                         struct spi_transfer *t)
 179 {
 180         struct mpc8xxx_spi *mpc8xxx_spi;
 181         int bits_per_word = 0;
 182         u8 pm;
 183         u32 hz = 0;
 184         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 185
 186         mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
 187
 188         if (t) {
 189                 bits_per_word = t->bits_per_word;
 190                 hz = t->speed_hz;
 191         }
 192
 193         /* spi_transfer level calls that work per-word */
 194         if (!bits_per_word)
 195                 bits_per_word = spi->bits_per_word;
 196
 197         if (!hz)
 198                 hz = spi->max_speed_hz;
 199
 200         if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
 201                 mspi_apply_cpu_mode_quirks(cs, spi, mpc8xxx_spi, bits_per_word);
 202
 203         if (bits_per_word == 32)
 204                 bits_per_word = 0;
 205         else
 206                 bits_per_word = bits_per_word - 1;
 207
 208         /* mask out bits we are going to set */
 209         cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
 210                                   | SPMODE_PM(0xF));
 211
 212         cs->hw_mode |= SPMODE_LEN(bits_per_word);
 213
 214         if ((mpc8xxx_spi->spibrg / hz) > 64) {
 215                 cs->hw_mode |= SPMODE_DIV16;
 216                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
 217                 WARN_ONCE(pm > 16,
 218                           "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n",
 219                           dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);
 220                 if (pm > 16)
 221                         pm = 16;
 222         } else {
 223                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
 224         }
 225         if (pm)
 226                 pm--;
 227
 228         cs->hw_mode |= SPMODE_PM(pm);
 229
 230         fsl_spi_change_mode(spi);
 231         return 0;
 232 }
 233
 234 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
 235                                 struct spi_transfer *t, unsigned int len)
 236 {
 237         u32 word;
 238         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
 239
 240         mspi->count = len;
 241
 242         /* enable rx ints */
 243         mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
 244
 245         /* transmit word */
 246         word = mspi->get_tx(mspi);
 247         mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 248
 249         return 0;
 250 }
 251
 252 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
 253                             bool is_dma_mapped)
 254 {
 255         struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
 256         struct fsl_spi_reg __iomem *reg_base;
 257         unsigned int len = t->len;
 258         u8 bits_per_word;
 259         int ret;
 260
 261         reg_base = mpc8xxx_spi->reg_base;
 262         bits_per_word = spi->bits_per_word;
 263         if (t->bits_per_word)
 264                 bits_per_word = t->bits_per_word;
 265
 266         if (bits_per_word > 8)
 267                 len /= 2;
 268         if (bits_per_word > 16)
 269                 len /= 2;
 270
 271         mpc8xxx_spi->tx = t->tx_buf;
 272         mpc8xxx_spi->rx = t->rx_buf;
 273
 274         reinit_completion(&mpc8xxx_spi->done);
 275
 276         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 277                 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
 278         else
 279                 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
 280         if (ret)
 281                 return ret;
 282
 283         wait_for_completion(&mpc8xxx_spi->done);
 284
 285         /* disable rx ints */
 286         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 287
 288         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 289                 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
 290
 291         return mpc8xxx_spi->count;
 292 }
 293
 294 static int fsl_spi_prepare_message(struct spi_controller *ctlr,
 295                                    struct spi_message *m)
 296 {
 297         struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(ctlr);
 298         struct spi_transfer *t;
 299         struct spi_transfer *first;
 300
 301         first = list_first_entry(&m->transfers, struct spi_transfer,
 302                                  transfer_list);
 303
 304         /*
 305          * In CPU mode, optimize large byte transfers to use larger
 306          * bits_per_word values to reduce number of interrupts taken.
 307          *
 308          * Some glitches can appear on the SPI clock when the mode changes.
 309          * Check that there is no speed change during the transfer and set it up
 310          * now to change the mode without having a chip-select asserted.
 311          */
 312         list_for_each_entry(t, &m->transfers, transfer_list) {
 313                 if (t->speed_hz != first->speed_hz) {
 314                         dev_err(&m->spi->dev,
 315                                 "speed_hz cannot change during message.\n");
 316                         return -EINVAL;
 317                 }
 318                 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
 319                         if (t->len < 256 || t->bits_per_word != 8)
 320                                 continue;
 321                         if ((t->len & 3) == 0)
 322                                 t->bits_per_word = 32;
 323                         else if ((t->len & 1) == 0)
 324                                 t->bits_per_word = 16;
 325                 } else {
 326                         /*
 327                          * CPM/QE uses Little Endian for words > 8
 328                          * so transform 16 and 32 bits words into 8 bits
 329                          * Unfortnatly that doesn't work for LSB so
 330                          * reject these for now
 331                          * Note: 32 bits word, LSB works iff
 332                          * tfcr/rfcr is set to CPMFCR_GBL
 333                          */
 334                         if (m->spi->mode & SPI_LSB_FIRST && t->bits_per_word > 8)
 335                                 return -EINVAL;
 336                         if (t->bits_per_word == 16 || t->bits_per_word == 32)
 337                                 t->bits_per_word = 8; /* pretend its 8 bits */
 338                         if (t->bits_per_word == 8 && t->len >= 256 &&
 339                             (mpc8xxx_spi->flags & SPI_CPM1))
 340                                 t->bits_per_word = 16;
 341                 }
 342         }
 343         return fsl_spi_setup_transfer(m->spi, first);
 344 }
 345
 346 static int fsl_spi_transfer_one(struct spi_controller *controller,
 347                                 struct spi_device *spi,
 348                                 struct spi_transfer *t)
 349 {
 350         int status;
 351
 352         status = fsl_spi_setup_transfer(spi, t);
 353         if (status < 0)
 354                 return status;
 355         if (t->len)
 356                 status = fsl_spi_bufs(spi, t, !!t->tx_dma || !!t->rx_dma);
 357         if (status > 0)
 358                 return -EMSGSIZE;
 359
 360         return status;
 361 }
 362
 363 static int fsl_spi_unprepare_message(struct spi_controller *controller,
 364                                      struct spi_message *msg)
 365 {
 366         return fsl_spi_setup_transfer(msg->spi, NULL);
 367 }
 368
 369 static int fsl_spi_setup(struct spi_device *spi)
 370 {
 371         struct mpc8xxx_spi *mpc8xxx_spi;
 372         struct fsl_spi_reg __iomem *reg_base;
 373         bool initial_setup = false;
 374         int retval;
 375         u32 hw_mode;
 376         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 377
 378         if (!spi->max_speed_hz)
 379                 return -EINVAL;
 380
 381         if (!cs) {
 382                 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 383                 if (!cs)
 384                         return -ENOMEM;
 385                 spi_set_ctldata(spi, cs);
 386                 initial_setup = true;
 387         }
 388         mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
 389
 390         reg_base = mpc8xxx_spi->reg_base;
 391
 392         hw_mode = cs->hw_mode; /* Save original settings */
 393         cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
 394         /* mask out bits we are going to set */
 395         cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
 396                          | SPMODE_REV | SPMODE_LOOP);
 397
 398         if (spi->mode & SPI_CPHA)
 399                 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
 400         if (spi->mode & SPI_CPOL)
 401                 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
 402         if (!(spi->mode & SPI_LSB_FIRST))
 403                 cs->hw_mode |= SPMODE_REV;
 404         if (spi->mode & SPI_LOOP)
 405                 cs->hw_mode |= SPMODE_LOOP;
 406
 407         retval = fsl_spi_setup_transfer(spi, NULL);
 408         if (retval < 0) {
 409                 cs->hw_mode = hw_mode; /* Restore settings */
 410                 if (initial_setup)
 411                         kfree(cs);
 412                 return retval;
 413         }
 414
 415         return 0;
 416 }
 417
 418 static void fsl_spi_cleanup(struct spi_device *spi)
 419 {
 420         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 421
 422         kfree(cs);
 423         spi_set_ctldata(spi, NULL);
 424 }
 425
 426 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
 427 {
 428         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
 429
 430         /* We need handle RX first */
 431         if (events & SPIE_NE) {
 432                 u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
 433
 434                 if (mspi->rx)
 435                         mspi->get_rx(rx_data, mspi);
 436         }
 437
 438         if ((events & SPIE_NF) == 0)
 439                 /* spin until TX is done */
 440                 while (((events =
 441                         mpc8xxx_spi_read_reg(&reg_base->event)) &
 442                                                 SPIE_NF) == 0)
 443                         cpu_relax();
 444
 445         /* Clear the events */
 446         mpc8xxx_spi_write_reg(&reg_base->event, events);
 447
 448         mspi->count -= 1;
 449         if (mspi->count) {
 450                 u32 word = mspi->get_tx(mspi);
 451
 452                 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 453         } else {
 454                 complete(&mspi->done);
 455         }
 456 }
 457
 458 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
 459 {
 460         struct mpc8xxx_spi *mspi = context_data;
 461         irqreturn_t ret = IRQ_NONE;
 462         u32 events;
 463         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
 464
 465         /* Get interrupt events(tx/rx) */
 466         events = mpc8xxx_spi_read_reg(&reg_base->event);
 467         if (events)
 468                 ret = IRQ_HANDLED;
 469
 470         dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
 471
 472         if (mspi->flags & SPI_CPM_MODE)
 473                 fsl_spi_cpm_irq(mspi, events);
 474         else
 475                 fsl_spi_cpu_irq(mspi, events);
 476
 477         return ret;
 478 }
 479
 480 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
 481 {
 482         struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
 483         struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
 484         u32 slvsel;
 485         u16 cs = spi_get_chipselect(spi, 0);
 486
 487         if (cs < mpc8xxx_spi->native_chipselects) {
 488                 slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
 489                 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
 490                 mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
 491         }
 492 }
 493
 494 static void fsl_spi_grlib_probe(struct device *dev)
 495 {
 496         struct spi_controller *host = dev_get_drvdata(dev);
 497         struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(host);
 498         struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
 499         int mbits;
 500         u32 capabilities;
 501
 502         capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
 503
 504         mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
 505         mbits = SPCAP_MAXWLEN(capabilities);
 506         if (mbits)
 507                 mpc8xxx_spi->max_bits_per_word = mbits + 1;
 508
 509         mpc8xxx_spi->native_chipselects = 0;
 510         if (SPCAP_SSEN(capabilities)) {
 511                 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
 512                 mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
 513         }
 514         host->num_chipselect = mpc8xxx_spi->native_chipselects;
 515         host->set_cs = fsl_spi_grlib_cs_control;
 516 }
 517
 518 static void fsl_spi_cs_control(struct spi_device *spi, bool on)
 519 {
 520         struct device *dev = spi->dev.parent->parent;
 521         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 522         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 523
 524         if (WARN_ON_ONCE(!pinfo->immr_spi_cs))
 525                 return;
 526         iowrite32be(on ? 0 : SPI_BOOT_SEL_BIT, pinfo->immr_spi_cs);
 527 }
 528
 529 static struct spi_controller *fsl_spi_probe(struct device *dev,
 530                 struct resource *mem, unsigned int irq)
 531 {
 532         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 533         struct spi_controller *host;
 534         struct mpc8xxx_spi *mpc8xxx_spi;
 535         struct fsl_spi_reg __iomem *reg_base;
 536         u32 regval;
 537         int ret = 0;
 538
 539         host = spi_alloc_host(dev, sizeof(struct mpc8xxx_spi));
 540         if (host == NULL) {
 541                 ret = -ENOMEM;
 542                 goto err;
 543         }
 544
 545         dev_set_drvdata(dev, host);
 546
 547         mpc8xxx_spi_probe(dev, mem, irq);
 548
 549         host->setup = fsl_spi_setup;
 550         host->cleanup = fsl_spi_cleanup;
 551         host->prepare_message = fsl_spi_prepare_message;
 552         host->transfer_one = fsl_spi_transfer_one;
 553         host->unprepare_message = fsl_spi_unprepare_message;
 554         host->use_gpio_descriptors = true;
 555         host->set_cs = fsl_spi_cs_control;
 556
 557         mpc8xxx_spi = spi_controller_get_devdata(host);
 558         mpc8xxx_spi->max_bits_per_word = 32;
 559         mpc8xxx_spi->type = fsl_spi_get_type(dev);
 560
 561         ret = fsl_spi_cpm_init(mpc8xxx_spi);
 562         if (ret)
 563                 goto err_cpm_init;
 564
 565         mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
 566         if (IS_ERR(mpc8xxx_spi->reg_base)) {
 567                 ret = PTR_ERR(mpc8xxx_spi->reg_base);
 568                 goto err_probe;
 569         }
 570
 571         if (mpc8xxx_spi->type == TYPE_GRLIB)
 572                 fsl_spi_grlib_probe(dev);
 573
 574         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 575                 host->bits_per_word_mask =
 576                         (SPI_BPW_RANGE_MASK(4, 8) | SPI_BPW_MASK(16) | SPI_BPW_MASK(32));
 577         else
 578                 host->bits_per_word_mask =
 579                         (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32));
 580
 581         host->bits_per_word_mask &=
 582                 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
 583
 584         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 585                 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
 586
 587         if (mpc8xxx_spi->set_shifts)
 588                 /* 8 bits per word and MSB first */
 589                 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
 590                                         &mpc8xxx_spi->tx_shift, 8, 1);
 591
 592         /* Register for SPI Interrupt */
 593         ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
 594                                0, "fsl_spi", mpc8xxx_spi);
 595
 596         if (ret != 0)
 597                 goto err_probe;
 598
 599         reg_base = mpc8xxx_spi->reg_base;
 600
 601         /* SPI controller initializations */
 602         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
 603         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 604         mpc8xxx_spi_write_reg(&reg_base->command, 0);
 605         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
 606
 607         /* Enable SPI interface */
 608         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 609         if (mpc8xxx_spi->max_bits_per_word < 8) {
 610                 regval &= ~SPMODE_LEN(0xF);
 611                 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
 612         }
 613         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 614                 regval |= SPMODE_OP;
 615
 616         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 617
 618         ret = devm_spi_register_controller(dev, host);
 619         if (ret < 0)
 620                 goto err_probe;
 621
 622         dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
 623                  mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
 624
 625         return host;
 626
 627 err_probe:
 628         fsl_spi_cpm_free(mpc8xxx_spi);
 629 err_cpm_init:
 630         spi_controller_put(host);
 631 err:
 632         return ERR_PTR(ret);
 633 }
 634
 635 static int of_fsl_spi_probe(struct platform_device *ofdev)
 636 {
 637         struct device *dev = &ofdev->dev;
 638         struct device_node *np = ofdev->dev.of_node;
 639         struct spi_controller *host;
 640         struct resource mem;
 641         int irq, type;
 642         int ret;
 643         bool spisel_boot = false;
 644 #if IS_ENABLED(CONFIG_FSL_SOC)
 645         struct mpc8xxx_spi_probe_info *pinfo = NULL;
 646 #endif
 647
 648
 649         ret = of_mpc8xxx_spi_probe(ofdev);
 650         if (ret)
 651                 return ret;
 652
 653         type = fsl_spi_get_type(&ofdev->dev);
 654         if (type == TYPE_FSL) {
 655                 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 656 #if IS_ENABLED(CONFIG_FSL_SOC)
 657                 pinfo = to_of_pinfo(pdata);
 658
 659                 spisel_boot = of_property_read_bool(np, "fsl,spisel_boot");
 660                 if (spisel_boot) {
 661                         pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4);
 662                         if (!pinfo->immr_spi_cs)
 663                                 return -ENOMEM;
 664                 }
 665 #endif
 666                 /*
 667                  * Handle the case where we have one hardwired (always selected)
 668                  * device on the first "chipselect". Else we let the core code
 669                  * handle any GPIOs or native chip selects and assign the
 670                  * appropriate callback for dealing with the CS lines. This isn't
 671                  * supported on the GRLIB variant.
 672                  */
 673                 ret = gpiod_count(dev, "cs");
 674                 if (ret < 0)
 675                         ret = 0;
 676                 if (ret == 0 && !spisel_boot)
 677                         pdata->max_chipselect = 1;
 678                 else
 679                         pdata->max_chipselect = ret + spisel_boot;
 680         }
 681
 682         ret = of_address_to_resource(np, 0, &mem);
 683         if (ret)
 684                 goto unmap_out;
 685
 686         irq = platform_get_irq(ofdev, 0);
 687         if (irq < 0) {
 688                 ret = irq;
 689                 goto unmap_out;
 690         }
 691
 692         host = fsl_spi_probe(dev, &mem, irq);
 693
 694         return PTR_ERR_OR_ZERO(host);
 695
 696 unmap_out:
 697 #if IS_ENABLED(CONFIG_FSL_SOC)
 698         if (spisel_boot)
 699                 iounmap(pinfo->immr_spi_cs);
 700 #endif
 701         return ret;
 702 }
 703
 704 static void of_fsl_spi_remove(struct platform_device *ofdev)
 705 {
 706         struct spi_controller *host = platform_get_drvdata(ofdev);
 707         struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(host);
 708
 709         fsl_spi_cpm_free(mpc8xxx_spi);
 710 }
 711
 712 static struct platform_driver of_fsl_spi_driver = {
 713         .driver = {
 714                 .name = "fsl_spi",
 715                 .of_match_table = of_fsl_spi_match,
 716         },
 717         .probe          = of_fsl_spi_probe,
 718         .remove_new     = of_fsl_spi_remove,
 719 };
 720
 721 #ifdef CONFIG_MPC832x_RDB
 722 /*
 723  * XXX XXX XXX
 724  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
 725  * only. The driver should go away soon, since newer MPC8323E-RDB's device
 726  * tree can work with OpenFirmware driver. But for now we support old trees
 727  * as well.
 728  */
 729 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
 730 {
 731         struct resource *mem;
 732         int irq;
 733         struct spi_controller *host;
 734
 735         if (!dev_get_platdata(&pdev->dev))
 736                 return -EINVAL;
 737
 738         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 739         if (!mem)
 740                 return -EINVAL;
 741
 742         irq = platform_get_irq(pdev, 0);
 743         if (irq < 0)
 744                 return irq;
 745
 746         host = fsl_spi_probe(&pdev->dev, mem, irq);
 747         return PTR_ERR_OR_ZERO(host);
 748 }
 749
 750 static void plat_mpc8xxx_spi_remove(struct platform_device *pdev)
 751 {
 752         struct spi_controller *host = platform_get_drvdata(pdev);
 753         struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(host);
 754
 755         fsl_spi_cpm_free(mpc8xxx_spi);
 756 }
 757
 758 MODULE_ALIAS("platform:mpc8xxx_spi");
 759 static struct platform_driver mpc8xxx_spi_driver = {
 760         .probe = plat_mpc8xxx_spi_probe,
 761         .remove_new = plat_mpc8xxx_spi_remove,
 762         .driver = {
 763                 .name = "mpc8xxx_spi",
 764         },
 765 };
 766
 767 static bool legacy_driver_failed;
 768
 769 static void __init legacy_driver_register(void)
 770 {
 771         legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
 772 }
 773
 774 static void __exit legacy_driver_unregister(void)
 775 {
 776         if (legacy_driver_failed)
 777                 return;
 778         platform_driver_unregister(&mpc8xxx_spi_driver);
 779 }
 780 #else
 781 static void __init legacy_driver_register(void) {}
 782 static void __exit legacy_driver_unregister(void) {}
 783 #endif /* CONFIG_MPC832x_RDB */
 784
 785 static int __init fsl_spi_init(void)
 786 {
 787         legacy_driver_register();
 788         return platform_driver_register(&of_fsl_spi_driver);
 789 }
 790 module_init(fsl_spi_init);
 791
 792 static void __exit fsl_spi_exit(void)
 793 {
 794         platform_driver_unregister(&of_fsl_spi_driver);
 795         legacy_driver_unregister();
 796 }
 797 module_exit(fsl_spi_exit);
 798
 799 MODULE_AUTHOR("Kumar Gala");
 800 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
 801 MODULE_LICENSE("GPL");