1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale SPI/eSPI controller driver library.
5 * Maintainer: Kumar Gala
7 * Copyright (C) 2006 Polycom, Inc.
9 * CPM SPI and QE buffer descriptors mode support:
10 * Copyright (c) 2009 MontaVista Software, Inc.
11 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
13 * Copyright 2010 Freescale Semiconductor, Inc.
15 #include <linux/dma-mapping.h>
16 #include <linux/fsl_devices.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/of_platform.h>
22 #include <linux/spi/spi.h>
24 #include <sysdev/fsl_soc.h>
27 #include "spi-fsl-lib.h"
29 #define MPC8XXX_SPI_RX_BUF(type) \
30 void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
32 type *rx = mpc8xxx_spi->rx; \
33 *rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \
34 mpc8xxx_spi->rx = rx; \
36 EXPORT_SYMBOL_GPL(mpc8xxx_spi_rx_buf_##type);
38 #define MPC8XXX_SPI_TX_BUF(type) \
39 u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
42 const type *tx = mpc8xxx_spi->tx; \
45 data = *tx++ << mpc8xxx_spi->tx_shift; \
46 mpc8xxx_spi->tx = tx; \
49 EXPORT_SYMBOL_GPL(mpc8xxx_spi_tx_buf_##type);
51 MPC8XXX_SPI_RX_BUF(u8)
52 MPC8XXX_SPI_RX_BUF(u16)
53 MPC8XXX_SPI_RX_BUF(u32)
54 MPC8XXX_SPI_TX_BUF(u8)
55 MPC8XXX_SPI_TX_BUF(u16)
56 MPC8XXX_SPI_TX_BUF(u32)
58 struct mpc8xxx_spi_probe_info *to_of_pinfo(struct fsl_spi_platform_data *pdata)
60 return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
62 EXPORT_SYMBOL_GPL(to_of_pinfo);
64 const char *mpc8xxx_spi_strmode(unsigned int flags)
66 if (flags & SPI_QE_CPU_MODE) {
68 } else if (flags & SPI_CPM_MODE) {
71 else if (flags & SPI_CPM2)
78 EXPORT_SYMBOL_GPL(mpc8xxx_spi_strmode);
80 void mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
83 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
84 struct spi_master *master;
85 struct mpc8xxx_spi *mpc8xxx_spi;
87 master = dev_get_drvdata(dev);
89 /* the spi->mode bits understood by this driver: */
90 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
91 | SPI_LSB_FIRST | SPI_LOOP;
93 master->dev.of_node = dev->of_node;
95 mpc8xxx_spi = spi_master_get_devdata(master);
96 mpc8xxx_spi->dev = dev;
97 mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
98 mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
99 mpc8xxx_spi->flags = pdata->flags;
100 mpc8xxx_spi->spibrg = pdata->sysclk;
101 mpc8xxx_spi->irq = irq;
103 mpc8xxx_spi->rx_shift = 0;
104 mpc8xxx_spi->tx_shift = 0;
106 master->bus_num = pdata->bus_num;
107 master->num_chipselect = pdata->max_chipselect;
109 init_completion(&mpc8xxx_spi->done);
111 EXPORT_SYMBOL_GPL(mpc8xxx_spi_probe);
113 int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
115 struct device *dev = &ofdev->dev;
116 struct device_node *np = ofdev->dev.of_node;
117 struct mpc8xxx_spi_probe_info *pinfo;
118 struct fsl_spi_platform_data *pdata;
122 pinfo = devm_kzalloc(&ofdev->dev, sizeof(*pinfo), GFP_KERNEL);
126 pdata = &pinfo->pdata;
127 dev->platform_data = pdata;
129 /* Allocate bus num dynamically. */
132 #ifdef CONFIG_FSL_SOC
133 /* SPI controller is either clocked from QE or SoC clock. */
134 pdata->sysclk = get_brgfreq();
135 if (pdata->sysclk == -1) {
136 pdata->sysclk = fsl_get_sys_freq();
137 if (pdata->sysclk == -1)
141 ret = of_property_read_u32(np, "clock-frequency", &pdata->sysclk);
146 prop = of_get_property(np, "mode", NULL);
147 if (prop && !strcmp(prop, "cpu-qe"))
148 pdata->flags = SPI_QE_CPU_MODE;
149 else if (prop && !strcmp(prop, "qe"))
150 pdata->flags = SPI_CPM_MODE | SPI_QE;
151 else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
152 pdata->flags = SPI_CPM_MODE | SPI_CPM2;
153 else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
154 pdata->flags = SPI_CPM_MODE | SPI_CPM1;
158 EXPORT_SYMBOL_GPL(of_mpc8xxx_spi_probe);
160 MODULE_LICENSE("GPL");