drivers/spi/spi-dw.c

   1 /*
   2  * Designware SPI core controller driver (refer pxa2xx_spi.c)
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #include <linux/dma-mapping.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/highmem.h>
  24 #include <linux/delay.h>
  25 #include <linux/slab.h>
  26 #include <linux/spi/spi.h>
  27
  28 #include "spi-dw.h"
  29
  30 #ifdef CONFIG_DEBUG_FS
  31 #include <linux/debugfs.h>
  32 #endif
  33
  34 #define START_STATE     ((void *)0)
  35 #define RUNNING_STATE   ((void *)1)
  36 #define DONE_STATE      ((void *)2)
  37 #define ERROR_STATE     ((void *)-1)
  38
  39 #define QUEUE_RUNNING   0
  40 #define QUEUE_STOPPED   1
  41
  42 #define MRST_SPI_DEASSERT       0
  43 #define MRST_SPI_ASSERT         1
  44
  45 /* Slave spi_dev related */
  46 struct chip_data {
  47         u16 cr0;
  48         u8 cs;                  /* chip select pin */
  49         u8 n_bytes;             /* current is a 1/2/4 byte op */
  50         u8 tmode;               /* TR/TO/RO/EEPROM */
  51         u8 type;                /* SPI/SSP/MicroWire */
  52
  53         u8 poll_mode;           /* 1 means use poll mode */
  54
  55         u32 dma_width;
  56         u32 rx_threshold;
  57         u32 tx_threshold;
  58         u8 enable_dma;
  59         u8 bits_per_word;
  60         u16 clk_div;            /* baud rate divider */
  61         u32 speed_hz;           /* baud rate */
  62         void (*cs_control)(u32 command);
  63 };
  64
  65 #ifdef CONFIG_DEBUG_FS
  66 #define SPI_REGS_BUFSIZE        1024
  67 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,
  68                                 size_t count, loff_t *ppos)
  69 {
  70         struct dw_spi *dws;
  71         char *buf;
  72         u32 len = 0;
  73         ssize_t ret;
  74
  75         dws = file->private_data;
  76
  77         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  78         if (!buf)
  79                 return 0;
  80
  81         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  82                         "MRST SPI0 registers:\n");
  83         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  84                         "=================================\n");
  85         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  86                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
  87         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  88                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
  89         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  90                         "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
  91         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  92                         "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
  93         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  94                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
  95         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  96                         "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
  97         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  98                         "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
  99         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 100                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
 101         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 102                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
 103         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 104                         "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
 105         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 106                         "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
 107         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 108                         "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
 109         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 110                         "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
 111         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 112                         "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
 113         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 114                         "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
 115         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 116                         "=================================\n");
 117
 118         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 119         kfree(buf);
 120         return ret;
 121 }
 122
 123 static const struct file_operations mrst_spi_regs_ops = {
 124         .owner          = THIS_MODULE,
 125         .open           = simple_open,
 126         .read           = spi_show_regs,
 127         .llseek         = default_llseek,
 128 };
 129
 130 static int mrst_spi_debugfs_init(struct dw_spi *dws)
 131 {
 132         dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
 133         if (!dws->debugfs)
 134                 return -ENOMEM;
 135
 136         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 137                 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
 138         return 0;
 139 }
 140
 141 static void mrst_spi_debugfs_remove(struct dw_spi *dws)
 142 {
 143         if (dws->debugfs)
 144                 debugfs_remove_recursive(dws->debugfs);
 145 }
 146
 147 #else
 148 static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
 149 {
 150         return 0;
 151 }
 152
 153 static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
 154 {
 155 }
 156 #endif /* CONFIG_DEBUG_FS */
 157
 158 /* Return the max entries we can fill into tx fifo */
 159 static inline u32 tx_max(struct dw_spi *dws)
 160 {
 161         u32 tx_left, tx_room, rxtx_gap;
 162
 163         tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
 164         tx_room = dws->fifo_len - dw_readw(dws, DW_SPI_TXFLR);
 165
 166         /*
 167          * Another concern is about the tx/rx mismatch, we
 168          * though to use (dws->fifo_len - rxflr - txflr) as
 169          * one maximum value for tx, but it doesn't cover the
 170          * data which is out of tx/rx fifo and inside the
 171          * shift registers. So a control from sw point of
 172          * view is taken.
 173          */
 174         rxtx_gap =  ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
 175                         / dws->n_bytes;
 176
 177         return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
 178 }
 179
 180 /* Return the max entries we should read out of rx fifo */
 181 static inline u32 rx_max(struct dw_spi *dws)
 182 {
 183         u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
 184
 185         return min(rx_left, (u32)dw_readw(dws, DW_SPI_RXFLR));
 186 }
 187
 188 static void dw_writer(struct dw_spi *dws)
 189 {
 190         u32 max = tx_max(dws);
 191         u16 txw = 0;
 192
 193         while (max--) {
 194                 /* Set the tx word if the transfer's original "tx" is not null */
 195                 if (dws->tx_end - dws->len) {
 196                         if (dws->n_bytes == 1)
 197                                 txw = *(u8 *)(dws->tx);
 198                         else
 199                                 txw = *(u16 *)(dws->tx);
 200                 }
 201                 dw_writew(dws, DW_SPI_DR, txw);
 202                 dws->tx += dws->n_bytes;
 203         }
 204 }
 205
 206 static void dw_reader(struct dw_spi *dws)
 207 {
 208         u32 max = rx_max(dws);
 209         u16 rxw;
 210
 211         while (max--) {
 212                 rxw = dw_readw(dws, DW_SPI_DR);
 213                 /* Care rx only if the transfer's original "rx" is not null */
 214                 if (dws->rx_end - dws->len) {
 215                         if (dws->n_bytes == 1)
 216                                 *(u8 *)(dws->rx) = rxw;
 217                         else
 218                                 *(u16 *)(dws->rx) = rxw;
 219                 }
 220                 dws->rx += dws->n_bytes;
 221         }
 222 }
 223
 224 static void *next_transfer(struct dw_spi *dws)
 225 {
 226         struct spi_message *msg = dws->cur_msg;
 227         struct spi_transfer *trans = dws->cur_transfer;
 228
 229         /* Move to next transfer */
 230         if (trans->transfer_list.next != &msg->transfers) {
 231                 dws->cur_transfer =
 232                         list_entry(trans->transfer_list.next,
 233                                         struct spi_transfer,
 234                                         transfer_list);
 235                 return RUNNING_STATE;
 236         } else
 237                 return DONE_STATE;
 238 }
 239
 240 /*
 241  * Note: first step is the protocol driver prepares
 242  * a dma-capable memory, and this func just need translate
 243  * the virt addr to physical
 244  */
 245 static int map_dma_buffers(struct dw_spi *dws)
 246 {
 247         if (!dws->cur_msg->is_dma_mapped
 248                 || !dws->dma_inited
 249                 || !dws->cur_chip->enable_dma
 250                 || !dws->dma_ops)
 251                 return 0;
 252
 253         if (dws->cur_transfer->tx_dma)
 254                 dws->tx_dma = dws->cur_transfer->tx_dma;
 255
 256         if (dws->cur_transfer->rx_dma)
 257                 dws->rx_dma = dws->cur_transfer->rx_dma;
 258
 259         return 1;
 260 }
 261
 262 /* Caller already set message->status; dma and pio irqs are blocked */
 263 static void giveback(struct dw_spi *dws)
 264 {
 265         struct spi_transfer *last_transfer;
 266         unsigned long flags;
 267         struct spi_message *msg;
 268
 269         spin_lock_irqsave(&dws->lock, flags);
 270         msg = dws->cur_msg;
 271         dws->cur_msg = NULL;
 272         dws->cur_transfer = NULL;
 273         dws->prev_chip = dws->cur_chip;
 274         dws->cur_chip = NULL;
 275         dws->dma_mapped = 0;
 276         queue_work(dws->workqueue, &dws->pump_messages);
 277         spin_unlock_irqrestore(&dws->lock, flags);
 278
 279         last_transfer = list_entry(msg->transfers.prev,
 280                                         struct spi_transfer,
 281                                         transfer_list);
 282
 283         if (!last_transfer->cs_change && dws->cs_control)
 284                 dws->cs_control(MRST_SPI_DEASSERT);
 285
 286         msg->state = NULL;
 287         if (msg->complete)
 288                 msg->complete(msg->context);
 289 }
 290
 291 static void int_error_stop(struct dw_spi *dws, const char *msg)
 292 {
 293         /* Stop the hw */
 294         spi_enable_chip(dws, 0);
 295
 296         dev_err(&dws->master->dev, "%s\n", msg);
 297         dws->cur_msg->state = ERROR_STATE;
 298         tasklet_schedule(&dws->pump_transfers);
 299 }
 300
 301 void dw_spi_xfer_done(struct dw_spi *dws)
 302 {
 303         /* Update total byte transferred return count actual bytes read */
 304         dws->cur_msg->actual_length += dws->len;
 305
 306         /* Move to next transfer */
 307         dws->cur_msg->state = next_transfer(dws);
 308
 309         /* Handle end of message */
 310         if (dws->cur_msg->state == DONE_STATE) {
 311                 dws->cur_msg->status = 0;
 312                 giveback(dws);
 313         } else
 314                 tasklet_schedule(&dws->pump_transfers);
 315 }
 316 EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
 317
 318 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 319 {
 320         u16 irq_status = dw_readw(dws, DW_SPI_ISR);
 321
 322         /* Error handling */
 323         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 324                 dw_readw(dws, DW_SPI_TXOICR);
 325                 dw_readw(dws, DW_SPI_RXOICR);
 326                 dw_readw(dws, DW_SPI_RXUICR);
 327                 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
 328                 return IRQ_HANDLED;
 329         }
 330
 331         dw_reader(dws);
 332         if (dws->rx_end == dws->rx) {
 333                 spi_mask_intr(dws, SPI_INT_TXEI);
 334                 dw_spi_xfer_done(dws);
 335                 return IRQ_HANDLED;
 336         }
 337         if (irq_status & SPI_INT_TXEI) {
 338                 spi_mask_intr(dws, SPI_INT_TXEI);
 339                 dw_writer(dws);
 340                 /* Enable TX irq always, it will be disabled when RX finished */
 341                 spi_umask_intr(dws, SPI_INT_TXEI);
 342         }
 343
 344         return IRQ_HANDLED;
 345 }
 346
 347 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 348 {
 349         struct dw_spi *dws = dev_id;
 350         u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f;
 351
 352         if (!irq_status)
 353                 return IRQ_NONE;
 354
 355         if (!dws->cur_msg) {
 356                 spi_mask_intr(dws, SPI_INT_TXEI);
 357                 return IRQ_HANDLED;
 358         }
 359
 360         return dws->transfer_handler(dws);
 361 }
 362
 363 /* Must be called inside pump_transfers() */
 364 static void poll_transfer(struct dw_spi *dws)
 365 {
 366         do {
 367                 dw_writer(dws);
 368                 dw_reader(dws);
 369                 cpu_relax();
 370         } while (dws->rx_end > dws->rx);
 371
 372         dw_spi_xfer_done(dws);
 373 }
 374
 375 static void pump_transfers(unsigned long data)
 376 {
 377         struct dw_spi *dws = (struct dw_spi *)data;
 378         struct spi_message *message = NULL;
 379         struct spi_transfer *transfer = NULL;
 380         struct spi_transfer *previous = NULL;
 381         struct spi_device *spi = NULL;
 382         struct chip_data *chip = NULL;
 383         u8 bits = 0;
 384         u8 imask = 0;
 385         u8 cs_change = 0;
 386         u16 txint_level = 0;
 387         u16 clk_div = 0;
 388         u32 speed = 0;
 389         u32 cr0 = 0;
 390
 391         /* Get current state information */
 392         message = dws->cur_msg;
 393         transfer = dws->cur_transfer;
 394         chip = dws->cur_chip;
 395         spi = message->spi;
 396
 397         if (message->state == ERROR_STATE) {
 398                 message->status = -EIO;
 399                 goto early_exit;
 400         }
 401
 402         /* Handle end of message */
 403         if (message->state == DONE_STATE) {
 404                 message->status = 0;
 405                 goto early_exit;
 406         }
 407
 408         /* Delay if requested at end of transfer*/
 409         if (message->state == RUNNING_STATE) {
 410                 previous = list_entry(transfer->transfer_list.prev,
 411                                         struct spi_transfer,
 412                                         transfer_list);
 413                 if (previous->delay_usecs)
 414                         udelay(previous->delay_usecs);
 415         }
 416
 417         dws->n_bytes = chip->n_bytes;
 418         dws->dma_width = chip->dma_width;
 419         dws->cs_control = chip->cs_control;
 420
 421         dws->rx_dma = transfer->rx_dma;
 422         dws->tx_dma = transfer->tx_dma;
 423         dws->tx = (void *)transfer->tx_buf;
 424         dws->tx_end = dws->tx + transfer->len;
 425         dws->rx = transfer->rx_buf;
 426         dws->rx_end = dws->rx + transfer->len;
 427         dws->len = dws->cur_transfer->len;
 428         if (chip != dws->prev_chip)
 429                 cs_change = 1;
 430
 431         cr0 = chip->cr0;
 432
 433         /* Handle per transfer options for bpw and speed */
 434         if (transfer->speed_hz) {
 435                 speed = chip->speed_hz;
 436
 437                 if ((transfer->speed_hz != speed) || (!chip->clk_div)) {
 438                         speed = transfer->speed_hz;
 439                         if (speed > dws->max_freq) {
 440                                 printk(KERN_ERR "MRST SPI0: unsupported"
 441                                         "freq: %dHz\n", speed);
 442                                 message->status = -EIO;
 443                                 goto early_exit;
 444                         }
 445
 446                         /* clk_div doesn't support odd number */
 447                         clk_div = dws->max_freq / speed;
 448                         clk_div = (clk_div + 1) & 0xfffe;
 449
 450                         chip->speed_hz = speed;
 451                         chip->clk_div = clk_div;
 452                 }
 453         }
 454         if (transfer->bits_per_word) {
 455                 bits = transfer->bits_per_word;
 456                 dws->n_bytes = dws->dma_width = bits >> 3;
 457                 cr0 = (bits - 1)
 458                         | (chip->type << SPI_FRF_OFFSET)
 459                         | (spi->mode << SPI_MODE_OFFSET)
 460                         | (chip->tmode << SPI_TMOD_OFFSET);
 461         }
 462         message->state = RUNNING_STATE;
 463
 464         /*
 465          * Adjust transfer mode if necessary. Requires platform dependent
 466          * chipselect mechanism.
 467          */
 468         if (dws->cs_control) {
 469                 if (dws->rx && dws->tx)
 470                         chip->tmode = SPI_TMOD_TR;
 471                 else if (dws->rx)
 472                         chip->tmode = SPI_TMOD_RO;
 473                 else
 474                         chip->tmode = SPI_TMOD_TO;
 475
 476                 cr0 &= ~SPI_TMOD_MASK;
 477                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 478         }
 479
 480         /* Check if current transfer is a DMA transaction */
 481         dws->dma_mapped = map_dma_buffers(dws);
 482
 483         /*
 484          * Interrupt mode
 485          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 486          */
 487         if (!dws->dma_mapped && !chip->poll_mode) {
 488                 int templen = dws->len / dws->n_bytes;
 489                 txint_level = dws->fifo_len / 2;
 490                 txint_level = (templen > txint_level) ? txint_level : templen;
 491
 492                 imask |= SPI_INT_TXEI | SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI;
 493                 dws->transfer_handler = interrupt_transfer;
 494         }
 495
 496         /*
 497          * Reprogram registers only if
 498          *      1. chip select changes
 499          *      2. clk_div is changed
 500          *      3. control value changes
 501          */
 502         if (dw_readw(dws, DW_SPI_CTRL0) != cr0 || cs_change || clk_div || imask) {
 503                 spi_enable_chip(dws, 0);
 504
 505                 if (dw_readw(dws, DW_SPI_CTRL0) != cr0)
 506                         dw_writew(dws, DW_SPI_CTRL0, cr0);
 507
 508                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
 509                 spi_chip_sel(dws, spi->chip_select);
 510
 511                 /* Set the interrupt mask, for poll mode just disable all int */
 512                 spi_mask_intr(dws, 0xff);
 513                 if (imask)
 514                         spi_umask_intr(dws, imask);
 515                 if (txint_level)
 516                         dw_writew(dws, DW_SPI_TXFLTR, txint_level);
 517
 518                 spi_enable_chip(dws, 1);
 519                 if (cs_change)
 520                         dws->prev_chip = chip;
 521         }
 522
 523         if (dws->dma_mapped)
 524                 dws->dma_ops->dma_transfer(dws, cs_change);
 525
 526         if (chip->poll_mode)
 527                 poll_transfer(dws);
 528
 529         return;
 530
 531 early_exit:
 532         giveback(dws);
 533         return;
 534 }
 535
 536 static void pump_messages(struct work_struct *work)
 537 {
 538         struct dw_spi *dws =
 539                 container_of(work, struct dw_spi, pump_messages);
 540         unsigned long flags;
 541
 542         /* Lock queue and check for queue work */
 543         spin_lock_irqsave(&dws->lock, flags);
 544         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
 545                 dws->busy = 0;
 546                 spin_unlock_irqrestore(&dws->lock, flags);
 547                 return;
 548         }
 549
 550         /* Make sure we are not already running a message */
 551         if (dws->cur_msg) {
 552                 spin_unlock_irqrestore(&dws->lock, flags);
 553                 return;
 554         }
 555
 556         /* Extract head of queue */
 557         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
 558         list_del_init(&dws->cur_msg->queue);
 559
 560         /* Initial message state*/
 561         dws->cur_msg->state = START_STATE;
 562         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
 563                                                 struct spi_transfer,
 564                                                 transfer_list);
 565         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
 566
 567         /* Mark as busy and launch transfers */
 568         tasklet_schedule(&dws->pump_transfers);
 569
 570         dws->busy = 1;
 571         spin_unlock_irqrestore(&dws->lock, flags);
 572 }
 573
 574 /* spi_device use this to queue in their spi_msg */
 575 static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 576 {
 577         struct dw_spi *dws = spi_master_get_devdata(spi->master);
 578         unsigned long flags;
 579
 580         spin_lock_irqsave(&dws->lock, flags);
 581
 582         if (dws->run == QUEUE_STOPPED) {
 583                 spin_unlock_irqrestore(&dws->lock, flags);
 584                 return -ESHUTDOWN;
 585         }
 586
 587         msg->actual_length = 0;
 588         msg->status = -EINPROGRESS;
 589         msg->state = START_STATE;
 590
 591         list_add_tail(&msg->queue, &dws->queue);
 592
 593         if (dws->run == QUEUE_RUNNING && !dws->busy) {
 594
 595                 if (dws->cur_transfer || dws->cur_msg)
 596                         queue_work(dws->workqueue,
 597                                         &dws->pump_messages);
 598                 else {
 599                         /* If no other data transaction in air, just go */
 600                         spin_unlock_irqrestore(&dws->lock, flags);
 601                         pump_messages(&dws->pump_messages);
 602                         return 0;
 603                 }
 604         }
 605
 606         spin_unlock_irqrestore(&dws->lock, flags);
 607         return 0;
 608 }
 609
 610 /* This may be called twice for each spi dev */
 611 static int dw_spi_setup(struct spi_device *spi)
 612 {
 613         struct dw_spi_chip *chip_info = NULL;
 614         struct chip_data *chip;
 615
 616         /* Only alloc on first setup */
 617         chip = spi_get_ctldata(spi);
 618         if (!chip) {
 619                 chip = devm_kzalloc(&spi->dev, sizeof(struct chip_data),
 620                                 GFP_KERNEL);
 621                 if (!chip)
 622                         return -ENOMEM;
 623                 spi_set_ctldata(spi, chip);
 624         }
 625
 626         /*
 627          * Protocol drivers may change the chip settings, so...
 628          * if chip_info exists, use it
 629          */
 630         chip_info = spi->controller_data;
 631
 632         /* chip_info doesn't always exist */
 633         if (chip_info) {
 634                 if (chip_info->cs_control)
 635                         chip->cs_control = chip_info->cs_control;
 636
 637                 chip->poll_mode = chip_info->poll_mode;
 638                 chip->type = chip_info->type;
 639
 640                 chip->rx_threshold = 0;
 641                 chip->tx_threshold = 0;
 642
 643                 chip->enable_dma = chip_info->enable_dma;
 644         }
 645
 646         if (spi->bits_per_word == 8) {
 647                 chip->n_bytes = 1;
 648                 chip->dma_width = 1;
 649         } else if (spi->bits_per_word == 16) {
 650                 chip->n_bytes = 2;
 651                 chip->dma_width = 2;
 652         }
 653         chip->bits_per_word = spi->bits_per_word;
 654
 655         if (!spi->max_speed_hz) {
 656                 dev_err(&spi->dev, "No max speed HZ parameter\n");
 657                 return -EINVAL;
 658         }
 659
 660         chip->tmode = 0; /* Tx & Rx */
 661         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 662         chip->cr0 = (chip->bits_per_word - 1)
 663                         | (chip->type << SPI_FRF_OFFSET)
 664                         | (spi->mode  << SPI_MODE_OFFSET)
 665                         | (chip->tmode << SPI_TMOD_OFFSET);
 666
 667         return 0;
 668 }
 669
 670 static int init_queue(struct dw_spi *dws)
 671 {
 672         INIT_LIST_HEAD(&dws->queue);
 673         spin_lock_init(&dws->lock);
 674
 675         dws->run = QUEUE_STOPPED;
 676         dws->busy = 0;
 677
 678         tasklet_init(&dws->pump_transfers,
 679                         pump_transfers, (unsigned long)dws);
 680
 681         INIT_WORK(&dws->pump_messages, pump_messages);
 682         dws->workqueue = create_singlethread_workqueue(
 683                                         dev_name(dws->master->dev.parent));
 684         if (dws->workqueue == NULL)
 685                 return -EBUSY;
 686
 687         return 0;
 688 }
 689
 690 static int start_queue(struct dw_spi *dws)
 691 {
 692         unsigned long flags;
 693
 694         spin_lock_irqsave(&dws->lock, flags);
 695
 696         if (dws->run == QUEUE_RUNNING || dws->busy) {
 697                 spin_unlock_irqrestore(&dws->lock, flags);
 698                 return -EBUSY;
 699         }
 700
 701         dws->run = QUEUE_RUNNING;
 702         dws->cur_msg = NULL;
 703         dws->cur_transfer = NULL;
 704         dws->cur_chip = NULL;
 705         dws->prev_chip = NULL;
 706         spin_unlock_irqrestore(&dws->lock, flags);
 707
 708         queue_work(dws->workqueue, &dws->pump_messages);
 709
 710         return 0;
 711 }
 712
 713 static int stop_queue(struct dw_spi *dws)
 714 {
 715         unsigned long flags;
 716         unsigned limit = 50;
 717         int status = 0;
 718
 719         spin_lock_irqsave(&dws->lock, flags);
 720         dws->run = QUEUE_STOPPED;
 721         while ((!list_empty(&dws->queue) || dws->busy) && limit--) {
 722                 spin_unlock_irqrestore(&dws->lock, flags);
 723                 msleep(10);
 724                 spin_lock_irqsave(&dws->lock, flags);
 725         }
 726
 727         if (!list_empty(&dws->queue) || dws->busy)
 728                 status = -EBUSY;
 729         spin_unlock_irqrestore(&dws->lock, flags);
 730
 731         return status;
 732 }
 733
 734 static int destroy_queue(struct dw_spi *dws)
 735 {
 736         int status;
 737
 738         status = stop_queue(dws);
 739         if (status != 0)
 740                 return status;
 741         destroy_workqueue(dws->workqueue);
 742         return 0;
 743 }
 744
 745 /* Restart the controller, disable all interrupts, clean rx fifo */
 746 static void spi_hw_init(struct dw_spi *dws)
 747 {
 748         spi_enable_chip(dws, 0);
 749         spi_mask_intr(dws, 0xff);
 750         spi_enable_chip(dws, 1);
 751
 752         /*
 753          * Try to detect the FIFO depth if not set by interface driver,
 754          * the depth could be from 2 to 256 from HW spec
 755          */
 756         if (!dws->fifo_len) {
 757                 u32 fifo;
 758                 for (fifo = 2; fifo <= 257; fifo++) {
 759                         dw_writew(dws, DW_SPI_TXFLTR, fifo);
 760                         if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
 761                                 break;
 762                 }
 763
 764                 dws->fifo_len = (fifo == 257) ? 0 : fifo;
 765                 dw_writew(dws, DW_SPI_TXFLTR, 0);
 766         }
 767 }
 768
 769 int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
 770 {
 771         struct spi_master *master;
 772         int ret;
 773
 774         BUG_ON(dws == NULL);
 775
 776         master = spi_alloc_master(dev, 0);
 777         if (!master)
 778                 return -ENOMEM;
 779
 780         dws->master = master;
 781         dws->type = SSI_MOTO_SPI;
 782         dws->prev_chip = NULL;
 783         dws->dma_inited = 0;
 784         dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
 785         snprintf(dws->name, sizeof(dws->name), "dw_spi%d",
 786                         dws->bus_num);
 787
 788         ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED,
 789                         dws->name, dws);
 790         if (ret < 0) {
 791                 dev_err(&master->dev, "can not get IRQ\n");
 792                 goto err_free_master;
 793         }
 794
 795         master->mode_bits = SPI_CPOL | SPI_CPHA;
 796         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
 797         master->bus_num = dws->bus_num;
 798         master->num_chipselect = dws->num_cs;
 799         master->setup = dw_spi_setup;
 800         master->transfer = dw_spi_transfer;
 801
 802         /* Basic HW init */
 803         spi_hw_init(dws);
 804
 805         if (dws->dma_ops && dws->dma_ops->dma_init) {
 806                 ret = dws->dma_ops->dma_init(dws);
 807                 if (ret) {
 808                         dev_warn(&master->dev, "DMA init failed\n");
 809                         dws->dma_inited = 0;
 810                 }
 811         }
 812
 813         /* Initial and start queue */
 814         ret = init_queue(dws);
 815         if (ret) {
 816                 dev_err(&master->dev, "problem initializing queue\n");
 817                 goto err_diable_hw;
 818         }
 819         ret = start_queue(dws);
 820         if (ret) {
 821                 dev_err(&master->dev, "problem starting queue\n");
 822                 goto err_diable_hw;
 823         }
 824
 825         spi_master_set_devdata(master, dws);
 826         ret = devm_spi_register_master(dev, master);
 827         if (ret) {
 828                 dev_err(&master->dev, "problem registering spi master\n");
 829                 goto err_queue_alloc;
 830         }
 831
 832         mrst_spi_debugfs_init(dws);
 833         return 0;
 834
 835 err_queue_alloc:
 836         destroy_queue(dws);
 837         if (dws->dma_ops && dws->dma_ops->dma_exit)
 838                 dws->dma_ops->dma_exit(dws);
 839 err_diable_hw:
 840         spi_enable_chip(dws, 0);
 841 err_free_master:
 842         spi_master_put(master);
 843         return ret;
 844 }
 845 EXPORT_SYMBOL_GPL(dw_spi_add_host);
 846
 847 void dw_spi_remove_host(struct dw_spi *dws)
 848 {
 849         int status = 0;
 850
 851         if (!dws)
 852                 return;
 853         mrst_spi_debugfs_remove(dws);
 854
 855         /* Remove the queue */
 856         status = destroy_queue(dws);
 857         if (status != 0)
 858                 dev_err(&dws->master->dev,
 859                         "dw_spi_remove: workqueue will not complete, message memory not freed\n");
 860
 861         if (dws->dma_ops && dws->dma_ops->dma_exit)
 862                 dws->dma_ops->dma_exit(dws);
 863         spi_enable_chip(dws, 0);
 864         /* Disable clk */
 865         spi_set_clk(dws, 0);
 866 }
 867 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
 868
 869 int dw_spi_suspend_host(struct dw_spi *dws)
 870 {
 871         int ret = 0;
 872
 873         ret = stop_queue(dws);
 874         if (ret)
 875                 return ret;
 876         spi_enable_chip(dws, 0);
 877         spi_set_clk(dws, 0);
 878         return ret;
 879 }
 880 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
 881
 882 int dw_spi_resume_host(struct dw_spi *dws)
 883 {
 884         int ret;
 885
 886         spi_hw_init(dws);
 887         ret = start_queue(dws);
 888         if (ret)
 889                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
 890         return ret;
 891 }
 892 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
 893
 894 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
 895 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
 896 MODULE_LICENSE("GPL v2");