drivers/spi/spi-dw-mmio.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Memory-mapped interface driver for DW SPI Core
   4  *
   5  * Copyright (c) 2010, Octasic semiconductor.
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/err.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/pm_runtime.h>
  12 #include <linux/slab.h>
  13 #include <linux/spi/spi.h>
  14 #include <linux/scatterlist.h>
  15 #include <linux/mfd/syscon.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/acpi.h>
  20 #include <linux/property.h>
  21 #include <linux/regmap.h>
  22 #include <linux/reset.h>
  23 #include <linux/interrupt.h>
  24
  25 #include "spi-dw.h"
  26
  27 #define DRIVER_NAME "dw_spi_mmio"
  28
  29 struct dw_spi_mmio {
  30         struct dw_spi  dws;
  31         struct clk     *clk;
  32         struct clk     *pclk;
  33         void           *priv;
  34         struct reset_control *rstc;
  35 };
  36
  37 #define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL       0x24
  38 #define OCELOT_IF_SI_OWNER_OFFSET               4
  39 #define JAGUAR2_IF_SI_OWNER_OFFSET              6
  40 #define MSCC_IF_SI_OWNER_MASK                   GENMASK(1, 0)
  41 #define MSCC_IF_SI_OWNER_SISL                   0
  42 #define MSCC_IF_SI_OWNER_SIBM                   1
  43 #define MSCC_IF_SI_OWNER_SIMC                   2
  44
  45 #define MSCC_SPI_MST_SW_MODE                    0x14
  46 #define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE   BIT(13)
  47 #define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x)       (x << 5)
  48
  49 #define SPARX5_FORCE_ENA                        0xa4
  50 #define SPARX5_FORCE_VAL                        0xa8
  51
  52 struct dw_spi_mscc {
  53         struct regmap       *syscon;
  54         void __iomem        *spi_mst; /* Not sparx5 */
  55 };
  56
  57 /*
  58  * Elba SoC does not use ssi, pin override is used for cs 0,1 and
  59  * gpios for cs 2,3 as defined in the device tree.
  60  *
  61  * cs:  |       1               0
  62  * bit: |---3-------2-------1-------0
  63  *      |  cs1   cs1_ovr   cs0   cs0_ovr
  64  */
  65 #define ELBA_SPICS_REG                  0x2468
  66 #define ELBA_SPICS_OFFSET(cs)           ((cs) << 1)
  67 #define ELBA_SPICS_MASK(cs)             (GENMASK(1, 0) << ELBA_SPICS_OFFSET(cs))
  68 #define ELBA_SPICS_SET(cs, val)         \
  69                 ((((val) << 1) | BIT(0)) << ELBA_SPICS_OFFSET(cs))
  70
  71 /*
  72  * The Designware SPI controller (referred to as master in the documentation)
  73  * automatically deasserts chip select when the tx fifo is empty. The chip
  74  * selects then needs to be either driven as GPIOs or, for the first 4 using
  75  * the SPI boot controller registers. the final chip select is an OR gate
  76  * between the Designware SPI controller and the SPI boot controller.
  77  */
  78 static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
  79 {
  80         struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
  81         struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
  82         struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
  83         u32 cs = spi_get_chipselect(spi, 0);
  84
  85         if (cs < 4) {
  86                 u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
  87
  88                 if (!enable)
  89                         sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
  90
  91                 writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
  92         }
  93
  94         dw_spi_set_cs(spi, enable);
  95 }
  96
  97 static int dw_spi_mscc_init(struct platform_device *pdev,
  98                             struct dw_spi_mmio *dwsmmio,
  99                             const char *cpu_syscon, u32 if_si_owner_offset)
 100 {
 101         struct dw_spi_mscc *dwsmscc;
 102
 103         dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
 104         if (!dwsmscc)
 105                 return -ENOMEM;
 106
 107         dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1);
 108         if (IS_ERR(dwsmscc->spi_mst)) {
 109                 dev_err(&pdev->dev, "SPI_MST region map failed\n");
 110                 return PTR_ERR(dwsmscc->spi_mst);
 111         }
 112
 113         dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
 114         if (IS_ERR(dwsmscc->syscon))
 115                 return PTR_ERR(dwsmscc->syscon);
 116
 117         /* Deassert all CS */
 118         writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
 119
 120         /* Select the owner of the SI interface */
 121         regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
 122                            MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
 123                            MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);
 124
 125         dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
 126         dwsmmio->priv = dwsmscc;
 127
 128         return 0;
 129 }
 130
 131 static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
 132                                    struct dw_spi_mmio *dwsmmio)
 133 {
 134         return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
 135                                 OCELOT_IF_SI_OWNER_OFFSET);
 136 }
 137
 138 static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
 139                                     struct dw_spi_mmio *dwsmmio)
 140 {
 141         return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
 142                                 JAGUAR2_IF_SI_OWNER_OFFSET);
 143 }
 144
 145 /*
 146  * The Designware SPI controller (referred to as master in the
 147  * documentation) automatically deasserts chip select when the tx fifo
 148  * is empty. The chip selects then needs to be driven by a CS override
 149  * register. enable is an active low signal.
 150  */
 151 static void dw_spi_sparx5_set_cs(struct spi_device *spi, bool enable)
 152 {
 153         struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
 154         struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
 155         struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
 156         u8 cs = spi_get_chipselect(spi, 0);
 157
 158         if (!enable) {
 159                 /* CS override drive enable */
 160                 regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 1);
 161                 /* Now set CSx enabled */
 162                 regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~BIT(cs));
 163                 /* Allow settle */
 164                 usleep_range(1, 5);
 165         } else {
 166                 /* CS value */
 167                 regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~0);
 168                 /* Allow settle */
 169                 usleep_range(1, 5);
 170                 /* CS override drive disable */
 171                 regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 0);
 172         }
 173
 174         dw_spi_set_cs(spi, enable);
 175 }
 176
 177 static int dw_spi_mscc_sparx5_init(struct platform_device *pdev,
 178                                    struct dw_spi_mmio *dwsmmio)
 179 {
 180         const char *syscon_name = "microchip,sparx5-cpu-syscon";
 181         struct device *dev = &pdev->dev;
 182         struct dw_spi_mscc *dwsmscc;
 183
 184         if (!IS_ENABLED(CONFIG_SPI_MUX)) {
 185                 dev_err(dev, "This driver needs CONFIG_SPI_MUX\n");
 186                 return -EOPNOTSUPP;
 187         }
 188
 189         dwsmscc = devm_kzalloc(dev, sizeof(*dwsmscc), GFP_KERNEL);
 190         if (!dwsmscc)
 191                 return -ENOMEM;
 192
 193         dwsmscc->syscon =
 194                 syscon_regmap_lookup_by_compatible(syscon_name);
 195         if (IS_ERR(dwsmscc->syscon)) {
 196                 dev_err(dev, "No syscon map %s\n", syscon_name);
 197                 return PTR_ERR(dwsmscc->syscon);
 198         }
 199
 200         dwsmmio->dws.set_cs = dw_spi_sparx5_set_cs;
 201         dwsmmio->priv = dwsmscc;
 202
 203         return 0;
 204 }
 205
 206 static int dw_spi_alpine_init(struct platform_device *pdev,
 207                               struct dw_spi_mmio *dwsmmio)
 208 {
 209         dwsmmio->dws.caps = DW_SPI_CAP_CS_OVERRIDE;
 210
 211         return 0;
 212 }
 213
 214 static int dw_spi_pssi_init(struct platform_device *pdev,
 215                             struct dw_spi_mmio *dwsmmio)
 216 {
 217         dw_spi_dma_setup_generic(&dwsmmio->dws);
 218
 219         return 0;
 220 }
 221
 222 static int dw_spi_hssi_init(struct platform_device *pdev,
 223                             struct dw_spi_mmio *dwsmmio)
 224 {
 225         dwsmmio->dws.ip = DW_HSSI_ID;
 226
 227         dw_spi_dma_setup_generic(&dwsmmio->dws);
 228
 229         return 0;
 230 }
 231
 232 static int dw_spi_intel_init(struct platform_device *pdev,
 233                              struct dw_spi_mmio *dwsmmio)
 234 {
 235         dwsmmio->dws.ip = DW_HSSI_ID;
 236
 237         return 0;
 238 }
 239
 240 /*
 241  * DMA-based mem ops are not configured for this device and are not tested.
 242  */
 243 static int dw_spi_mountevans_imc_init(struct platform_device *pdev,
 244                                       struct dw_spi_mmio *dwsmmio)
 245 {
 246         /*
 247          * The Intel Mount Evans SoC's Integrated Management Complex DW
 248          * apb_ssi_v4.02a controller has an errata where a full TX FIFO can
 249          * result in data corruption. The suggested workaround is to never
 250          * completely fill the FIFO. The TX FIFO has a size of 32 so the
 251          * fifo_len is set to 31.
 252          */
 253         dwsmmio->dws.fifo_len = 31;
 254
 255         return 0;
 256 }
 257
 258 static int dw_spi_canaan_k210_init(struct platform_device *pdev,
 259                                    struct dw_spi_mmio *dwsmmio)
 260 {
 261         /*
 262          * The Canaan Kendryte K210 SoC DW apb_ssi v4 spi controller is
 263          * documented to have a 32 word deep TX and RX FIFO, which
 264          * spi_hw_init() detects. However, when the RX FIFO is filled up to
 265          * 32 entries (RXFLR = 32), an RX FIFO overrun error occurs. Avoid this
 266          * problem by force setting fifo_len to 31.
 267          */
 268         dwsmmio->dws.fifo_len = 31;
 269
 270         return 0;
 271 }
 272
 273 static void dw_spi_elba_override_cs(struct regmap *syscon, int cs, int enable)
 274 {
 275         regmap_update_bits(syscon, ELBA_SPICS_REG, ELBA_SPICS_MASK(cs),
 276                            ELBA_SPICS_SET(cs, enable));
 277 }
 278
 279 static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable)
 280 {
 281         struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
 282         struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
 283         struct regmap *syscon = dwsmmio->priv;
 284         u8 cs;
 285
 286         cs = spi_get_chipselect(spi, 0);
 287         if (cs < 2)
 288                 dw_spi_elba_override_cs(syscon, spi_get_chipselect(spi, 0), enable);
 289
 290         /*
 291          * The DW SPI controller needs a native CS bit selected to start
 292          * the serial engine.
 293          */
 294         spi_set_chipselect(spi, 0, 0);
 295         dw_spi_set_cs(spi, enable);
 296         spi_set_chipselect(spi, 0, cs);
 297 }
 298
 299 static int dw_spi_elba_init(struct platform_device *pdev,
 300                             struct dw_spi_mmio *dwsmmio)
 301 {
 302         struct regmap *syscon;
 303
 304         syscon = syscon_regmap_lookup_by_phandle(dev_of_node(&pdev->dev),
 305                                                  "amd,pensando-elba-syscon");
 306         if (IS_ERR(syscon))
 307                 return dev_err_probe(&pdev->dev, PTR_ERR(syscon),
 308                                      "syscon regmap lookup failed\n");
 309
 310         dwsmmio->priv = syscon;
 311         dwsmmio->dws.set_cs = dw_spi_elba_set_cs;
 312
 313         return 0;
 314 }
 315
 316 static int dw_spi_mmio_probe(struct platform_device *pdev)
 317 {
 318         int (*init_func)(struct platform_device *pdev,
 319                          struct dw_spi_mmio *dwsmmio);
 320         struct dw_spi_mmio *dwsmmio;
 321         struct resource *mem;
 322         struct dw_spi *dws;
 323         int ret;
 324         int num_cs;
 325
 326         dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
 327                         GFP_KERNEL);
 328         if (!dwsmmio)
 329                 return -ENOMEM;
 330
 331         dws = &dwsmmio->dws;
 332
 333         /* Get basic io resource and map it */
 334         dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
 335         if (IS_ERR(dws->regs))
 336                 return PTR_ERR(dws->regs);
 337
 338         dws->paddr = mem->start;
 339
 340         dws->irq = platform_get_irq(pdev, 0);
 341         if (dws->irq < 0) {
 342                 if (dws->irq != -ENXIO)
 343                         return dws->irq; /* -ENXIO */
 344                 dws->irq = IRQ_NOTCONNECTED;
 345         }
 346
 347         dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
 348         if (IS_ERR(dwsmmio->clk))
 349                 return PTR_ERR(dwsmmio->clk);
 350         ret = clk_prepare_enable(dwsmmio->clk);
 351         if (ret)
 352                 return ret;
 353
 354         /* Optional clock needed to access the registers */
 355         dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
 356         if (IS_ERR(dwsmmio->pclk)) {
 357                 ret = PTR_ERR(dwsmmio->pclk);
 358                 goto out_clk;
 359         }
 360         ret = clk_prepare_enable(dwsmmio->pclk);
 361         if (ret)
 362                 goto out_clk;
 363
 364         /* find an optional reset controller */
 365         dwsmmio->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi");
 366         if (IS_ERR(dwsmmio->rstc)) {
 367                 ret = PTR_ERR(dwsmmio->rstc);
 368                 goto out_clk;
 369         }
 370         reset_control_deassert(dwsmmio->rstc);
 371
 372         dws->bus_num = pdev->id;
 373
 374         dws->max_freq = clk_get_rate(dwsmmio->clk);
 375
 376         if (device_property_read_u32(&pdev->dev, "reg-io-width",
 377                                      &dws->reg_io_width))
 378                 dws->reg_io_width = 4;
 379
 380         num_cs = 4;
 381
 382         device_property_read_u32(&pdev->dev, "num-cs", &num_cs);
 383
 384         dws->num_cs = num_cs;
 385
 386         init_func = device_get_match_data(&pdev->dev);
 387         if (init_func) {
 388                 ret = init_func(pdev, dwsmmio);
 389                 if (ret)
 390                         goto out;
 391         }
 392
 393         pm_runtime_enable(&pdev->dev);
 394
 395         ret = dw_spi_add_host(&pdev->dev, dws);
 396         if (ret)
 397                 goto out;
 398
 399         platform_set_drvdata(pdev, dwsmmio);
 400         return 0;
 401
 402 out:
 403         pm_runtime_disable(&pdev->dev);
 404         clk_disable_unprepare(dwsmmio->pclk);
 405 out_clk:
 406         clk_disable_unprepare(dwsmmio->clk);
 407         reset_control_assert(dwsmmio->rstc);
 408
 409         return ret;
 410 }
 411
 412 static void dw_spi_mmio_remove(struct platform_device *pdev)
 413 {
 414         struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
 415
 416         dw_spi_remove_host(&dwsmmio->dws);
 417         pm_runtime_disable(&pdev->dev);
 418         clk_disable_unprepare(dwsmmio->pclk);
 419         clk_disable_unprepare(dwsmmio->clk);
 420         reset_control_assert(dwsmmio->rstc);
 421 }
 422
 423 static const struct of_device_id dw_spi_mmio_of_match[] = {
 424         { .compatible = "snps,dw-apb-ssi", .data = dw_spi_pssi_init},
 425         { .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
 426         { .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
 427         { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
 428         { .compatible = "renesas,rzn1-spi", .data = dw_spi_pssi_init},
 429         { .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_hssi_init},
 430         { .compatible = "intel,keembay-ssi", .data = dw_spi_intel_init},
 431         { .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init},
 432         {
 433                 .compatible = "intel,mountevans-imc-ssi",
 434                 .data = dw_spi_mountevans_imc_init,
 435         },
 436         { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
 437         { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
 438         { .compatible = "amd,pensando-elba-spi", .data = dw_spi_elba_init},
 439         { /* end of table */}
 440 };
 441 MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
 442
 443 #ifdef CONFIG_ACPI
 444 static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
 445         {"HISI0173", (kernel_ulong_t)dw_spi_pssi_init},
 446         {},
 447 };
 448 MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
 449 #endif
 450
 451 static struct platform_driver dw_spi_mmio_driver = {
 452         .probe          = dw_spi_mmio_probe,
 453         .remove_new     = dw_spi_mmio_remove,
 454         .driver         = {
 455                 .name   = DRIVER_NAME,
 456                 .of_match_table = dw_spi_mmio_of_match,
 457                 .acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
 458         },
 459 };
 460 module_platform_driver(dw_spi_mmio_driver);
 461
 462 MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
 463 MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
 464 MODULE_LICENSE("GPL v2");
 465 MODULE_IMPORT_NS(SPI_DW_CORE);