1 // SPDX-License-Identifier: GPL-2.0-only
3 * Special handling for DW core on Intel MID platform
5 * Copyright (c) 2009, 2014 Intel Corporation.
8 #include <linux/dma-mapping.h>
9 #include <linux/dmaengine.h>
10 #include <linux/interrupt.h>
11 #include <linux/slab.h>
12 #include <linux/spi/spi.h>
13 #include <linux/types.h>
17 #ifdef CONFIG_SPI_DW_MID_DMA
18 #include <linux/pci.h>
19 #include <linux/platform_data/dma-dw.h>
24 static struct dw_dma_slave mid_dma_tx = { .dst_id = 1 };
25 static struct dw_dma_slave mid_dma_rx = { .src_id = 0 };
27 static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
29 struct dw_dma_slave *s = param;
31 if (s->dma_dev != chan->device->dev)
38 static int mid_spi_dma_init(struct dw_spi *dws)
40 struct pci_dev *dma_dev;
41 struct dw_dma_slave *tx = dws->dma_tx;
42 struct dw_dma_slave *rx = dws->dma_rx;
46 * Get pci device for DMA controller, currently it could only
47 * be the DMA controller of Medfield
49 dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
54 dma_cap_set(DMA_SLAVE, mask);
56 /* 1. Init rx channel */
57 rx->dma_dev = &dma_dev->dev;
58 dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, rx);
61 dws->master->dma_rx = dws->rxchan;
63 /* 2. Init tx channel */
64 tx->dma_dev = &dma_dev->dev;
65 dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, tx);
68 dws->master->dma_tx = dws->txchan;
74 dma_release_channel(dws->rxchan);
79 static void mid_spi_dma_exit(struct dw_spi *dws)
84 dmaengine_terminate_sync(dws->txchan);
85 dma_release_channel(dws->txchan);
87 dmaengine_terminate_sync(dws->rxchan);
88 dma_release_channel(dws->rxchan);
91 static irqreturn_t dma_transfer(struct dw_spi *dws)
93 u16 irq_status = dw_readl(dws, DW_SPI_ISR);
98 dw_readl(dws, DW_SPI_ICR);
101 dev_err(&dws->master->dev, "%s: FIFO overrun/underrun\n", __func__);
102 dws->master->cur_msg->status = -EIO;
103 spi_finalize_current_transfer(dws->master);
107 static bool mid_spi_can_dma(struct spi_controller *master,
108 struct spi_device *spi, struct spi_transfer *xfer)
110 struct dw_spi *dws = spi_controller_get_devdata(master);
112 if (!dws->dma_inited)
115 return xfer->len > dws->fifo_len;
118 static enum dma_slave_buswidth convert_dma_width(u32 dma_width) {
120 return DMA_SLAVE_BUSWIDTH_1_BYTE;
121 else if (dma_width == 2)
122 return DMA_SLAVE_BUSWIDTH_2_BYTES;
124 return DMA_SLAVE_BUSWIDTH_UNDEFINED;
128 * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
129 * channel will clear a corresponding bit.
131 static void dw_spi_dma_tx_done(void *arg)
133 struct dw_spi *dws = arg;
135 clear_bit(TX_BUSY, &dws->dma_chan_busy);
136 if (test_bit(RX_BUSY, &dws->dma_chan_busy))
138 spi_finalize_current_transfer(dws->master);
141 static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
142 struct spi_transfer *xfer)
144 struct dma_slave_config txconf;
145 struct dma_async_tx_descriptor *txdesc;
150 memset(&txconf, 0, sizeof(txconf));
151 txconf.direction = DMA_MEM_TO_DEV;
152 txconf.dst_addr = dws->dma_addr;
153 txconf.dst_maxburst = 16;
154 txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
155 txconf.dst_addr_width = convert_dma_width(dws->dma_width);
156 txconf.device_fc = false;
158 dmaengine_slave_config(dws->txchan, &txconf);
160 txdesc = dmaengine_prep_slave_sg(dws->txchan,
164 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
168 txdesc->callback = dw_spi_dma_tx_done;
169 txdesc->callback_param = dws;
175 * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
176 * channel will clear a corresponding bit.
178 static void dw_spi_dma_rx_done(void *arg)
180 struct dw_spi *dws = arg;
182 clear_bit(RX_BUSY, &dws->dma_chan_busy);
183 if (test_bit(TX_BUSY, &dws->dma_chan_busy))
185 spi_finalize_current_transfer(dws->master);
188 static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
189 struct spi_transfer *xfer)
191 struct dma_slave_config rxconf;
192 struct dma_async_tx_descriptor *rxdesc;
197 memset(&rxconf, 0, sizeof(rxconf));
198 rxconf.direction = DMA_DEV_TO_MEM;
199 rxconf.src_addr = dws->dma_addr;
200 rxconf.src_maxburst = 16;
201 rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
202 rxconf.src_addr_width = convert_dma_width(dws->dma_width);
203 rxconf.device_fc = false;
205 dmaengine_slave_config(dws->rxchan, &rxconf);
207 rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
211 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
215 rxdesc->callback = dw_spi_dma_rx_done;
216 rxdesc->callback_param = dws;
221 static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
223 u16 imr = 0, dma_ctrl = 0;
225 dw_writel(dws, DW_SPI_DMARDLR, 0xf);
226 dw_writel(dws, DW_SPI_DMATDLR, 0x10);
229 dma_ctrl |= SPI_DMA_TDMAE;
233 dma_ctrl |= SPI_DMA_RDMAE;
234 imr |= SPI_INT_RXUI | SPI_INT_RXOI;
236 dw_writel(dws, DW_SPI_DMACR, dma_ctrl);
238 /* Set the interrupt mask */
239 spi_umask_intr(dws, imr);
241 dws->transfer_handler = dma_transfer;
246 static int mid_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
248 struct dma_async_tx_descriptor *txdesc, *rxdesc;
250 /* Prepare the TX dma transfer */
251 txdesc = dw_spi_dma_prepare_tx(dws, xfer);
253 /* Prepare the RX dma transfer */
254 rxdesc = dw_spi_dma_prepare_rx(dws, xfer);
256 /* rx must be started before tx due to spi instinct */
258 set_bit(RX_BUSY, &dws->dma_chan_busy);
259 dmaengine_submit(rxdesc);
260 dma_async_issue_pending(dws->rxchan);
264 set_bit(TX_BUSY, &dws->dma_chan_busy);
265 dmaengine_submit(txdesc);
266 dma_async_issue_pending(dws->txchan);
272 static void mid_spi_dma_stop(struct dw_spi *dws)
274 if (test_bit(TX_BUSY, &dws->dma_chan_busy)) {
275 dmaengine_terminate_sync(dws->txchan);
276 clear_bit(TX_BUSY, &dws->dma_chan_busy);
278 if (test_bit(RX_BUSY, &dws->dma_chan_busy)) {
279 dmaengine_terminate_sync(dws->rxchan);
280 clear_bit(RX_BUSY, &dws->dma_chan_busy);
284 static const struct dw_spi_dma_ops mid_dma_ops = {
285 .dma_init = mid_spi_dma_init,
286 .dma_exit = mid_spi_dma_exit,
287 .dma_setup = mid_spi_dma_setup,
288 .can_dma = mid_spi_can_dma,
289 .dma_transfer = mid_spi_dma_transfer,
290 .dma_stop = mid_spi_dma_stop,
294 /* Some specific info for SPI0 controller on Intel MID */
296 /* HW info for MRST Clk Control Unit, 32b reg per controller */
297 #define MRST_SPI_CLK_BASE 100000000 /* 100m */
298 #define MRST_CLK_SPI_REG 0xff11d86c
299 #define CLK_SPI_BDIV_OFFSET 0
300 #define CLK_SPI_BDIV_MASK 0x00000007
301 #define CLK_SPI_CDIV_OFFSET 9
302 #define CLK_SPI_CDIV_MASK 0x00000e00
303 #define CLK_SPI_DISABLE_OFFSET 8
305 int dw_spi_mid_init(struct dw_spi *dws)
307 void __iomem *clk_reg;
310 clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
314 /* Get SPI controller operating freq info */
315 clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
316 clk_cdiv &= CLK_SPI_CDIV_MASK;
317 clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
318 dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
322 #ifdef CONFIG_SPI_DW_MID_DMA
323 dws->dma_tx = &mid_dma_tx;
324 dws->dma_rx = &mid_dma_rx;
325 dws->dma_ops = &mid_dma_ops;