drivers/spi/spi-dw-mid.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Special handling for DW core on Intel MID platform
   4  *
   5  * Copyright (c) 2009, 2014 Intel Corporation.
   6  */
   7
   8 #include <linux/dma-mapping.h>
   9 #include <linux/dmaengine.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/slab.h>
  12 #include <linux/spi/spi.h>
  13 #include <linux/types.h>
  14
  15 #include "spi-dw.h"
  16
  17 #ifdef CONFIG_SPI_DW_MID_DMA
  18 #include <linux/pci.h>
  19 #include <linux/platform_data/dma-dw.h>
  20
  21 #define RX_BUSY         0
  22 #define TX_BUSY         1
  23
  24 static struct dw_dma_slave mid_dma_tx = { .dst_id = 1 };
  25 static struct dw_dma_slave mid_dma_rx = { .src_id = 0 };
  26
  27 static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
  28 {
  29         struct dw_dma_slave *s = param;
  30
  31         if (s->dma_dev != chan->device->dev)
  32                 return false;
  33
  34         chan->private = s;
  35         return true;
  36 }
  37
  38 static int mid_spi_dma_init(struct dw_spi *dws)
  39 {
  40         struct pci_dev *dma_dev;
  41         struct dw_dma_slave *tx = dws->dma_tx;
  42         struct dw_dma_slave *rx = dws->dma_rx;
  43         dma_cap_mask_t mask;
  44
  45         /*
  46          * Get pci device for DMA controller, currently it could only
  47          * be the DMA controller of Medfield
  48          */
  49         dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
  50         if (!dma_dev)
  51                 return -ENODEV;
  52
  53         dma_cap_zero(mask);
  54         dma_cap_set(DMA_SLAVE, mask);
  55
  56         /* 1. Init rx channel */
  57         rx->dma_dev = &dma_dev->dev;
  58         dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, rx);
  59         if (!dws->rxchan)
  60                 goto err_exit;
  61         dws->master->dma_rx = dws->rxchan;
  62
  63         /* 2. Init tx channel */
  64         tx->dma_dev = &dma_dev->dev;
  65         dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, tx);
  66         if (!dws->txchan)
  67                 goto free_rxchan;
  68         dws->master->dma_tx = dws->txchan;
  69
  70         dws->dma_inited = 1;
  71         return 0;
  72
  73 free_rxchan:
  74         dma_release_channel(dws->rxchan);
  75 err_exit:
  76         return -EBUSY;
  77 }
  78
  79 static void mid_spi_dma_exit(struct dw_spi *dws)
  80 {
  81         if (!dws->dma_inited)
  82                 return;
  83
  84         dmaengine_terminate_sync(dws->txchan);
  85         dma_release_channel(dws->txchan);
  86
  87         dmaengine_terminate_sync(dws->rxchan);
  88         dma_release_channel(dws->rxchan);
  89 }
  90
  91 static irqreturn_t dma_transfer(struct dw_spi *dws)
  92 {
  93         u16 irq_status = dw_readl(dws, DW_SPI_ISR);
  94
  95         if (!irq_status)
  96                 return IRQ_NONE;
  97
  98         dw_readl(dws, DW_SPI_ICR);
  99         spi_reset_chip(dws);
 100
 101         dev_err(&dws->master->dev, "%s: FIFO overrun/underrun\n", __func__);
 102         dws->master->cur_msg->status = -EIO;
 103         spi_finalize_current_transfer(dws->master);
 104         return IRQ_HANDLED;
 105 }
 106
 107 static bool mid_spi_can_dma(struct spi_controller *master,
 108                 struct spi_device *spi, struct spi_transfer *xfer)
 109 {
 110         struct dw_spi *dws = spi_controller_get_devdata(master);
 111
 112         if (!dws->dma_inited)
 113                 return false;
 114
 115         return xfer->len > dws->fifo_len;
 116 }
 117
 118 static enum dma_slave_buswidth convert_dma_width(u32 dma_width) {
 119         if (dma_width == 1)
 120                 return DMA_SLAVE_BUSWIDTH_1_BYTE;
 121         else if (dma_width == 2)
 122                 return DMA_SLAVE_BUSWIDTH_2_BYTES;
 123
 124         return DMA_SLAVE_BUSWIDTH_UNDEFINED;
 125 }
 126
 127 /*
 128  * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
 129  * channel will clear a corresponding bit.
 130  */
 131 static void dw_spi_dma_tx_done(void *arg)
 132 {
 133         struct dw_spi *dws = arg;
 134
 135         clear_bit(TX_BUSY, &dws->dma_chan_busy);
 136         if (test_bit(RX_BUSY, &dws->dma_chan_busy))
 137                 return;
 138         spi_finalize_current_transfer(dws->master);
 139 }
 140
 141 static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
 142                 struct spi_transfer *xfer)
 143 {
 144         struct dma_slave_config txconf;
 145         struct dma_async_tx_descriptor *txdesc;
 146
 147         if (!xfer->tx_buf)
 148                 return NULL;
 149
 150         memset(&txconf, 0, sizeof(txconf));
 151         txconf.direction = DMA_MEM_TO_DEV;
 152         txconf.dst_addr = dws->dma_addr;
 153         txconf.dst_maxburst = 16;
 154         txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 155         txconf.dst_addr_width = convert_dma_width(dws->dma_width);
 156         txconf.device_fc = false;
 157
 158         dmaengine_slave_config(dws->txchan, &txconf);
 159
 160         txdesc = dmaengine_prep_slave_sg(dws->txchan,
 161                                 xfer->tx_sg.sgl,
 162                                 xfer->tx_sg.nents,
 163                                 DMA_MEM_TO_DEV,
 164                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 165         if (!txdesc)
 166                 return NULL;
 167
 168         txdesc->callback = dw_spi_dma_tx_done;
 169         txdesc->callback_param = dws;
 170
 171         return txdesc;
 172 }
 173
 174 /*
 175  * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
 176  * channel will clear a corresponding bit.
 177  */
 178 static void dw_spi_dma_rx_done(void *arg)
 179 {
 180         struct dw_spi *dws = arg;
 181
 182         clear_bit(RX_BUSY, &dws->dma_chan_busy);
 183         if (test_bit(TX_BUSY, &dws->dma_chan_busy))
 184                 return;
 185         spi_finalize_current_transfer(dws->master);
 186 }
 187
 188 static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
 189                 struct spi_transfer *xfer)
 190 {
 191         struct dma_slave_config rxconf;
 192         struct dma_async_tx_descriptor *rxdesc;
 193
 194         if (!xfer->rx_buf)
 195                 return NULL;
 196
 197         memset(&rxconf, 0, sizeof(rxconf));
 198         rxconf.direction = DMA_DEV_TO_MEM;
 199         rxconf.src_addr = dws->dma_addr;
 200         rxconf.src_maxburst = 16;
 201         rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 202         rxconf.src_addr_width = convert_dma_width(dws->dma_width);
 203         rxconf.device_fc = false;
 204
 205         dmaengine_slave_config(dws->rxchan, &rxconf);
 206
 207         rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
 208                                 xfer->rx_sg.sgl,
 209                                 xfer->rx_sg.nents,
 210                                 DMA_DEV_TO_MEM,
 211                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 212         if (!rxdesc)
 213                 return NULL;
 214
 215         rxdesc->callback = dw_spi_dma_rx_done;
 216         rxdesc->callback_param = dws;
 217
 218         return rxdesc;
 219 }
 220
 221 static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
 222 {
 223         u16 imr = 0, dma_ctrl = 0;
 224
 225         dw_writel(dws, DW_SPI_DMARDLR, 0xf);
 226         dw_writel(dws, DW_SPI_DMATDLR, 0x10);
 227
 228         if (xfer->tx_buf) {
 229                 dma_ctrl |= SPI_DMA_TDMAE;
 230                 imr |= SPI_INT_TXOI;
 231         }
 232         if (xfer->rx_buf) {
 233                 dma_ctrl |= SPI_DMA_RDMAE;
 234                 imr |= SPI_INT_RXUI | SPI_INT_RXOI;
 235         }
 236         dw_writel(dws, DW_SPI_DMACR, dma_ctrl);
 237
 238         /* Set the interrupt mask */
 239         spi_umask_intr(dws, imr);
 240
 241         dws->transfer_handler = dma_transfer;
 242
 243         return 0;
 244 }
 245
 246 static int mid_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
 247 {
 248         struct dma_async_tx_descriptor *txdesc, *rxdesc;
 249
 250         /* Prepare the TX dma transfer */
 251         txdesc = dw_spi_dma_prepare_tx(dws, xfer);
 252
 253         /* Prepare the RX dma transfer */
 254         rxdesc = dw_spi_dma_prepare_rx(dws, xfer);
 255
 256         /* rx must be started before tx due to spi instinct */
 257         if (rxdesc) {
 258                 set_bit(RX_BUSY, &dws->dma_chan_busy);
 259                 dmaengine_submit(rxdesc);
 260                 dma_async_issue_pending(dws->rxchan);
 261         }
 262
 263         if (txdesc) {
 264                 set_bit(TX_BUSY, &dws->dma_chan_busy);
 265                 dmaengine_submit(txdesc);
 266                 dma_async_issue_pending(dws->txchan);
 267         }
 268
 269         return 1;
 270 }
 271
 272 static void mid_spi_dma_stop(struct dw_spi *dws)
 273 {
 274         if (test_bit(TX_BUSY, &dws->dma_chan_busy)) {
 275                 dmaengine_terminate_sync(dws->txchan);
 276                 clear_bit(TX_BUSY, &dws->dma_chan_busy);
 277         }
 278         if (test_bit(RX_BUSY, &dws->dma_chan_busy)) {
 279                 dmaengine_terminate_sync(dws->rxchan);
 280                 clear_bit(RX_BUSY, &dws->dma_chan_busy);
 281         }
 282 }
 283
 284 static const struct dw_spi_dma_ops mid_dma_ops = {
 285         .dma_init       = mid_spi_dma_init,
 286         .dma_exit       = mid_spi_dma_exit,
 287         .dma_setup      = mid_spi_dma_setup,
 288         .can_dma        = mid_spi_can_dma,
 289         .dma_transfer   = mid_spi_dma_transfer,
 290         .dma_stop       = mid_spi_dma_stop,
 291 };
 292 #endif
 293
 294 /* Some specific info for SPI0 controller on Intel MID */
 295
 296 /* HW info for MRST Clk Control Unit, 32b reg per controller */
 297 #define MRST_SPI_CLK_BASE       100000000       /* 100m */
 298 #define MRST_CLK_SPI_REG        0xff11d86c
 299 #define CLK_SPI_BDIV_OFFSET     0
 300 #define CLK_SPI_BDIV_MASK       0x00000007
 301 #define CLK_SPI_CDIV_OFFSET     9
 302 #define CLK_SPI_CDIV_MASK       0x00000e00
 303 #define CLK_SPI_DISABLE_OFFSET  8
 304
 305 int dw_spi_mid_init(struct dw_spi *dws)
 306 {
 307         void __iomem *clk_reg;
 308         u32 clk_cdiv;
 309
 310         clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
 311         if (!clk_reg)
 312                 return -ENOMEM;
 313
 314         /* Get SPI controller operating freq info */
 315         clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
 316         clk_cdiv &= CLK_SPI_CDIV_MASK;
 317         clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
 318         dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
 319
 320         iounmap(clk_reg);
 321
 322 #ifdef CONFIG_SPI_DW_MID_DMA
 323         dws->dma_tx = &mid_dma_tx;
 324         dws->dma_rx = &mid_dma_rx;
 325         dws->dma_ops = &mid_dma_ops;
 326 #endif
 327         return 0;
 328 }