drivers/spi/spi-dw-core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Designware SPI core controller driver (refer pxa2xx_spi.c)
   4  *
   5  * Copyright (c) 2009, Intel Corporation.
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/module.h>
  12 #include <linux/preempt.h>
  13 #include <linux/highmem.h>
  14 #include <linux/delay.h>
  15 #include <linux/slab.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/spi/spi-mem.h>
  18 #include <linux/string.h>
  19 #include <linux/of.h>
  20
  21 #include "spi-dw.h"
  22
  23 #ifdef CONFIG_DEBUG_FS
  24 #include <linux/debugfs.h>
  25 #endif
  26
  27 /* Slave spi_device related */
  28 struct dw_spi_chip_data {
  29         u32 cr0;
  30         u32 rx_sample_dly;      /* RX sample delay */
  31 };
  32
  33 #ifdef CONFIG_DEBUG_FS
  34
  35 #define DW_SPI_DBGFS_REG(_name, _off)   \
  36 {                                       \
  37         .name = _name,                  \
  38         .offset = _off,                 \
  39 }
  40
  41 static const struct debugfs_reg32 dw_spi_dbgfs_regs[] = {
  42         DW_SPI_DBGFS_REG("CTRLR0", DW_SPI_CTRLR0),
  43         DW_SPI_DBGFS_REG("CTRLR1", DW_SPI_CTRLR1),
  44         DW_SPI_DBGFS_REG("SSIENR", DW_SPI_SSIENR),
  45         DW_SPI_DBGFS_REG("SER", DW_SPI_SER),
  46         DW_SPI_DBGFS_REG("BAUDR", DW_SPI_BAUDR),
  47         DW_SPI_DBGFS_REG("TXFTLR", DW_SPI_TXFTLR),
  48         DW_SPI_DBGFS_REG("RXFTLR", DW_SPI_RXFTLR),
  49         DW_SPI_DBGFS_REG("TXFLR", DW_SPI_TXFLR),
  50         DW_SPI_DBGFS_REG("RXFLR", DW_SPI_RXFLR),
  51         DW_SPI_DBGFS_REG("SR", DW_SPI_SR),
  52         DW_SPI_DBGFS_REG("IMR", DW_SPI_IMR),
  53         DW_SPI_DBGFS_REG("ISR", DW_SPI_ISR),
  54         DW_SPI_DBGFS_REG("DMACR", DW_SPI_DMACR),
  55         DW_SPI_DBGFS_REG("DMATDLR", DW_SPI_DMATDLR),
  56         DW_SPI_DBGFS_REG("DMARDLR", DW_SPI_DMARDLR),
  57         DW_SPI_DBGFS_REG("RX_SAMPLE_DLY", DW_SPI_RX_SAMPLE_DLY),
  58 };
  59
  60 static void dw_spi_debugfs_init(struct dw_spi *dws)
  61 {
  62         char name[32];
  63
  64         snprintf(name, 32, "dw_spi%d", dws->host->bus_num);
  65         dws->debugfs = debugfs_create_dir(name, NULL);
  66
  67         dws->regset.regs = dw_spi_dbgfs_regs;
  68         dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs);
  69         dws->regset.base = dws->regs;
  70         debugfs_create_regset32("registers", 0400, dws->debugfs, &dws->regset);
  71 }
  72
  73 static void dw_spi_debugfs_remove(struct dw_spi *dws)
  74 {
  75         debugfs_remove_recursive(dws->debugfs);
  76 }
  77
  78 #else
  79 static inline void dw_spi_debugfs_init(struct dw_spi *dws)
  80 {
  81 }
  82
  83 static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
  84 {
  85 }
  86 #endif /* CONFIG_DEBUG_FS */
  87
  88 void dw_spi_set_cs(struct spi_device *spi, bool enable)
  89 {
  90         struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
  91         bool cs_high = !!(spi->mode & SPI_CS_HIGH);
  92
  93         /*
  94          * DW SPI controller demands any native CS being set in order to
  95          * proceed with data transfer. So in order to activate the SPI
  96          * communications we must set a corresponding bit in the Slave
  97          * Enable register no matter whether the SPI core is configured to
  98          * support active-high or active-low CS level.
  99          */
 100         if (cs_high == enable)
 101                 dw_writel(dws, DW_SPI_SER, BIT(spi_get_chipselect(spi, 0)));
 102         else
 103                 dw_writel(dws, DW_SPI_SER, 0);
 104 }
 105 EXPORT_SYMBOL_NS_GPL(dw_spi_set_cs, SPI_DW_CORE);
 106
 107 /* Return the max entries we can fill into tx fifo */
 108 static inline u32 dw_spi_tx_max(struct dw_spi *dws)
 109 {
 110         u32 tx_room, rxtx_gap;
 111
 112         tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
 113
 114         /*
 115          * Another concern is about the tx/rx mismatch, we
 116          * though to use (dws->fifo_len - rxflr - txflr) as
 117          * one maximum value for tx, but it doesn't cover the
 118          * data which is out of tx/rx fifo and inside the
 119          * shift registers. So a control from sw point of
 120          * view is taken.
 121          */
 122         rxtx_gap = dws->fifo_len - (dws->rx_len - dws->tx_len);
 123
 124         return min3((u32)dws->tx_len, tx_room, rxtx_gap);
 125 }
 126
 127 /* Return the max entries we should read out of rx fifo */
 128 static inline u32 dw_spi_rx_max(struct dw_spi *dws)
 129 {
 130         return min_t(u32, dws->rx_len, dw_readl(dws, DW_SPI_RXFLR));
 131 }
 132
 133 static void dw_writer(struct dw_spi *dws)
 134 {
 135         u32 max = dw_spi_tx_max(dws);
 136         u32 txw = 0;
 137
 138         while (max--) {
 139                 if (dws->tx) {
 140                         if (dws->n_bytes == 1)
 141                                 txw = *(u8 *)(dws->tx);
 142                         else if (dws->n_bytes == 2)
 143                                 txw = *(u16 *)(dws->tx);
 144                         else
 145                                 txw = *(u32 *)(dws->tx);
 146
 147                         dws->tx += dws->n_bytes;
 148                 }
 149                 dw_write_io_reg(dws, DW_SPI_DR, txw);
 150                 --dws->tx_len;
 151         }
 152 }
 153
 154 static void dw_reader(struct dw_spi *dws)
 155 {
 156         u32 max = dw_spi_rx_max(dws);
 157         u32 rxw;
 158
 159         while (max--) {
 160                 rxw = dw_read_io_reg(dws, DW_SPI_DR);
 161                 if (dws->rx) {
 162                         if (dws->n_bytes == 1)
 163                                 *(u8 *)(dws->rx) = rxw;
 164                         else if (dws->n_bytes == 2)
 165                                 *(u16 *)(dws->rx) = rxw;
 166                         else
 167                                 *(u32 *)(dws->rx) = rxw;
 168
 169                         dws->rx += dws->n_bytes;
 170                 }
 171                 --dws->rx_len;
 172         }
 173 }
 174
 175 int dw_spi_check_status(struct dw_spi *dws, bool raw)
 176 {
 177         u32 irq_status;
 178         int ret = 0;
 179
 180         if (raw)
 181                 irq_status = dw_readl(dws, DW_SPI_RISR);
 182         else
 183                 irq_status = dw_readl(dws, DW_SPI_ISR);
 184
 185         if (irq_status & DW_SPI_INT_RXOI) {
 186                 dev_err(&dws->host->dev, "RX FIFO overflow detected\n");
 187                 ret = -EIO;
 188         }
 189
 190         if (irq_status & DW_SPI_INT_RXUI) {
 191                 dev_err(&dws->host->dev, "RX FIFO underflow detected\n");
 192                 ret = -EIO;
 193         }
 194
 195         if (irq_status & DW_SPI_INT_TXOI) {
 196                 dev_err(&dws->host->dev, "TX FIFO overflow detected\n");
 197                 ret = -EIO;
 198         }
 199
 200         /* Generically handle the erroneous situation */
 201         if (ret) {
 202                 dw_spi_reset_chip(dws);
 203                 if (dws->host->cur_msg)
 204                         dws->host->cur_msg->status = ret;
 205         }
 206
 207         return ret;
 208 }
 209 EXPORT_SYMBOL_NS_GPL(dw_spi_check_status, SPI_DW_CORE);
 210
 211 static irqreturn_t dw_spi_transfer_handler(struct dw_spi *dws)
 212 {
 213         u16 irq_status = dw_readl(dws, DW_SPI_ISR);
 214
 215         if (dw_spi_check_status(dws, false)) {
 216                 spi_finalize_current_transfer(dws->host);
 217                 return IRQ_HANDLED;
 218         }
 219
 220         /*
 221          * Read data from the Rx FIFO every time we've got a chance executing
 222          * this method. If there is nothing left to receive, terminate the
 223          * procedure. Otherwise adjust the Rx FIFO Threshold level if it's a
 224          * final stage of the transfer. By doing so we'll get the next IRQ
 225          * right when the leftover incoming data is received.
 226          */
 227         dw_reader(dws);
 228         if (!dws->rx_len) {
 229                 dw_spi_mask_intr(dws, 0xff);
 230                 spi_finalize_current_transfer(dws->host);
 231         } else if (dws->rx_len <= dw_readl(dws, DW_SPI_RXFTLR)) {
 232                 dw_writel(dws, DW_SPI_RXFTLR, dws->rx_len - 1);
 233         }
 234
 235         /*
 236          * Send data out if Tx FIFO Empty IRQ is received. The IRQ will be
 237          * disabled after the data transmission is finished so not to
 238          * have the TXE IRQ flood at the final stage of the transfer.
 239          */
 240         if (irq_status & DW_SPI_INT_TXEI) {
 241                 dw_writer(dws);
 242                 if (!dws->tx_len) {
 243                         dw_spi_mask_intr(dws, DW_SPI_INT_TXEI);
 244                         if (!dws->rx_len)
 245                                 spi_finalize_current_transfer(dws->host);
 246                 }
 247         }
 248
 249         return IRQ_HANDLED;
 250 }
 251
 252 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 253 {
 254         struct spi_controller *host = dev_id;
 255         struct dw_spi *dws = spi_controller_get_devdata(host);
 256         u16 irq_status = dw_readl(dws, DW_SPI_ISR) & DW_SPI_INT_MASK;
 257
 258         if (!irq_status)
 259                 return IRQ_NONE;
 260
 261         if (!host->cur_msg) {
 262                 dw_spi_mask_intr(dws, 0xff);
 263                 return IRQ_HANDLED;
 264         }
 265
 266         return dws->transfer_handler(dws);
 267 }
 268
 269 static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi)
 270 {
 271         u32 cr0 = 0;
 272
 273         if (dw_spi_ip_is(dws, PSSI)) {
 274                 /* CTRLR0[ 5: 4] Frame Format */
 275                 cr0 |= FIELD_PREP(DW_PSSI_CTRLR0_FRF_MASK, DW_SPI_CTRLR0_FRF_MOTO_SPI);
 276
 277                 /*
 278                  * SPI mode (SCPOL|SCPH)
 279                  * CTRLR0[ 6] Serial Clock Phase
 280                  * CTRLR0[ 7] Serial Clock Polarity
 281                  */
 282                 if (spi->mode & SPI_CPOL)
 283                         cr0 |= DW_PSSI_CTRLR0_SCPOL;
 284                 if (spi->mode & SPI_CPHA)
 285                         cr0 |= DW_PSSI_CTRLR0_SCPHA;
 286
 287                 /* CTRLR0[11] Shift Register Loop */
 288                 if (spi->mode & SPI_LOOP)
 289                         cr0 |= DW_PSSI_CTRLR0_SRL;
 290         } else {
 291                 /* CTRLR0[ 7: 6] Frame Format */
 292                 cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_FRF_MASK, DW_SPI_CTRLR0_FRF_MOTO_SPI);
 293
 294                 /*
 295                  * SPI mode (SCPOL|SCPH)
 296                  * CTRLR0[ 8] Serial Clock Phase
 297                  * CTRLR0[ 9] Serial Clock Polarity
 298                  */
 299                 if (spi->mode & SPI_CPOL)
 300                         cr0 |= DW_HSSI_CTRLR0_SCPOL;
 301                 if (spi->mode & SPI_CPHA)
 302                         cr0 |= DW_HSSI_CTRLR0_SCPHA;
 303
 304                 /* CTRLR0[13] Shift Register Loop */
 305                 if (spi->mode & SPI_LOOP)
 306                         cr0 |= DW_HSSI_CTRLR0_SRL;
 307
 308                 /* CTRLR0[31] MST */
 309                 if (dw_spi_ver_is_ge(dws, HSSI, 102A))
 310                         cr0 |= DW_HSSI_CTRLR0_MST;
 311         }
 312
 313         return cr0;
 314 }
 315
 316 void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
 317                           struct dw_spi_cfg *cfg)
 318 {
 319         struct dw_spi_chip_data *chip = spi_get_ctldata(spi);
 320         u32 cr0 = chip->cr0;
 321         u32 speed_hz;
 322         u16 clk_div;
 323
 324         /* CTRLR0[ 4/3: 0] or CTRLR0[ 20: 16] Data Frame Size */
 325         cr0 |= (cfg->dfs - 1) << dws->dfs_offset;
 326
 327         if (dw_spi_ip_is(dws, PSSI))
 328                 /* CTRLR0[ 9:8] Transfer Mode */
 329                 cr0 |= FIELD_PREP(DW_PSSI_CTRLR0_TMOD_MASK, cfg->tmode);
 330         else
 331                 /* CTRLR0[11:10] Transfer Mode */
 332                 cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_TMOD_MASK, cfg->tmode);
 333
 334         dw_writel(dws, DW_SPI_CTRLR0, cr0);
 335
 336         if (cfg->tmode == DW_SPI_CTRLR0_TMOD_EPROMREAD ||
 337             cfg->tmode == DW_SPI_CTRLR0_TMOD_RO)
 338                 dw_writel(dws, DW_SPI_CTRLR1, cfg->ndf ? cfg->ndf - 1 : 0);
 339
 340         /* Note DW APB SSI clock divider doesn't support odd numbers */
 341         clk_div = (DIV_ROUND_UP(dws->max_freq, cfg->freq) + 1) & 0xfffe;
 342         speed_hz = dws->max_freq / clk_div;
 343
 344         if (dws->current_freq != speed_hz) {
 345                 dw_spi_set_clk(dws, clk_div);
 346                 dws->current_freq = speed_hz;
 347         }
 348
 349         /* Update RX sample delay if required */
 350         if (dws->cur_rx_sample_dly != chip->rx_sample_dly) {
 351                 dw_writel(dws, DW_SPI_RX_SAMPLE_DLY, chip->rx_sample_dly);
 352                 dws->cur_rx_sample_dly = chip->rx_sample_dly;
 353         }
 354 }
 355 EXPORT_SYMBOL_NS_GPL(dw_spi_update_config, SPI_DW_CORE);
 356
 357 static void dw_spi_irq_setup(struct dw_spi *dws)
 358 {
 359         u16 level;
 360         u8 imask;
 361
 362         /*
 363          * Originally Tx and Rx data lengths match. Rx FIFO Threshold level
 364          * will be adjusted at the final stage of the IRQ-based SPI transfer
 365          * execution so not to lose the leftover of the incoming data.
 366          */
 367         level = min_t(unsigned int, dws->fifo_len / 2, dws->tx_len);
 368         dw_writel(dws, DW_SPI_TXFTLR, level);
 369         dw_writel(dws, DW_SPI_RXFTLR, level - 1);
 370
 371         dws->transfer_handler = dw_spi_transfer_handler;
 372
 373         imask = 0;
 374         if (dws->tx_len)
 375                 imask |= DW_SPI_INT_TXEI | DW_SPI_INT_TXOI;
 376         if (dws->rx_len)
 377                 imask |= DW_SPI_INT_RXUI | DW_SPI_INT_RXOI | DW_SPI_INT_RXFI;
 378         dw_spi_umask_intr(dws, imask);
 379 }
 380
 381 /*
 382  * The iterative procedure of the poll-based transfer is simple: write as much
 383  * as possible to the Tx FIFO, wait until the pending to receive data is ready
 384  * to be read, read it from the Rx FIFO and check whether the performed
 385  * procedure has been successful.
 386  *
 387  * Note this method the same way as the IRQ-based transfer won't work well for
 388  * the SPI devices connected to the controller with native CS due to the
 389  * automatic CS assertion/de-assertion.
 390  */
 391 static int dw_spi_poll_transfer(struct dw_spi *dws,
 392                                 struct spi_transfer *transfer)
 393 {
 394         struct spi_delay delay;
 395         u16 nbits;
 396         int ret;
 397
 398         delay.unit = SPI_DELAY_UNIT_SCK;
 399         nbits = dws->n_bytes * BITS_PER_BYTE;
 400
 401         do {
 402                 dw_writer(dws);
 403
 404                 delay.value = nbits * (dws->rx_len - dws->tx_len);
 405                 spi_delay_exec(&delay, transfer);
 406
 407                 dw_reader(dws);
 408
 409                 ret = dw_spi_check_status(dws, true);
 410                 if (ret)
 411                         return ret;
 412         } while (dws->rx_len);
 413
 414         return 0;
 415 }
 416
 417 static int dw_spi_transfer_one(struct spi_controller *host,
 418                                struct spi_device *spi,
 419                                struct spi_transfer *transfer)
 420 {
 421         struct dw_spi *dws = spi_controller_get_devdata(host);
 422         struct dw_spi_cfg cfg = {
 423                 .tmode = DW_SPI_CTRLR0_TMOD_TR,
 424                 .dfs = transfer->bits_per_word,
 425                 .freq = transfer->speed_hz,
 426         };
 427         int ret;
 428
 429         dws->dma_mapped = 0;
 430         dws->n_bytes =
 431                 roundup_pow_of_two(DIV_ROUND_UP(transfer->bits_per_word,
 432                                                 BITS_PER_BYTE));
 433
 434         dws->tx = (void *)transfer->tx_buf;
 435         dws->tx_len = transfer->len / dws->n_bytes;
 436         dws->rx = transfer->rx_buf;
 437         dws->rx_len = dws->tx_len;
 438
 439         /* Ensure the data above is visible for all CPUs */
 440         smp_mb();
 441
 442         dw_spi_enable_chip(dws, 0);
 443
 444         dw_spi_update_config(dws, spi, &cfg);
 445
 446         transfer->effective_speed_hz = dws->current_freq;
 447
 448         /* Check if current transfer is a DMA transaction */
 449         if (host->can_dma && host->can_dma(host, spi, transfer))
 450                 dws->dma_mapped = host->cur_msg_mapped;
 451
 452         /* For poll mode just disable all interrupts */
 453         dw_spi_mask_intr(dws, 0xff);
 454
 455         if (dws->dma_mapped) {
 456                 ret = dws->dma_ops->dma_setup(dws, transfer);
 457                 if (ret)
 458                         return ret;
 459         }
 460
 461         dw_spi_enable_chip(dws, 1);
 462
 463         if (dws->dma_mapped)
 464                 return dws->dma_ops->dma_transfer(dws, transfer);
 465         else if (dws->irq == IRQ_NOTCONNECTED)
 466                 return dw_spi_poll_transfer(dws, transfer);
 467
 468         dw_spi_irq_setup(dws);
 469
 470         return 1;
 471 }
 472
 473 static void dw_spi_handle_err(struct spi_controller *host,
 474                               struct spi_message *msg)
 475 {
 476         struct dw_spi *dws = spi_controller_get_devdata(host);
 477
 478         if (dws->dma_mapped)
 479                 dws->dma_ops->dma_stop(dws);
 480
 481         dw_spi_reset_chip(dws);
 482 }
 483
 484 static int dw_spi_adjust_mem_op_size(struct spi_mem *mem, struct spi_mem_op *op)
 485 {
 486         if (op->data.dir == SPI_MEM_DATA_IN)
 487                 op->data.nbytes = clamp_val(op->data.nbytes, 0, DW_SPI_NDF_MASK + 1);
 488
 489         return 0;
 490 }
 491
 492 static bool dw_spi_supports_mem_op(struct spi_mem *mem,
 493                                    const struct spi_mem_op *op)
 494 {
 495         if (op->data.buswidth > 1 || op->addr.buswidth > 1 ||
 496             op->dummy.buswidth > 1 || op->cmd.buswidth > 1)
 497                 return false;
 498
 499         return spi_mem_default_supports_op(mem, op);
 500 }
 501
 502 static int dw_spi_init_mem_buf(struct dw_spi *dws, const struct spi_mem_op *op)
 503 {
 504         unsigned int i, j, len;
 505         u8 *out;
 506
 507         /*
 508          * Calculate the total length of the EEPROM command transfer and
 509          * either use the pre-allocated buffer or create a temporary one.
 510          */
 511         len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
 512         if (op->data.dir == SPI_MEM_DATA_OUT)
 513                 len += op->data.nbytes;
 514
 515         if (len <= DW_SPI_BUF_SIZE) {
 516                 out = dws->buf;
 517         } else {
 518                 out = kzalloc(len, GFP_KERNEL);
 519                 if (!out)
 520                         return -ENOMEM;
 521         }
 522
 523         /*
 524          * Collect the operation code, address and dummy bytes into the single
 525          * buffer. If it's a transfer with data to be sent, also copy it into the
 526          * single buffer in order to speed the data transmission up.
 527          */
 528         for (i = 0; i < op->cmd.nbytes; ++i)
 529                 out[i] = DW_SPI_GET_BYTE(op->cmd.opcode, op->cmd.nbytes - i - 1);
 530         for (j = 0; j < op->addr.nbytes; ++i, ++j)
 531                 out[i] = DW_SPI_GET_BYTE(op->addr.val, op->addr.nbytes - j - 1);
 532         for (j = 0; j < op->dummy.nbytes; ++i, ++j)
 533                 out[i] = 0x0;
 534
 535         if (op->data.dir == SPI_MEM_DATA_OUT)
 536                 memcpy(&out[i], op->data.buf.out, op->data.nbytes);
 537
 538         dws->n_bytes = 1;
 539         dws->tx = out;
 540         dws->tx_len = len;
 541         if (op->data.dir == SPI_MEM_DATA_IN) {
 542                 dws->rx = op->data.buf.in;
 543                 dws->rx_len = op->data.nbytes;
 544         } else {
 545                 dws->rx = NULL;
 546                 dws->rx_len = 0;
 547         }
 548
 549         return 0;
 550 }
 551
 552 static void dw_spi_free_mem_buf(struct dw_spi *dws)
 553 {
 554         if (dws->tx != dws->buf)
 555                 kfree(dws->tx);
 556 }
 557
 558 static int dw_spi_write_then_read(struct dw_spi *dws, struct spi_device *spi)
 559 {
 560         u32 room, entries, sts;
 561         unsigned int len;
 562         u8 *buf;
 563
 564         /*
 565          * At initial stage we just pre-fill the Tx FIFO in with no rush,
 566          * since native CS hasn't been enabled yet and the automatic data
 567          * transmission won't start til we do that.
 568          */
 569         len = min(dws->fifo_len, dws->tx_len);
 570         buf = dws->tx;
 571         while (len--)
 572                 dw_write_io_reg(dws, DW_SPI_DR, *buf++);
 573
 574         /*
 575          * After setting any bit in the SER register the transmission will
 576          * start automatically. We have to keep up with that procedure
 577          * otherwise the CS de-assertion will happen whereupon the memory
 578          * operation will be pre-terminated.
 579          */
 580         len = dws->tx_len - ((void *)buf - dws->tx);
 581         dw_spi_set_cs(spi, false);
 582         while (len) {
 583                 entries = readl_relaxed(dws->regs + DW_SPI_TXFLR);
 584                 if (!entries) {
 585                         dev_err(&dws->host->dev, "CS de-assertion on Tx\n");
 586                         return -EIO;
 587                 }
 588                 room = min(dws->fifo_len - entries, len);
 589                 for (; room; --room, --len)
 590                         dw_write_io_reg(dws, DW_SPI_DR, *buf++);
 591         }
 592
 593         /*
 594          * Data fetching will start automatically if the EEPROM-read mode is
 595          * activated. We have to keep up with the incoming data pace to
 596          * prevent the Rx FIFO overflow causing the inbound data loss.
 597          */
 598         len = dws->rx_len;
 599         buf = dws->rx;
 600         while (len) {
 601                 entries = readl_relaxed(dws->regs + DW_SPI_RXFLR);
 602                 if (!entries) {
 603                         sts = readl_relaxed(dws->regs + DW_SPI_RISR);
 604                         if (sts & DW_SPI_INT_RXOI) {
 605                                 dev_err(&dws->host->dev, "FIFO overflow on Rx\n");
 606                                 return -EIO;
 607                         }
 608                         continue;
 609                 }
 610                 entries = min(entries, len);
 611                 for (; entries; --entries, --len)
 612                         *buf++ = dw_read_io_reg(dws, DW_SPI_DR);
 613         }
 614
 615         return 0;
 616 }
 617
 618 static inline bool dw_spi_ctlr_busy(struct dw_spi *dws)
 619 {
 620         return dw_readl(dws, DW_SPI_SR) & DW_SPI_SR_BUSY;
 621 }
 622
 623 static int dw_spi_wait_mem_op_done(struct dw_spi *dws)
 624 {
 625         int retry = DW_SPI_WAIT_RETRIES;
 626         struct spi_delay delay;
 627         unsigned long ns, us;
 628         u32 nents;
 629
 630         nents = dw_readl(dws, DW_SPI_TXFLR);
 631         ns = NSEC_PER_SEC / dws->current_freq * nents;
 632         ns *= dws->n_bytes * BITS_PER_BYTE;
 633         if (ns <= NSEC_PER_USEC) {
 634                 delay.unit = SPI_DELAY_UNIT_NSECS;
 635                 delay.value = ns;
 636         } else {
 637                 us = DIV_ROUND_UP(ns, NSEC_PER_USEC);
 638                 delay.unit = SPI_DELAY_UNIT_USECS;
 639                 delay.value = clamp_val(us, 0, USHRT_MAX);
 640         }
 641
 642         while (dw_spi_ctlr_busy(dws) && retry--)
 643                 spi_delay_exec(&delay, NULL);
 644
 645         if (retry < 0) {
 646                 dev_err(&dws->host->dev, "Mem op hanged up\n");
 647                 return -EIO;
 648         }
 649
 650         return 0;
 651 }
 652
 653 static void dw_spi_stop_mem_op(struct dw_spi *dws, struct spi_device *spi)
 654 {
 655         dw_spi_enable_chip(dws, 0);
 656         dw_spi_set_cs(spi, true);
 657         dw_spi_enable_chip(dws, 1);
 658 }
 659
 660 /*
 661  * The SPI memory operation implementation below is the best choice for the
 662  * devices, which are selected by the native chip-select lane. It's
 663  * specifically developed to workaround the problem with automatic chip-select
 664  * lane toggle when there is no data in the Tx FIFO buffer. Luckily the current
 665  * SPI-mem core calls exec_op() callback only if the GPIO-based CS is
 666  * unavailable.
 667  */
 668 static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
 669 {
 670         struct dw_spi *dws = spi_controller_get_devdata(mem->spi->controller);
 671         struct dw_spi_cfg cfg;
 672         unsigned long flags;
 673         int ret;
 674
 675         /*
 676          * Collect the outbound data into a single buffer to speed the
 677          * transmission up at least on the initial stage.
 678          */
 679         ret = dw_spi_init_mem_buf(dws, op);
 680         if (ret)
 681                 return ret;
 682
 683         /*
 684          * DW SPI EEPROM-read mode is required only for the SPI memory Data-IN
 685          * operation. Transmit-only mode is suitable for the rest of them.
 686          */
 687         cfg.dfs = 8;
 688         cfg.freq = clamp(mem->spi->max_speed_hz, 0U, dws->max_mem_freq);
 689         if (op->data.dir == SPI_MEM_DATA_IN) {
 690                 cfg.tmode = DW_SPI_CTRLR0_TMOD_EPROMREAD;
 691                 cfg.ndf = op->data.nbytes;
 692         } else {
 693                 cfg.tmode = DW_SPI_CTRLR0_TMOD_TO;
 694         }
 695
 696         dw_spi_enable_chip(dws, 0);
 697
 698         dw_spi_update_config(dws, mem->spi, &cfg);
 699
 700         dw_spi_mask_intr(dws, 0xff);
 701
 702         dw_spi_enable_chip(dws, 1);
 703
 704         /*
 705          * DW APB SSI controller has very nasty peculiarities. First originally
 706          * (without any vendor-specific modifications) it doesn't provide a
 707          * direct way to set and clear the native chip-select signal. Instead
 708          * the controller asserts the CS lane if Tx FIFO isn't empty and a
 709          * transmission is going on, and automatically de-asserts it back to
 710          * the high level if the Tx FIFO doesn't have anything to be pushed
 711          * out. Due to that a multi-tasking or heavy IRQs activity might be
 712          * fatal, since the transfer procedure preemption may cause the Tx FIFO
 713          * getting empty and sudden CS de-assertion, which in the middle of the
 714          * transfer will most likely cause the data loss. Secondly the
 715          * EEPROM-read or Read-only DW SPI transfer modes imply the incoming
 716          * data being automatically pulled in into the Rx FIFO. So if the
 717          * driver software is late in fetching the data from the FIFO before
 718          * it's overflown, new incoming data will be lost. In order to make
 719          * sure the executed memory operations are CS-atomic and to prevent the
 720          * Rx FIFO overflow we have to disable the local interrupts so to block
 721          * any preemption during the subsequent IO operations.
 722          *
 723          * Note. At some circumstances disabling IRQs may not help to prevent
 724          * the problems described above. The CS de-assertion and Rx FIFO
 725          * overflow may still happen due to the relatively slow system bus or
 726          * CPU not working fast enough, so the write-then-read algo implemented
 727          * here just won't keep up with the SPI bus data transfer. Such
 728          * situation is highly platform specific and is supposed to be fixed by
 729          * manually restricting the SPI bus frequency using the
 730          * dws->max_mem_freq parameter.
 731          */
 732         local_irq_save(flags);
 733         preempt_disable();
 734
 735         ret = dw_spi_write_then_read(dws, mem->spi);
 736
 737         local_irq_restore(flags);
 738         preempt_enable();
 739
 740         /*
 741          * Wait for the operation being finished and check the controller
 742          * status only if there hasn't been any run-time error detected. In the
 743          * former case it's just pointless. In the later one to prevent an
 744          * additional error message printing since any hw error flag being set
 745          * would be due to an error detected on the data transfer.
 746          */
 747         if (!ret) {
 748                 ret = dw_spi_wait_mem_op_done(dws);
 749                 if (!ret)
 750                         ret = dw_spi_check_status(dws, true);
 751         }
 752
 753         dw_spi_stop_mem_op(dws, mem->spi);
 754
 755         dw_spi_free_mem_buf(dws);
 756
 757         return ret;
 758 }
 759
 760 /*
 761  * Initialize the default memory operations if a glue layer hasn't specified
 762  * custom ones. Direct mapping operations will be preserved anyway since DW SPI
 763  * controller doesn't have an embedded dirmap interface. Note the memory
 764  * operations implemented in this driver is the best choice only for the DW APB
 765  * SSI controller with standard native CS functionality. If a hardware vendor
 766  * has fixed the automatic CS assertion/de-assertion peculiarity, then it will
 767  * be safer to use the normal SPI-messages-based transfers implementation.
 768  */
 769 static void dw_spi_init_mem_ops(struct dw_spi *dws)
 770 {
 771         if (!dws->mem_ops.exec_op && !(dws->caps & DW_SPI_CAP_CS_OVERRIDE) &&
 772             !dws->set_cs) {
 773                 dws->mem_ops.adjust_op_size = dw_spi_adjust_mem_op_size;
 774                 dws->mem_ops.supports_op = dw_spi_supports_mem_op;
 775                 dws->mem_ops.exec_op = dw_spi_exec_mem_op;
 776                 if (!dws->max_mem_freq)
 777                         dws->max_mem_freq = dws->max_freq;
 778         }
 779 }
 780
 781 /* This may be called twice for each spi dev */
 782 static int dw_spi_setup(struct spi_device *spi)
 783 {
 784         struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
 785         struct dw_spi_chip_data *chip;
 786
 787         /* Only alloc on first setup */
 788         chip = spi_get_ctldata(spi);
 789         if (!chip) {
 790                 struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
 791                 u32 rx_sample_dly_ns;
 792
 793                 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
 794                 if (!chip)
 795                         return -ENOMEM;
 796                 spi_set_ctldata(spi, chip);
 797                 /* Get specific / default rx-sample-delay */
 798                 if (device_property_read_u32(&spi->dev,
 799                                              "rx-sample-delay-ns",
 800                                              &rx_sample_dly_ns) != 0)
 801                         /* Use default controller value */
 802                         rx_sample_dly_ns = dws->def_rx_sample_dly_ns;
 803                 chip->rx_sample_dly = DIV_ROUND_CLOSEST(rx_sample_dly_ns,
 804                                                         NSEC_PER_SEC /
 805                                                         dws->max_freq);
 806         }
 807
 808         /*
 809          * Update CR0 data each time the setup callback is invoked since
 810          * the device parameters could have been changed, for instance, by
 811          * the MMC SPI driver or something else.
 812          */
 813         chip->cr0 = dw_spi_prepare_cr0(dws, spi);
 814
 815         return 0;
 816 }
 817
 818 static void dw_spi_cleanup(struct spi_device *spi)
 819 {
 820         struct dw_spi_chip_data *chip = spi_get_ctldata(spi);
 821
 822         kfree(chip);
 823         spi_set_ctldata(spi, NULL);
 824 }
 825
 826 /* Restart the controller, disable all interrupts, clean rx fifo */
 827 static void dw_spi_hw_init(struct device *dev, struct dw_spi *dws)
 828 {
 829         dw_spi_reset_chip(dws);
 830
 831         /*
 832          * Retrieve the Synopsys component version if it hasn't been specified
 833          * by the platform. CoreKit version ID is encoded as a 3-chars ASCII
 834          * code enclosed with '*' (typical for the most of Synopsys IP-cores).
 835          */
 836         if (!dws->ver) {
 837                 dws->ver = dw_readl(dws, DW_SPI_VERSION);
 838
 839                 dev_dbg(dev, "Synopsys DWC%sSSI v%c.%c%c\n",
 840                         dw_spi_ip_is(dws, PSSI) ? " APB " : " ",
 841                         DW_SPI_GET_BYTE(dws->ver, 3), DW_SPI_GET_BYTE(dws->ver, 2),
 842                         DW_SPI_GET_BYTE(dws->ver, 1));
 843         }
 844
 845         /*
 846          * Try to detect the FIFO depth if not set by interface driver,
 847          * the depth could be from 2 to 256 from HW spec
 848          */
 849         if (!dws->fifo_len) {
 850                 u32 fifo;
 851
 852                 for (fifo = 1; fifo < 256; fifo++) {
 853                         dw_writel(dws, DW_SPI_TXFTLR, fifo);
 854                         if (fifo != dw_readl(dws, DW_SPI_TXFTLR))
 855                                 break;
 856                 }
 857                 dw_writel(dws, DW_SPI_TXFTLR, 0);
 858
 859                 dws->fifo_len = (fifo == 1) ? 0 : fifo;
 860                 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
 861         }
 862
 863         /*
 864          * Detect CTRLR0.DFS field size and offset by testing the lowest bits
 865          * writability. Note DWC SSI controller also has the extended DFS, but
 866          * with zero offset.
 867          */
 868         if (dw_spi_ip_is(dws, PSSI)) {
 869                 u32 cr0, tmp = dw_readl(dws, DW_SPI_CTRLR0);
 870
 871                 dw_spi_enable_chip(dws, 0);
 872                 dw_writel(dws, DW_SPI_CTRLR0, 0xffffffff);
 873                 cr0 = dw_readl(dws, DW_SPI_CTRLR0);
 874                 dw_writel(dws, DW_SPI_CTRLR0, tmp);
 875                 dw_spi_enable_chip(dws, 1);
 876
 877                 if (!(cr0 & DW_PSSI_CTRLR0_DFS_MASK)) {
 878                         dws->caps |= DW_SPI_CAP_DFS32;
 879                         dws->dfs_offset = __bf_shf(DW_PSSI_CTRLR0_DFS32_MASK);
 880                         dev_dbg(dev, "Detected 32-bits max data frame size\n");
 881                 }
 882         } else {
 883                 dws->caps |= DW_SPI_CAP_DFS32;
 884         }
 885
 886         /* enable HW fixup for explicit CS deselect for Amazon's alpine chip */
 887         if (dws->caps & DW_SPI_CAP_CS_OVERRIDE)
 888                 dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF);
 889 }
 890
 891 int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
 892 {
 893         struct spi_controller *host;
 894         int ret;
 895
 896         if (!dws)
 897                 return -EINVAL;
 898
 899         host = spi_alloc_host(dev, 0);
 900         if (!host)
 901                 return -ENOMEM;
 902
 903         device_set_node(&host->dev, dev_fwnode(dev));
 904
 905         dws->host = host;
 906         dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
 907
 908         spi_controller_set_devdata(host, dws);
 909
 910         /* Basic HW init */
 911         dw_spi_hw_init(dev, dws);
 912
 913         ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
 914                           host);
 915         if (ret < 0 && ret != -ENOTCONN) {
 916                 dev_err(dev, "can not get IRQ\n");
 917                 goto err_free_host;
 918         }
 919
 920         dw_spi_init_mem_ops(dws);
 921
 922         host->use_gpio_descriptors = true;
 923         host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
 924         if (dws->caps & DW_SPI_CAP_DFS32)
 925                 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
 926         else
 927                 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
 928         host->bus_num = dws->bus_num;
 929         host->num_chipselect = dws->num_cs;
 930         host->setup = dw_spi_setup;
 931         host->cleanup = dw_spi_cleanup;
 932         if (dws->set_cs)
 933                 host->set_cs = dws->set_cs;
 934         else
 935                 host->set_cs = dw_spi_set_cs;
 936         host->transfer_one = dw_spi_transfer_one;
 937         host->handle_err = dw_spi_handle_err;
 938         if (dws->mem_ops.exec_op)
 939                 host->mem_ops = &dws->mem_ops;
 940         host->max_speed_hz = dws->max_freq;
 941         host->flags = SPI_CONTROLLER_GPIO_SS;
 942         host->auto_runtime_pm = true;
 943
 944         /* Get default rx sample delay */
 945         device_property_read_u32(dev, "rx-sample-delay-ns",
 946                                  &dws->def_rx_sample_dly_ns);
 947
 948         if (dws->dma_ops && dws->dma_ops->dma_init) {
 949                 ret = dws->dma_ops->dma_init(dev, dws);
 950                 if (ret == -EPROBE_DEFER) {
 951                         goto err_free_irq;
 952                 } else if (ret) {
 953                         dev_warn(dev, "DMA init failed\n");
 954                 } else {
 955                         host->can_dma = dws->dma_ops->can_dma;
 956                         host->flags |= SPI_CONTROLLER_MUST_TX;
 957                 }
 958         }
 959
 960         ret = spi_register_controller(host);
 961         if (ret) {
 962                 dev_err_probe(dev, ret, "problem registering spi host\n");
 963                 goto err_dma_exit;
 964         }
 965
 966         dw_spi_debugfs_init(dws);
 967         return 0;
 968
 969 err_dma_exit:
 970         if (dws->dma_ops && dws->dma_ops->dma_exit)
 971                 dws->dma_ops->dma_exit(dws);
 972         dw_spi_enable_chip(dws, 0);
 973 err_free_irq:
 974         free_irq(dws->irq, host);
 975 err_free_host:
 976         spi_controller_put(host);
 977         return ret;
 978 }
 979 EXPORT_SYMBOL_NS_GPL(dw_spi_add_host, SPI_DW_CORE);
 980
 981 void dw_spi_remove_host(struct dw_spi *dws)
 982 {
 983         dw_spi_debugfs_remove(dws);
 984
 985         spi_unregister_controller(dws->host);
 986
 987         if (dws->dma_ops && dws->dma_ops->dma_exit)
 988                 dws->dma_ops->dma_exit(dws);
 989
 990         dw_spi_shutdown_chip(dws);
 991
 992         free_irq(dws->irq, dws->host);
 993 }
 994 EXPORT_SYMBOL_NS_GPL(dw_spi_remove_host, SPI_DW_CORE);
 995
 996 int dw_spi_suspend_host(struct dw_spi *dws)
 997 {
 998         int ret;
 999
1000         ret = spi_controller_suspend(dws->host);
1001         if (ret)
1002                 return ret;
1003
1004         dw_spi_shutdown_chip(dws);
1005         return 0;
1006 }
1007 EXPORT_SYMBOL_NS_GPL(dw_spi_suspend_host, SPI_DW_CORE);
1008
1009 int dw_spi_resume_host(struct dw_spi *dws)
1010 {
1011         dw_spi_hw_init(&dws->host->dev, dws);
1012         return spi_controller_resume(dws->host);
1013 }
1014 EXPORT_SYMBOL_NS_GPL(dw_spi_resume_host, SPI_DW_CORE);
1015
1016 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
1017 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
1018 MODULE_LICENSE("GPL v2");