drivers/spi/spi-clps711x.c

   1 /*
   2  *  CLPS711X SPI bus driver
   3  *
   4  *  Copyright (C) 2012-2014 Alexander Shiyan <shc_work@mail.ru>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/io.h>
  13 #include <linux/clk.h>
  14 #include <linux/gpio.h>
  15 #include <linux/delay.h>
  16 #include <linux/module.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/spi/spi.h>
  20 #include <linux/platform_data/spi-clps711x.h>
  21
  22 #include <mach/hardware.h>
  23
  24 #define DRIVER_NAME     "spi-clps711x"
  25
  26 struct spi_clps711x_data {
  27         struct completion       done;
  28
  29         struct clk              *spi_clk;
  30         u32                     max_speed_hz;
  31
  32         u8                      *tx_buf;
  33         u8                      *rx_buf;
  34         int                     count;
  35         int                     len;
  36
  37         int                     chipselect[0];
  38 };
  39
  40 static int spi_clps711x_setup(struct spi_device *spi)
  41 {
  42         struct spi_clps711x_data *hw = spi_master_get_devdata(spi->master);
  43
  44         /* We are expect that SPI-device is not selected */
  45         gpio_direction_output(hw->chipselect[spi->chip_select],
  46                               !(spi->mode & SPI_CS_HIGH));
  47
  48         return 0;
  49 }
  50
  51 static void spi_clps711x_setup_mode(struct spi_device *spi)
  52 {
  53         /* Setup edge for transfer */
  54         if (spi->mode & SPI_CPHA)
  55                 clps_writew(clps_readw(SYSCON3) | SYSCON3_ADCCKNSEN, SYSCON3);
  56         else
  57                 clps_writew(clps_readw(SYSCON3) & ~SYSCON3_ADCCKNSEN, SYSCON3);
  58 }
  59
  60 static int spi_clps711x_setup_xfer(struct spi_device *spi,
  61                                    struct spi_transfer *xfer)
  62 {
  63         u32 speed = xfer->speed_hz ? : spi->max_speed_hz;
  64         u8 bpw = xfer->bits_per_word;
  65         struct spi_clps711x_data *hw = spi_master_get_devdata(spi->master);
  66
  67         if (bpw != 8) {
  68                 dev_err(&spi->dev, "Unsupported master bus width %i\n", bpw);
  69                 return -EINVAL;
  70         }
  71
  72         /* Setup SPI frequency divider */
  73         if (!speed || (speed >= hw->max_speed_hz))
  74                 clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) |
  75                             SYSCON1_ADCKSEL(3), SYSCON1);
  76         else if (speed >= (hw->max_speed_hz / 2))
  77                 clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) |
  78                             SYSCON1_ADCKSEL(2), SYSCON1);
  79         else if (speed >= (hw->max_speed_hz / 8))
  80                 clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) |
  81                             SYSCON1_ADCKSEL(1), SYSCON1);
  82         else
  83                 clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) |
  84                             SYSCON1_ADCKSEL(0), SYSCON1);
  85
  86         return 0;
  87 }
  88
  89 static int spi_clps711x_transfer_one_message(struct spi_master *master,
  90                                              struct spi_message *msg)
  91 {
  92         struct spi_clps711x_data *hw = spi_master_get_devdata(master);
  93         struct spi_transfer *xfer;
  94         int status = 0, cs = hw->chipselect[msg->spi->chip_select];
  95         u32 data;
  96
  97         spi_clps711x_setup_mode(msg->spi);
  98
  99         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 100                 if (spi_clps711x_setup_xfer(msg->spi, xfer)) {
 101                         status = -EINVAL;
 102                         goto out_xfr;
 103                 }
 104
 105                 gpio_set_value(cs, !!(msg->spi->mode & SPI_CS_HIGH));
 106
 107                 reinit_completion(&hw->done);
 108
 109                 hw->count = 0;
 110                 hw->len = xfer->len;
 111                 hw->tx_buf = (u8 *)xfer->tx_buf;
 112                 hw->rx_buf = (u8 *)xfer->rx_buf;
 113
 114                 /* Initiate transfer */
 115                 data = hw->tx_buf ? hw->tx_buf[hw->count] : 0;
 116                 clps_writel(data | SYNCIO_FRMLEN(8) | SYNCIO_TXFRMEN, SYNCIO);
 117
 118                 wait_for_completion(&hw->done);
 119
 120                 if (xfer->delay_usecs)
 121                         udelay(xfer->delay_usecs);
 122
 123                 if (xfer->cs_change ||
 124                     list_is_last(&xfer->transfer_list, &msg->transfers))
 125                         gpio_set_value(cs, !(msg->spi->mode & SPI_CS_HIGH));
 126
 127                 msg->actual_length += xfer->len;
 128         }
 129
 130 out_xfr:
 131         msg->status = status;
 132         spi_finalize_current_message(master);
 133
 134         return 0;
 135 }
 136
 137 static irqreturn_t spi_clps711x_isr(int irq, void *dev_id)
 138 {
 139         struct spi_clps711x_data *hw = (struct spi_clps711x_data *)dev_id;
 140         u32 data;
 141
 142         /* Handle RX */
 143         data = clps_readb(SYNCIO);
 144         if (hw->rx_buf)
 145                 hw->rx_buf[hw->count] = (u8)data;
 146
 147         hw->count++;
 148
 149         /* Handle TX */
 150         if (hw->count < hw->len) {
 151                 data = hw->tx_buf ? hw->tx_buf[hw->count] : 0;
 152                 clps_writel(data | SYNCIO_FRMLEN(8) | SYNCIO_TXFRMEN, SYNCIO);
 153         } else
 154                 complete(&hw->done);
 155
 156         return IRQ_HANDLED;
 157 }
 158
 159 static int spi_clps711x_probe(struct platform_device *pdev)
 160 {
 161         int i, ret;
 162         struct spi_master *master;
 163         struct spi_clps711x_data *hw;
 164         struct spi_clps711x_pdata *pdata = dev_get_platdata(&pdev->dev);
 165
 166         if (!pdata) {
 167                 dev_err(&pdev->dev, "No platform data supplied\n");
 168                 return -EINVAL;
 169         }
 170
 171         if (pdata->num_chipselect < 1) {
 172                 dev_err(&pdev->dev, "At least one CS must be defined\n");
 173                 return -EINVAL;
 174         }
 175
 176         master = spi_alloc_master(&pdev->dev,
 177                                   sizeof(struct spi_clps711x_data) +
 178                                   sizeof(int) * pdata->num_chipselect);
 179         if (!master) {
 180                 dev_err(&pdev->dev, "SPI allocating memory error\n");
 181                 return -ENOMEM;
 182         }
 183
 184         master->bus_num = pdev->id;
 185         master->mode_bits = SPI_CPHA | SPI_CS_HIGH;
 186         master->bits_per_word_mask = SPI_BPW_MASK(8);
 187         master->num_chipselect = pdata->num_chipselect;
 188         master->setup = spi_clps711x_setup;
 189         master->transfer_one_message = spi_clps711x_transfer_one_message;
 190
 191         hw = spi_master_get_devdata(master);
 192
 193         for (i = 0; i < master->num_chipselect; i++) {
 194                 hw->chipselect[i] = pdata->chipselect[i];
 195                 if (!gpio_is_valid(hw->chipselect[i])) {
 196                         dev_err(&pdev->dev, "Invalid CS GPIO %i\n", i);
 197                         ret = -EINVAL;
 198                         goto err_out;
 199                 }
 200                 if (devm_gpio_request(&pdev->dev, hw->chipselect[i], NULL)) {
 201                         dev_err(&pdev->dev, "Can't get CS GPIO %i\n", i);
 202                         ret = -EINVAL;
 203                         goto err_out;
 204                 }
 205         }
 206
 207         hw->spi_clk = devm_clk_get(&pdev->dev, "spi");
 208         if (IS_ERR(hw->spi_clk)) {
 209                 dev_err(&pdev->dev, "Can't get clocks\n");
 210                 ret = PTR_ERR(hw->spi_clk);
 211                 goto err_out;
 212         }
 213         hw->max_speed_hz = clk_get_rate(hw->spi_clk);
 214
 215         init_completion(&hw->done);
 216         platform_set_drvdata(pdev, master);
 217
 218         /* Disable extended mode due hardware problems */
 219         clps_writew(clps_readw(SYSCON3) & ~SYSCON3_ADCCON, SYSCON3);
 220
 221         /* Clear possible pending interrupt */
 222         clps_readl(SYNCIO);
 223
 224         ret = devm_request_irq(&pdev->dev, IRQ_SSEOTI, spi_clps711x_isr, 0,
 225                                dev_name(&pdev->dev), hw);
 226         if (ret) {
 227                 dev_err(&pdev->dev, "Can't request IRQ\n");
 228                 goto err_out;
 229         }
 230
 231         ret = devm_spi_register_master(&pdev->dev, master);
 232         if (!ret) {
 233                 dev_info(&pdev->dev,
 234                          "SPI bus driver initialized. Master clock %u Hz\n",
 235                          hw->max_speed_hz);
 236                 return 0;
 237         }
 238
 239         dev_err(&pdev->dev, "Failed to register master\n");
 240
 241 err_out:
 242         spi_master_put(master);
 243
 244         return ret;
 245 }
 246
 247 static struct platform_driver clps711x_spi_driver = {
 248         .driver = {
 249                 .name   = DRIVER_NAME,
 250                 .owner  = THIS_MODULE,
 251         },
 252         .probe  = spi_clps711x_probe,
 253 };
 254 module_platform_driver(clps711x_spi_driver);
 255
 256 MODULE_LICENSE("GPL");
 257 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
 258 MODULE_DESCRIPTION("CLPS711X SPI bus driver");
 259 MODULE_ALIAS("platform:" DRIVER_NAME);