1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Cadence SPI controller driver (host and target mode)
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_address.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/spi/spi.h>
23 /* Name of this driver */
24 #define CDNS_SPI_NAME "cdns-spi"
26 /* Register offset definitions */
27 #define CDNS_SPI_CR 0x00 /* Configuration Register, RW */
28 #define CDNS_SPI_ISR 0x04 /* Interrupt Status Register, RO */
29 #define CDNS_SPI_IER 0x08 /* Interrupt Enable Register, WO */
30 #define CDNS_SPI_IDR 0x0c /* Interrupt Disable Register, WO */
31 #define CDNS_SPI_IMR 0x10 /* Interrupt Enabled Mask Register, RO */
32 #define CDNS_SPI_ER 0x14 /* Enable/Disable Register, RW */
33 #define CDNS_SPI_DR 0x18 /* Delay Register, RW */
34 #define CDNS_SPI_TXD 0x1C /* Data Transmit Register, WO */
35 #define CDNS_SPI_RXD 0x20 /* Data Receive Register, RO */
36 #define CDNS_SPI_SICR 0x24 /* Slave Idle Count Register, RW */
37 #define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */
39 #define SPI_AUTOSUSPEND_TIMEOUT 3000
41 * SPI Configuration Register bit Masks
43 * This register contains various control bits that affect the operation
44 * of the SPI controller
46 #define CDNS_SPI_CR_MANSTRT 0x00010000 /* Manual TX Start */
47 #define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */
48 #define CDNS_SPI_CR_CPOL 0x00000002 /* Clock Polarity Control */
49 #define CDNS_SPI_CR_SSCTRL 0x00003C00 /* Slave Select Mask */
50 #define CDNS_SPI_CR_PERI_SEL 0x00000200 /* Peripheral Select Decode */
51 #define CDNS_SPI_CR_BAUD_DIV 0x00000038 /* Baud Rate Divisor Mask */
52 #define CDNS_SPI_CR_MSTREN 0x00000001 /* Master Enable Mask */
53 #define CDNS_SPI_CR_MANSTRTEN 0x00008000 /* Manual TX Enable Mask */
54 #define CDNS_SPI_CR_SSFORCE 0x00004000 /* Manual SS Enable Mask */
55 #define CDNS_SPI_CR_BAUD_DIV_4 0x00000008 /* Default Baud Div Mask */
56 #define CDNS_SPI_CR_DEFAULT (CDNS_SPI_CR_MSTREN | \
57 CDNS_SPI_CR_SSCTRL | \
58 CDNS_SPI_CR_SSFORCE | \
59 CDNS_SPI_CR_BAUD_DIV_4)
62 * SPI Configuration Register - Baud rate and target select
64 * These are the values used in the calculation of baud rate divisor and
65 * setting the target select.
68 #define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
69 #define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */
70 #define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
71 #define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */
72 #define CDNS_SPI_SS0 0x1 /* Slave Select zero */
73 #define CDNS_SPI_NOSS 0xF /* No Slave select */
76 * SPI Interrupt Registers bit Masks
78 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
81 #define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */
82 #define CDNS_SPI_IXR_MODF 0x00000002 /* SPI Mode Fault */
83 #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
84 #define CDNS_SPI_IXR_DEFAULT (CDNS_SPI_IXR_TXOW | \
86 #define CDNS_SPI_IXR_TXFULL 0x00000008 /* SPI TX Full */
87 #define CDNS_SPI_IXR_ALL 0x0000007F /* SPI all interrupts */
90 * SPI Enable Register bit Masks
92 * This register is used to enable or disable the SPI controller
94 #define CDNS_SPI_ER_ENABLE 0x00000001 /* SPI Enable Bit Mask */
95 #define CDNS_SPI_ER_DISABLE 0x0 /* SPI Disable Bit Mask */
97 /* Default number of chip select lines */
98 #define CDNS_SPI_DEFAULT_NUM_CS 4
101 * struct cdns_spi - This definition defines spi driver instance
102 * @regs: Virtual address of the SPI controller registers
103 * @ref_clk: Pointer to the peripheral clock
104 * @pclk: Pointer to the APB clock
105 * @clk_rate: Reference clock frequency, taken from @ref_clk
106 * @speed_hz: Current SPI bus clock speed in Hz
107 * @txbuf: Pointer to the TX buffer
108 * @rxbuf: Pointer to the RX buffer
109 * @tx_bytes: Number of bytes left to transfer
110 * @rx_bytes: Number of bytes requested
111 * @dev_busy: Device busy flag
112 * @is_decoded_cs: Flag for decoder property set or not
113 * @tx_fifo_depth: Depth of the TX FIFO
119 unsigned int clk_rate;
127 unsigned int tx_fifo_depth;
130 /* Macros for the SPI controller read/write */
131 static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
133 return readl_relaxed(xspi->regs + offset);
136 static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
138 writel_relaxed(val, xspi->regs + offset);
142 * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
143 * @xspi: Pointer to the cdns_spi structure
144 * @is_target: Flag to indicate target or host mode
145 * * On reset the SPI controller is configured to target or host mode.
146 * In host mode baud rate divisor is set to 4, threshold value for TX FIFO
147 * not full interrupt is set to 1 and size of the word to be transferred as 8 bit.
149 * This function initializes the SPI controller to disable and clear all the
150 * interrupts, enable manual target select and manual start, deselect all the
151 * chip select lines, and enable the SPI controller.
153 static void cdns_spi_init_hw(struct cdns_spi *xspi, bool is_target)
158 ctrl_reg |= CDNS_SPI_CR_DEFAULT;
160 if (xspi->is_decoded_cs)
161 ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
163 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
164 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
166 /* Clear the RX FIFO */
167 while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
168 cdns_spi_read(xspi, CDNS_SPI_RXD);
170 cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
171 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
172 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
176 * cdns_spi_chipselect - Select or deselect the chip select line
177 * @spi: Pointer to the spi_device structure
178 * @is_high: Select(0) or deselect (1) the chip select line
180 static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
182 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
185 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
188 /* Deselect the target */
189 ctrl_reg |= CDNS_SPI_CR_SSCTRL;
191 /* Select the target */
192 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
193 if (!(xspi->is_decoded_cs))
194 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) <<
198 ctrl_reg |= (spi_get_chipselect(spi, 0) << CDNS_SPI_SS_SHIFT) &
202 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
206 * cdns_spi_config_clock_mode - Sets clock polarity and phase
207 * @spi: Pointer to the spi_device structure
209 * Sets the requested clock polarity and phase.
211 static void cdns_spi_config_clock_mode(struct spi_device *spi)
213 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
214 u32 ctrl_reg, new_ctrl_reg;
216 new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
217 ctrl_reg = new_ctrl_reg;
219 /* Set the SPI clock phase and clock polarity */
220 new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
221 if (spi->mode & SPI_CPHA)
222 new_ctrl_reg |= CDNS_SPI_CR_CPHA;
223 if (spi->mode & SPI_CPOL)
224 new_ctrl_reg |= CDNS_SPI_CR_CPOL;
226 if (new_ctrl_reg != ctrl_reg) {
228 * Just writing the CR register does not seem to apply the clock
229 * setting changes. This is problematic when changing the clock
230 * polarity as it will cause the SPI target to see spurious clock
231 * transitions. To workaround the issue toggle the ER register.
233 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
234 cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
235 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
240 * cdns_spi_config_clock_freq - Sets clock frequency
241 * @spi: Pointer to the spi_device structure
242 * @transfer: Pointer to the spi_transfer structure which provides
243 * information about next transfer setup parameters
245 * Sets the requested clock frequency.
246 * Note: If the requested frequency is not an exact match with what can be
247 * obtained using the prescalar value the driver sets the clock frequency which
248 * is lower than the requested frequency (maximum lower) for the transfer. If
249 * the requested frequency is higher or lower than that is supported by the SPI
250 * controller the driver will set the highest or lowest frequency supported by
253 static void cdns_spi_config_clock_freq(struct spi_device *spi,
254 struct spi_transfer *transfer)
256 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
257 u32 ctrl_reg, baud_rate_val;
258 unsigned long frequency;
260 frequency = xspi->clk_rate;
262 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
264 /* Set the clock frequency */
265 if (xspi->speed_hz != transfer->speed_hz) {
266 /* first valid value is 1 */
267 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
268 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
269 (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
272 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
273 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
275 xspi->speed_hz = frequency / (2 << baud_rate_val);
277 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
281 * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
282 * @spi: Pointer to the spi_device structure
283 * @transfer: Pointer to the spi_transfer structure which provides
284 * information about next transfer setup parameters
286 * Sets the operational mode of SPI controller for the next SPI transfer and
287 * sets the requested clock frequency.
291 static int cdns_spi_setup_transfer(struct spi_device *spi,
292 struct spi_transfer *transfer)
294 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
296 cdns_spi_config_clock_freq(spi, transfer);
298 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
299 __func__, spi->mode, spi->bits_per_word,
306 * cdns_spi_process_fifo - Fills the TX FIFO, and drain the RX FIFO
307 * @xspi: Pointer to the cdns_spi structure
308 * @ntx: Number of bytes to pack into the TX FIFO
309 * @nrx: Number of bytes to drain from the RX FIFO
311 static void cdns_spi_process_fifo(struct cdns_spi *xspi, int ntx, int nrx)
313 ntx = clamp(ntx, 0, xspi->tx_bytes);
314 nrx = clamp(nrx, 0, xspi->rx_bytes);
316 xspi->tx_bytes -= ntx;
317 xspi->rx_bytes -= nrx;
322 cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
324 cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
330 u8 data = cdns_spi_read(xspi, CDNS_SPI_RXD);
333 *xspi->rxbuf++ = data;
341 * cdns_spi_irq - Interrupt service routine of the SPI controller
343 * @dev_id: Pointer to the xspi structure
345 * This function handles TX empty and Mode Fault interrupts only.
346 * On TX empty interrupt this function reads the received data from RX FIFO and
347 * fills the TX FIFO if there is any data remaining to be transferred.
348 * On Mode Fault interrupt this function indicates that transfer is completed,
349 * the SPI subsystem will identify the error as the remaining bytes to be
350 * transferred is non-zero.
352 * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise.
354 static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
356 struct spi_controller *ctlr = dev_id;
357 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
362 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
363 cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
365 if (intr_status & CDNS_SPI_IXR_MODF) {
366 /* Indicate that transfer is completed, the SPI subsystem will
367 * identify the error as the remaining bytes to be
368 * transferred is non-zero
370 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
371 spi_finalize_current_transfer(ctlr);
372 status = IRQ_HANDLED;
373 } else if (intr_status & CDNS_SPI_IXR_TXOW) {
374 int threshold = cdns_spi_read(xspi, CDNS_SPI_THLD);
375 int trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
378 trans_cnt -= threshold;
380 /* Set threshold to one if number of pending are
381 * less than half fifo
383 if (xspi->tx_bytes < xspi->tx_fifo_depth >> 1)
384 cdns_spi_write(xspi, CDNS_SPI_THLD, 1);
386 if (xspi->tx_bytes) {
387 cdns_spi_process_fifo(xspi, trans_cnt, trans_cnt);
389 /* Fixed delay due to controller limitation with
390 * RX_NEMPTY incorrect status
391 * Xilinx AR:65885 contains more details
394 cdns_spi_process_fifo(xspi, 0, trans_cnt);
395 cdns_spi_write(xspi, CDNS_SPI_IDR,
396 CDNS_SPI_IXR_DEFAULT);
397 spi_finalize_current_transfer(ctlr);
399 status = IRQ_HANDLED;
405 static int cdns_prepare_message(struct spi_controller *ctlr,
406 struct spi_message *msg)
408 if (!spi_controller_is_target(ctlr))
409 cdns_spi_config_clock_mode(msg->spi);
414 * cdns_transfer_one - Initiates the SPI transfer
415 * @ctlr: Pointer to spi_controller structure
416 * @spi: Pointer to the spi_device structure
417 * @transfer: Pointer to the spi_transfer structure which provides
418 * information about next transfer parameters
420 * This function in host mode fills the TX FIFO, starts the SPI transfer and
421 * returns a positive transfer count so that core will wait for completion.
422 * This function in target mode fills the TX FIFO and wait for transfer trigger.
424 * Return: Number of bytes transferred in the last transfer
426 static int cdns_transfer_one(struct spi_controller *ctlr,
427 struct spi_device *spi,
428 struct spi_transfer *transfer)
430 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
432 xspi->txbuf = transfer->tx_buf;
433 xspi->rxbuf = transfer->rx_buf;
434 xspi->tx_bytes = transfer->len;
435 xspi->rx_bytes = transfer->len;
437 if (!spi_controller_is_target(ctlr)) {
438 cdns_spi_setup_transfer(spi, transfer);
440 /* Set TX empty threshold to half of FIFO depth
441 * only if TX bytes are more than FIFO depth.
443 if (xspi->tx_bytes > xspi->tx_fifo_depth)
444 cdns_spi_write(xspi, CDNS_SPI_THLD, xspi->tx_fifo_depth >> 1);
447 /* When xspi in busy condition, bytes may send failed,
448 * then spi control didn't work thoroughly, add one byte delay
450 if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL)
453 cdns_spi_process_fifo(xspi, xspi->tx_fifo_depth, 0);
454 spi_transfer_delay_exec(transfer);
456 cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
457 return transfer->len;
461 * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
462 * @ctlr: Pointer to the spi_controller structure which provides
463 * information about the controller.
465 * This function enables SPI host controller.
469 static int cdns_prepare_transfer_hardware(struct spi_controller *ctlr)
471 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
473 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
479 * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
480 * @ctlr: Pointer to the spi_controller structure which provides
481 * information about the controller.
483 * This function disables the SPI host controller when no target selected.
484 * This function flush out if any pending data in FIFO.
488 static int cdns_unprepare_transfer_hardware(struct spi_controller *ctlr)
490 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
492 unsigned int cnt = xspi->tx_fifo_depth;
494 if (spi_controller_is_target(ctlr)) {
496 cdns_spi_read(xspi, CDNS_SPI_RXD);
499 /* Disable the SPI if target is deselected */
500 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
501 ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >> CDNS_SPI_SS_SHIFT;
502 if (ctrl_reg == CDNS_SPI_NOSS || spi_controller_is_target(ctlr))
503 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
505 /* Reset to default */
506 cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
511 * cdns_spi_detect_fifo_depth - Detect the FIFO depth of the hardware
512 * @xspi: Pointer to the cdns_spi structure
514 * The depth of the TX FIFO is a synthesis configuration parameter of the SPI
515 * IP. The FIFO threshold register is sized so that its maximum value can be the
516 * FIFO size - 1. This is used to detect the size of the FIFO.
518 static void cdns_spi_detect_fifo_depth(struct cdns_spi *xspi)
520 /* The MSBs will get truncated giving us the size of the FIFO */
521 cdns_spi_write(xspi, CDNS_SPI_THLD, 0xffff);
522 xspi->tx_fifo_depth = cdns_spi_read(xspi, CDNS_SPI_THLD) + 1;
524 /* Reset to default */
525 cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
529 * cdns_target_abort - Abort target transfer
530 * @ctlr: Pointer to the spi_controller structure
532 * This function abort target transfer if there any transfer timeout.
536 static int cdns_target_abort(struct spi_controller *ctlr)
538 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
541 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
542 cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
543 cdns_spi_write(xspi, CDNS_SPI_IDR, (CDNS_SPI_IXR_MODF | CDNS_SPI_IXR_RXNEMTY));
544 spi_finalize_current_transfer(ctlr);
550 * cdns_spi_probe - Probe method for the SPI driver
551 * @pdev: Pointer to the platform_device structure
553 * This function initializes the driver data structures and the hardware.
555 * Return: 0 on success and error value on error
557 static int cdns_spi_probe(struct platform_device *pdev)
560 struct spi_controller *ctlr;
561 struct cdns_spi *xspi;
565 target = of_property_read_bool(pdev->dev.of_node, "spi-slave");
567 ctlr = spi_alloc_target(&pdev->dev, sizeof(*xspi));
569 ctlr = spi_alloc_host(&pdev->dev, sizeof(*xspi));
574 xspi = spi_controller_get_devdata(ctlr);
575 ctlr->dev.of_node = pdev->dev.of_node;
576 platform_set_drvdata(pdev, ctlr);
578 xspi->regs = devm_platform_ioremap_resource(pdev, 0);
579 if (IS_ERR(xspi->regs)) {
580 ret = PTR_ERR(xspi->regs);
584 xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
585 if (IS_ERR(xspi->pclk)) {
586 dev_err(&pdev->dev, "pclk clock not found.\n");
587 ret = PTR_ERR(xspi->pclk);
591 ret = clk_prepare_enable(xspi->pclk);
593 dev_err(&pdev->dev, "Unable to enable APB clock.\n");
597 if (!spi_controller_is_target(ctlr)) {
598 xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
599 if (IS_ERR(xspi->ref_clk)) {
600 dev_err(&pdev->dev, "ref_clk clock not found.\n");
601 ret = PTR_ERR(xspi->ref_clk);
605 ret = clk_prepare_enable(xspi->ref_clk);
607 dev_err(&pdev->dev, "Unable to enable device clock.\n");
611 pm_runtime_use_autosuspend(&pdev->dev);
612 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
613 pm_runtime_get_noresume(&pdev->dev);
614 pm_runtime_set_active(&pdev->dev);
615 pm_runtime_enable(&pdev->dev);
617 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
619 ctlr->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
621 ctlr->num_chipselect = num_cs;
623 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
624 &xspi->is_decoded_cs);
626 xspi->is_decoded_cs = 0;
629 cdns_spi_detect_fifo_depth(xspi);
631 /* SPI controller initializations */
632 cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr));
634 irq = platform_get_irq(pdev, 0);
640 ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
641 0, pdev->name, ctlr);
644 dev_err(&pdev->dev, "request_irq failed\n");
648 ctlr->use_gpio_descriptors = true;
649 ctlr->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
650 ctlr->prepare_message = cdns_prepare_message;
651 ctlr->transfer_one = cdns_transfer_one;
652 ctlr->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
653 ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
654 ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
656 if (!spi_controller_is_target(ctlr)) {
657 ctlr->mode_bits |= SPI_CS_HIGH;
658 ctlr->set_cs = cdns_spi_chipselect;
659 ctlr->auto_runtime_pm = true;
660 xspi->clk_rate = clk_get_rate(xspi->ref_clk);
661 /* Set to default valid value */
662 ctlr->max_speed_hz = xspi->clk_rate / 4;
663 xspi->speed_hz = ctlr->max_speed_hz;
664 pm_runtime_mark_last_busy(&pdev->dev);
665 pm_runtime_put_autosuspend(&pdev->dev);
667 ctlr->mode_bits |= SPI_NO_CS;
668 ctlr->target_abort = cdns_target_abort;
670 ret = spi_register_controller(ctlr);
672 dev_err(&pdev->dev, "spi_register_controller failed\n");
679 if (!spi_controller_is_target(ctlr)) {
680 pm_runtime_set_suspended(&pdev->dev);
681 pm_runtime_disable(&pdev->dev);
682 clk_disable_unprepare(xspi->ref_clk);
685 clk_disable_unprepare(xspi->pclk);
687 spi_controller_put(ctlr);
692 * cdns_spi_remove - Remove method for the SPI driver
693 * @pdev: Pointer to the platform_device structure
695 * This function is called if a device is physically removed from the system or
696 * if the driver module is being unloaded. It frees all resources allocated to
699 static void cdns_spi_remove(struct platform_device *pdev)
701 struct spi_controller *ctlr = platform_get_drvdata(pdev);
702 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
704 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
706 clk_disable_unprepare(xspi->ref_clk);
707 clk_disable_unprepare(xspi->pclk);
708 pm_runtime_set_suspended(&pdev->dev);
709 pm_runtime_disable(&pdev->dev);
711 spi_unregister_controller(ctlr);
715 * cdns_spi_suspend - Suspend method for the SPI driver
716 * @dev: Address of the platform_device structure
718 * This function disables the SPI controller and
719 * changes the driver state to "suspend"
721 * Return: 0 on success and error value on error
723 static int __maybe_unused cdns_spi_suspend(struct device *dev)
725 struct spi_controller *ctlr = dev_get_drvdata(dev);
727 return spi_controller_suspend(ctlr);
731 * cdns_spi_resume - Resume method for the SPI driver
732 * @dev: Address of the platform_device structure
734 * This function changes the driver state to "ready"
736 * Return: 0 on success and error value on error
738 static int __maybe_unused cdns_spi_resume(struct device *dev)
740 struct spi_controller *ctlr = dev_get_drvdata(dev);
741 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
743 cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr));
744 return spi_controller_resume(ctlr);
748 * cdns_spi_runtime_resume - Runtime resume method for the SPI driver
749 * @dev: Address of the platform_device structure
751 * This function enables the clocks
753 * Return: 0 on success and error value on error
755 static int __maybe_unused cdns_spi_runtime_resume(struct device *dev)
757 struct spi_controller *ctlr = dev_get_drvdata(dev);
758 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
761 ret = clk_prepare_enable(xspi->pclk);
763 dev_err(dev, "Cannot enable APB clock.\n");
767 ret = clk_prepare_enable(xspi->ref_clk);
769 dev_err(dev, "Cannot enable device clock.\n");
770 clk_disable_unprepare(xspi->pclk);
777 * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
778 * @dev: Address of the platform_device structure
780 * This function disables the clocks
784 static int __maybe_unused cdns_spi_runtime_suspend(struct device *dev)
786 struct spi_controller *ctlr = dev_get_drvdata(dev);
787 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
789 clk_disable_unprepare(xspi->ref_clk);
790 clk_disable_unprepare(xspi->pclk);
795 static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
796 SET_RUNTIME_PM_OPS(cdns_spi_runtime_suspend,
797 cdns_spi_runtime_resume, NULL)
798 SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
801 static const struct of_device_id cdns_spi_of_match[] = {
802 { .compatible = "xlnx,zynq-spi-r1p6" },
803 { .compatible = "cdns,spi-r1p6" },
804 { /* end of table */ }
806 MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
808 /* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
809 static struct platform_driver cdns_spi_driver = {
810 .probe = cdns_spi_probe,
811 .remove_new = cdns_spi_remove,
813 .name = CDNS_SPI_NAME,
814 .of_match_table = cdns_spi_of_match,
815 .pm = &cdns_spi_dev_pm_ops,
819 module_platform_driver(cdns_spi_driver);
821 MODULE_AUTHOR("Xilinx, Inc.");
822 MODULE_DESCRIPTION("Cadence SPI driver");
823 MODULE_LICENSE("GPL");