drivers/spi/spi-cadence-quadspi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 //
   3 // Driver for Cadence QSPI Controller
   4 //
   5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
   6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
   7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
   8
   9 #include <linux/clk.h>
  10 #include <linux/completion.h>
  11 #include <linux/delay.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/dmaengine.h>
  14 #include <linux/err.h>
  15 #include <linux/errno.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/iopoll.h>
  19 #include <linux/jiffies.h>
  20 #include <linux/kernel.h>
  21 #include <linux/log2.h>
  22 #include <linux/module.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/reset.h>
  28 #include <linux/sched.h>
  29 #include <linux/spi/spi.h>
  30 #include <linux/spi/spi-mem.h>
  31 #include <linux/timer.h>
  32
  33 #define CQSPI_NAME                      "cadence-qspi"
  34 #define CQSPI_MAX_CHIPSELECT            16
  35
  36 /* Quirks */
  37 #define CQSPI_NEEDS_WR_DELAY            BIT(0)
  38 #define CQSPI_DISABLE_DAC_MODE          BIT(1)
  39 #define CQSPI_NO_SUPPORT_WR_COMPLETION  BIT(3)
  40
  41 /* Capabilities */
  42 #define CQSPI_SUPPORTS_OCTAL            BIT(0)
  43
  44 struct cqspi_st;
  45
  46 struct cqspi_flash_pdata {
  47         struct cqspi_st *cqspi;
  48         u32             clk_rate;
  49         u32             read_delay;
  50         u32             tshsl_ns;
  51         u32             tsd2d_ns;
  52         u32             tchsh_ns;
  53         u32             tslch_ns;
  54         u8              inst_width;
  55         u8              addr_width;
  56         u8              data_width;
  57         bool            dtr;
  58         u8              cs;
  59 };
  60
  61 struct cqspi_st {
  62         struct platform_device  *pdev;
  63
  64         struct clk              *clk;
  65         unsigned int            sclk;
  66
  67         void __iomem            *iobase;
  68         void __iomem            *ahb_base;
  69         resource_size_t         ahb_size;
  70         struct completion       transfer_complete;
  71
  72         struct dma_chan         *rx_chan;
  73         struct completion       rx_dma_complete;
  74         dma_addr_t              mmap_phys_base;
  75
  76         int                     current_cs;
  77         unsigned long           master_ref_clk_hz;
  78         bool                    is_decoded_cs;
  79         u32                     fifo_depth;
  80         u32                     fifo_width;
  81         u32                     num_chipselect;
  82         bool                    rclk_en;
  83         u32                     trigger_address;
  84         u32                     wr_delay;
  85         bool                    use_direct_mode;
  86         struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
  87         bool                    wr_completion;
  88 };
  89
  90 struct cqspi_driver_platdata {
  91         u32 hwcaps_mask;
  92         u8 quirks;
  93 };
  94
  95 /* Operation timeout value */
  96 #define CQSPI_TIMEOUT_MS                        500
  97 #define CQSPI_READ_TIMEOUT_MS                   10
  98
  99 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
 100 #define CQSPI_DUMMY_BYTES_MAX                   4
 101 #define CQSPI_DUMMY_CLKS_MAX                    31
 102
 103 #define CQSPI_STIG_DATA_LEN_MAX                 8
 104
 105 /* Register map */
 106 #define CQSPI_REG_CONFIG                        0x00
 107 #define CQSPI_REG_CONFIG_ENABLE_MASK            BIT(0)
 108 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL       BIT(7)
 109 #define CQSPI_REG_CONFIG_DECODE_MASK            BIT(9)
 110 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
 111 #define CQSPI_REG_CONFIG_DMA_MASK               BIT(15)
 112 #define CQSPI_REG_CONFIG_BAUD_LSB               19
 113 #define CQSPI_REG_CONFIG_DTR_PROTO              BIT(24)
 114 #define CQSPI_REG_CONFIG_DUAL_OPCODE            BIT(30)
 115 #define CQSPI_REG_CONFIG_IDLE_LSB               31
 116 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
 117 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
 118
 119 #define CQSPI_REG_RD_INSTR                      0x04
 120 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
 121 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
 122 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
 123 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
 124 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
 125 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
 126 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
 127 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
 128 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
 129 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
 130
 131 #define CQSPI_REG_WR_INSTR                      0x08
 132 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
 133 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB        12
 134 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
 135
 136 #define CQSPI_REG_DELAY                         0x0C
 137 #define CQSPI_REG_DELAY_TSLCH_LSB               0
 138 #define CQSPI_REG_DELAY_TCHSH_LSB               8
 139 #define CQSPI_REG_DELAY_TSD2D_LSB               16
 140 #define CQSPI_REG_DELAY_TSHSL_LSB               24
 141 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
 142 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
 143 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
 144 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
 145
 146 #define CQSPI_REG_READCAPTURE                   0x10
 147 #define CQSPI_REG_READCAPTURE_BYPASS_LSB        0
 148 #define CQSPI_REG_READCAPTURE_DELAY_LSB         1
 149 #define CQSPI_REG_READCAPTURE_DELAY_MASK        0xF
 150
 151 #define CQSPI_REG_SIZE                          0x14
 152 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 153 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 154 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 155 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 156 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 157 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 158
 159 #define CQSPI_REG_SRAMPARTITION                 0x18
 160 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 161
 162 #define CQSPI_REG_DMA                           0x20
 163 #define CQSPI_REG_DMA_SINGLE_LSB                0
 164 #define CQSPI_REG_DMA_BURST_LSB                 8
 165 #define CQSPI_REG_DMA_SINGLE_MASK               0xFF
 166 #define CQSPI_REG_DMA_BURST_MASK                0xFF
 167
 168 #define CQSPI_REG_REMAP                         0x24
 169 #define CQSPI_REG_MODE_BIT                      0x28
 170
 171 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 172 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 173 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 174 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 175 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 176
 177 #define CQSPI_REG_WR_COMPLETION_CTRL            0x38
 178 #define CQSPI_REG_WR_DISABLE_AUTO_POLL          BIT(14)
 179
 180 #define CQSPI_REG_IRQSTATUS                     0x40
 181 #define CQSPI_REG_IRQMASK                       0x44
 182
 183 #define CQSPI_REG_INDIRECTRD                    0x60
 184 #define CQSPI_REG_INDIRECTRD_START_MASK         BIT(0)
 185 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        BIT(1)
 186 #define CQSPI_REG_INDIRECTRD_DONE_MASK          BIT(5)
 187
 188 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 189 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 190 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 191
 192 #define CQSPI_REG_CMDCTRL                       0x90
 193 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          BIT(0)
 194 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       BIT(1)
 195 #define CQSPI_REG_CMDCTRL_DUMMY_LSB             7
 196 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 197 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 198 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 199 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 200 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 201 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 202 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 203 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 204 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 205 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 206 #define CQSPI_REG_CMDCTRL_DUMMY_MASK            0x1F
 207
 208 #define CQSPI_REG_INDIRECTWR                    0x70
 209 #define CQSPI_REG_INDIRECTWR_START_MASK         BIT(0)
 210 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        BIT(1)
 211 #define CQSPI_REG_INDIRECTWR_DONE_MASK          BIT(5)
 212
 213 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 214 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 215 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 216
 217 #define CQSPI_REG_CMDADDRESS                    0x94
 218 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 219 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 220 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 221 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 222
 223 #define CQSPI_REG_POLLING_STATUS                0xB0
 224 #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB      16
 225
 226 #define CQSPI_REG_OP_EXT_LOWER                  0xE0
 227 #define CQSPI_REG_OP_EXT_READ_LSB               24
 228 #define CQSPI_REG_OP_EXT_WRITE_LSB              16
 229 #define CQSPI_REG_OP_EXT_STIG_LSB               0
 230
 231 /* Interrupt status bits */
 232 #define CQSPI_REG_IRQ_MODE_ERR                  BIT(0)
 233 #define CQSPI_REG_IRQ_UNDERFLOW                 BIT(1)
 234 #define CQSPI_REG_IRQ_IND_COMP                  BIT(2)
 235 #define CQSPI_REG_IRQ_IND_RD_REJECT             BIT(3)
 236 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR          BIT(4)
 237 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR           BIT(5)
 238 #define CQSPI_REG_IRQ_WATERMARK                 BIT(6)
 239 #define CQSPI_REG_IRQ_IND_SRAM_FULL             BIT(12)
 240
 241 #define CQSPI_IRQ_MASK_RD               (CQSPI_REG_IRQ_WATERMARK        | \
 242                                          CQSPI_REG_IRQ_IND_SRAM_FULL    | \
 243                                          CQSPI_REG_IRQ_IND_COMP)
 244
 245 #define CQSPI_IRQ_MASK_WR               (CQSPI_REG_IRQ_IND_COMP         | \
 246                                          CQSPI_REG_IRQ_WATERMARK        | \
 247                                          CQSPI_REG_IRQ_UNDERFLOW)
 248
 249 #define CQSPI_IRQ_STATUS_MASK           0x1FFFF
 250
 251 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
 252 {
 253         u32 val;
 254
 255         return readl_relaxed_poll_timeout(reg, val,
 256                                           (((clr ? ~val : val) & mask) == mask),
 257                                           10, CQSPI_TIMEOUT_MS * 1000);
 258 }
 259
 260 static bool cqspi_is_idle(struct cqspi_st *cqspi)
 261 {
 262         u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 263
 264         return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB);
 265 }
 266
 267 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
 268 {
 269         u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
 270
 271         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 272         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 273 }
 274
 275 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
 276 {
 277         struct cqspi_st *cqspi = dev;
 278         unsigned int irq_status;
 279
 280         /* Read interrupt status */
 281         irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
 282
 283         /* Clear interrupt */
 284         writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
 285
 286         irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
 287
 288         if (irq_status)
 289                 complete(&cqspi->transfer_complete);
 290
 291         return IRQ_HANDLED;
 292 }
 293
 294 static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata)
 295 {
 296         u32 rdreg = 0;
 297
 298         rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
 299         rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
 300         rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 301
 302         return rdreg;
 303 }
 304
 305 static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr)
 306 {
 307         unsigned int dummy_clk;
 308
 309         if (!op->dummy.nbytes)
 310                 return 0;
 311
 312         dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
 313         if (dtr)
 314                 dummy_clk /= 2;
 315
 316         return dummy_clk;
 317 }
 318
 319 static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata,
 320                               const struct spi_mem_op *op)
 321 {
 322         /*
 323          * For an op to be DTR, cmd phase along with every other non-empty
 324          * phase should have dtr field set to 1. If an op phase has zero
 325          * nbytes, ignore its dtr field; otherwise, check its dtr field.
 326          */
 327         f_pdata->dtr = op->cmd.dtr &&
 328                        (!op->addr.nbytes || op->addr.dtr) &&
 329                        (!op->data.nbytes || op->data.dtr);
 330
 331         f_pdata->inst_width = 0;
 332         if (op->cmd.buswidth)
 333                 f_pdata->inst_width = ilog2(op->cmd.buswidth);
 334
 335         f_pdata->addr_width = 0;
 336         if (op->addr.buswidth)
 337                 f_pdata->addr_width = ilog2(op->addr.buswidth);
 338
 339         f_pdata->data_width = 0;
 340         if (op->data.buswidth)
 341                 f_pdata->data_width = ilog2(op->data.buswidth);
 342
 343         /* Right now we only support 8-8-8 DTR mode. */
 344         if (f_pdata->dtr) {
 345                 switch (op->cmd.buswidth) {
 346                 case 0:
 347                 case 8:
 348                         break;
 349                 default:
 350                         return -EINVAL;
 351                 }
 352
 353                 switch (op->addr.buswidth) {
 354                 case 0:
 355                 case 8:
 356                         break;
 357                 default:
 358                         return -EINVAL;
 359                 }
 360
 361                 switch (op->data.buswidth) {
 362                 case 0:
 363                 case 8:
 364                         break;
 365                 default:
 366                         return -EINVAL;
 367                 }
 368         }
 369
 370         return 0;
 371 }
 372
 373 static int cqspi_wait_idle(struct cqspi_st *cqspi)
 374 {
 375         const unsigned int poll_idle_retry = 3;
 376         unsigned int count = 0;
 377         unsigned long timeout;
 378
 379         timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 380         while (1) {
 381                 /*
 382                  * Read few times in succession to ensure the controller
 383                  * is indeed idle, that is, the bit does not transition
 384                  * low again.
 385                  */
 386                 if (cqspi_is_idle(cqspi))
 387                         count++;
 388                 else
 389                         count = 0;
 390
 391                 if (count >= poll_idle_retry)
 392                         return 0;
 393
 394                 if (time_after(jiffies, timeout)) {
 395                         /* Timeout, in busy mode. */
 396                         dev_err(&cqspi->pdev->dev,
 397                                 "QSPI is still busy after %dms timeout.\n",
 398                                 CQSPI_TIMEOUT_MS);
 399                         return -ETIMEDOUT;
 400                 }
 401
 402                 cpu_relax();
 403         }
 404 }
 405
 406 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
 407 {
 408         void __iomem *reg_base = cqspi->iobase;
 409         int ret;
 410
 411         /* Write the CMDCTRL without start execution. */
 412         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 413         /* Start execute */
 414         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 415         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 416
 417         /* Polling for completion. */
 418         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
 419                                  CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
 420         if (ret) {
 421                 dev_err(&cqspi->pdev->dev,
 422                         "Flash command execution timed out.\n");
 423                 return ret;
 424         }
 425
 426         /* Polling QSPI idle status. */
 427         return cqspi_wait_idle(cqspi);
 428 }
 429
 430 static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata,
 431                                   const struct spi_mem_op *op,
 432                                   unsigned int shift)
 433 {
 434         struct cqspi_st *cqspi = f_pdata->cqspi;
 435         void __iomem *reg_base = cqspi->iobase;
 436         unsigned int reg;
 437         u8 ext;
 438
 439         if (op->cmd.nbytes != 2)
 440                 return -EINVAL;
 441
 442         /* Opcode extension is the LSB. */
 443         ext = op->cmd.opcode & 0xff;
 444
 445         reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER);
 446         reg &= ~(0xff << shift);
 447         reg |= ext << shift;
 448         writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER);
 449
 450         return 0;
 451 }
 452
 453 static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata,
 454                             const struct spi_mem_op *op, unsigned int shift,
 455                             bool enable)
 456 {
 457         struct cqspi_st *cqspi = f_pdata->cqspi;
 458         void __iomem *reg_base = cqspi->iobase;
 459         unsigned int reg;
 460         int ret;
 461
 462         reg = readl(reg_base + CQSPI_REG_CONFIG);
 463
 464         /*
 465          * We enable dual byte opcode here. The callers have to set up the
 466          * extension opcode based on which type of operation it is.
 467          */
 468         if (enable) {
 469                 reg |= CQSPI_REG_CONFIG_DTR_PROTO;
 470                 reg |= CQSPI_REG_CONFIG_DUAL_OPCODE;
 471
 472                 /* Set up command opcode extension. */
 473                 ret = cqspi_setup_opcode_ext(f_pdata, op, shift);
 474                 if (ret)
 475                         return ret;
 476         } else {
 477                 reg &= ~CQSPI_REG_CONFIG_DTR_PROTO;
 478                 reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE;
 479         }
 480
 481         writel(reg, reg_base + CQSPI_REG_CONFIG);
 482
 483         return cqspi_wait_idle(cqspi);
 484 }
 485
 486 static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
 487                               const struct spi_mem_op *op)
 488 {
 489         struct cqspi_st *cqspi = f_pdata->cqspi;
 490         void __iomem *reg_base = cqspi->iobase;
 491         u8 *rxbuf = op->data.buf.in;
 492         u8 opcode;
 493         size_t n_rx = op->data.nbytes;
 494         unsigned int rdreg;
 495         unsigned int reg;
 496         unsigned int dummy_clk;
 497         size_t read_len;
 498         int status;
 499
 500         status = cqspi_set_protocol(f_pdata, op);
 501         if (status)
 502                 return status;
 503
 504         status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB,
 505                                   f_pdata->dtr);
 506         if (status)
 507                 return status;
 508
 509         if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 510                 dev_err(&cqspi->pdev->dev,
 511                         "Invalid input argument, len %zu rxbuf 0x%p\n",
 512                         n_rx, rxbuf);
 513                 return -EINVAL;
 514         }
 515
 516         if (f_pdata->dtr)
 517                 opcode = op->cmd.opcode >> 8;
 518         else
 519                 opcode = op->cmd.opcode;
 520
 521         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 522
 523         rdreg = cqspi_calc_rdreg(f_pdata);
 524         writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
 525
 526         dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr);
 527         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 528                 return -EOPNOTSUPP;
 529
 530         if (dummy_clk)
 531                 reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)
 532                      << CQSPI_REG_CMDCTRL_DUMMY_LSB;
 533
 534         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 535
 536         /* 0 means 1 byte. */
 537         reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 538                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 539         status = cqspi_exec_flash_cmd(cqspi, reg);
 540         if (status)
 541                 return status;
 542
 543         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 544
 545         /* Put the read value into rx_buf */
 546         read_len = (n_rx > 4) ? 4 : n_rx;
 547         memcpy(rxbuf, &reg, read_len);
 548         rxbuf += read_len;
 549
 550         if (n_rx > 4) {
 551                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 552
 553                 read_len = n_rx - read_len;
 554                 memcpy(rxbuf, &reg, read_len);
 555         }
 556
 557         return 0;
 558 }
 559
 560 static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata,
 561                                const struct spi_mem_op *op)
 562 {
 563         struct cqspi_st *cqspi = f_pdata->cqspi;
 564         void __iomem *reg_base = cqspi->iobase;
 565         u8 opcode;
 566         const u8 *txbuf = op->data.buf.out;
 567         size_t n_tx = op->data.nbytes;
 568         unsigned int reg;
 569         unsigned int data;
 570         size_t write_len;
 571         int ret;
 572
 573         ret = cqspi_set_protocol(f_pdata, op);
 574         if (ret)
 575                 return ret;
 576
 577         ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB,
 578                                f_pdata->dtr);
 579         if (ret)
 580                 return ret;
 581
 582         if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
 583                 dev_err(&cqspi->pdev->dev,
 584                         "Invalid input argument, cmdlen %zu txbuf 0x%p\n",
 585                         n_tx, txbuf);
 586                 return -EINVAL;
 587         }
 588
 589         reg = cqspi_calc_rdreg(f_pdata);
 590         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 591
 592         if (f_pdata->dtr)
 593                 opcode = op->cmd.opcode >> 8;
 594         else
 595                 opcode = op->cmd.opcode;
 596
 597         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 598
 599         if (op->addr.nbytes) {
 600                 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 601                 reg |= ((op->addr.nbytes - 1) &
 602                         CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 603                         << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 604
 605                 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
 606         }
 607
 608         if (n_tx) {
 609                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 610                 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 611                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 612                 data = 0;
 613                 write_len = (n_tx > 4) ? 4 : n_tx;
 614                 memcpy(&data, txbuf, write_len);
 615                 txbuf += write_len;
 616                 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
 617
 618                 if (n_tx > 4) {
 619                         data = 0;
 620                         write_len = n_tx - 4;
 621                         memcpy(&data, txbuf, write_len);
 622                         writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
 623                 }
 624         }
 625
 626         return cqspi_exec_flash_cmd(cqspi, reg);
 627 }
 628
 629 static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
 630                             const struct spi_mem_op *op)
 631 {
 632         struct cqspi_st *cqspi = f_pdata->cqspi;
 633         void __iomem *reg_base = cqspi->iobase;
 634         unsigned int dummy_clk = 0;
 635         unsigned int reg;
 636         int ret;
 637         u8 opcode;
 638
 639         ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB,
 640                                f_pdata->dtr);
 641         if (ret)
 642                 return ret;
 643
 644         if (f_pdata->dtr)
 645                 opcode = op->cmd.opcode >> 8;
 646         else
 647                 opcode = op->cmd.opcode;
 648
 649         reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 650         reg |= cqspi_calc_rdreg(f_pdata);
 651
 652         /* Setup dummy clock cycles */
 653         dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr);
 654
 655         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 656                 return -EOPNOTSUPP;
 657
 658         if (dummy_clk)
 659                 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 660                        << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 661
 662         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 663
 664         /* Set address width */
 665         reg = readl(reg_base + CQSPI_REG_SIZE);
 666         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 667         reg |= (op->addr.nbytes - 1);
 668         writel(reg, reg_base + CQSPI_REG_SIZE);
 669         return 0;
 670 }
 671
 672 static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
 673                                        u8 *rxbuf, loff_t from_addr,
 674                                        const size_t n_rx)
 675 {
 676         struct cqspi_st *cqspi = f_pdata->cqspi;
 677         struct device *dev = &cqspi->pdev->dev;
 678         void __iomem *reg_base = cqspi->iobase;
 679         void __iomem *ahb_base = cqspi->ahb_base;
 680         unsigned int remaining = n_rx;
 681         unsigned int mod_bytes = n_rx % 4;
 682         unsigned int bytes_to_read = 0;
 683         u8 *rxbuf_end = rxbuf + n_rx;
 684         int ret = 0;
 685
 686         writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
 687         writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
 688
 689         /* Clear all interrupts. */
 690         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 691
 692         writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
 693
 694         reinit_completion(&cqspi->transfer_complete);
 695         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 696                reg_base + CQSPI_REG_INDIRECTRD);
 697
 698         while (remaining > 0) {
 699                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 700                                                  msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
 701                         ret = -ETIMEDOUT;
 702
 703                 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 704
 705                 if (ret && bytes_to_read == 0) {
 706                         dev_err(dev, "Indirect read timeout, no bytes\n");
 707                         goto failrd;
 708                 }
 709
 710                 while (bytes_to_read != 0) {
 711                         unsigned int word_remain = round_down(remaining, 4);
 712
 713                         bytes_to_read *= cqspi->fifo_width;
 714                         bytes_to_read = bytes_to_read > remaining ?
 715                                         remaining : bytes_to_read;
 716                         bytes_to_read = round_down(bytes_to_read, 4);
 717                         /* Read 4 byte word chunks then single bytes */
 718                         if (bytes_to_read) {
 719                                 ioread32_rep(ahb_base, rxbuf,
 720                                              (bytes_to_read / 4));
 721                         } else if (!word_remain && mod_bytes) {
 722                                 unsigned int temp = ioread32(ahb_base);
 723
 724                                 bytes_to_read = mod_bytes;
 725                                 memcpy(rxbuf, &temp, min((unsigned int)
 726                                                          (rxbuf_end - rxbuf),
 727                                                          bytes_to_read));
 728                         }
 729                         rxbuf += bytes_to_read;
 730                         remaining -= bytes_to_read;
 731                         bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 732                 }
 733
 734                 if (remaining > 0)
 735                         reinit_completion(&cqspi->transfer_complete);
 736         }
 737
 738         /* Check indirect done status */
 739         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
 740                                  CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
 741         if (ret) {
 742                 dev_err(dev, "Indirect read completion error (%i)\n", ret);
 743                 goto failrd;
 744         }
 745
 746         /* Disable interrupt */
 747         writel(0, reg_base + CQSPI_REG_IRQMASK);
 748
 749         /* Clear indirect completion status */
 750         writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
 751
 752         return 0;
 753
 754 failrd:
 755         /* Disable interrupt */
 756         writel(0, reg_base + CQSPI_REG_IRQMASK);
 757
 758         /* Cancel the indirect read */
 759         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 760                reg_base + CQSPI_REG_INDIRECTRD);
 761         return ret;
 762 }
 763
 764 static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
 765                              const struct spi_mem_op *op)
 766 {
 767         unsigned int reg;
 768         int ret;
 769         struct cqspi_st *cqspi = f_pdata->cqspi;
 770         void __iomem *reg_base = cqspi->iobase;
 771         u8 opcode;
 772
 773         ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB,
 774                                f_pdata->dtr);
 775         if (ret)
 776                 return ret;
 777
 778         if (f_pdata->dtr)
 779                 opcode = op->cmd.opcode >> 8;
 780         else
 781                 opcode = op->cmd.opcode;
 782
 783         /* Set opcode. */
 784         reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 785         reg |= f_pdata->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
 786         reg |= f_pdata->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
 787         writel(reg, reg_base + CQSPI_REG_WR_INSTR);
 788         reg = cqspi_calc_rdreg(f_pdata);
 789         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 790
 791         /*
 792          * SPI NAND flashes require the address of the status register to be
 793          * passed in the Read SR command. Also, some SPI NOR flashes like the
 794          * cypress Semper flash expect a 4-byte dummy address in the Read SR
 795          * command in DTR mode.
 796          *
 797          * But this controller does not support address phase in the Read SR
 798          * command when doing auto-HW polling. So, disable write completion
 799          * polling on the controller's side. spinand and spi-nor will take
 800          * care of polling the status register.
 801          */
 802         if (cqspi->wr_completion) {
 803                 reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
 804                 reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
 805                 writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
 806         }
 807
 808         reg = readl(reg_base + CQSPI_REG_SIZE);
 809         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 810         reg |= (op->addr.nbytes - 1);
 811         writel(reg, reg_base + CQSPI_REG_SIZE);
 812         return 0;
 813 }
 814
 815 static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
 816                                         loff_t to_addr, const u8 *txbuf,
 817                                         const size_t n_tx)
 818 {
 819         struct cqspi_st *cqspi = f_pdata->cqspi;
 820         struct device *dev = &cqspi->pdev->dev;
 821         void __iomem *reg_base = cqspi->iobase;
 822         unsigned int remaining = n_tx;
 823         unsigned int write_bytes;
 824         int ret;
 825
 826         writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
 827         writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
 828
 829         /* Clear all interrupts. */
 830         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 831
 832         writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
 833
 834         reinit_completion(&cqspi->transfer_complete);
 835         writel(CQSPI_REG_INDIRECTWR_START_MASK,
 836                reg_base + CQSPI_REG_INDIRECTWR);
 837         /*
 838          * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
 839          * Controller programming sequence, couple of cycles of
 840          * QSPI_REF_CLK delay is required for the above bit to
 841          * be internally synchronized by the QSPI module. Provide 5
 842          * cycles of delay.
 843          */
 844         if (cqspi->wr_delay)
 845                 ndelay(cqspi->wr_delay);
 846
 847         while (remaining > 0) {
 848                 size_t write_words, mod_bytes;
 849
 850                 write_bytes = remaining;
 851                 write_words = write_bytes / 4;
 852                 mod_bytes = write_bytes % 4;
 853                 /* Write 4 bytes at a time then single bytes. */
 854                 if (write_words) {
 855                         iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
 856                         txbuf += (write_words * 4);
 857                 }
 858                 if (mod_bytes) {
 859                         unsigned int temp = 0xFFFFFFFF;
 860
 861                         memcpy(&temp, txbuf, mod_bytes);
 862                         iowrite32(temp, cqspi->ahb_base);
 863                         txbuf += mod_bytes;
 864                 }
 865
 866                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 867                                                  msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
 868                         dev_err(dev, "Indirect write timeout\n");
 869                         ret = -ETIMEDOUT;
 870                         goto failwr;
 871                 }
 872
 873                 remaining -= write_bytes;
 874
 875                 if (remaining > 0)
 876                         reinit_completion(&cqspi->transfer_complete);
 877         }
 878
 879         /* Check indirect done status */
 880         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
 881                                  CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
 882         if (ret) {
 883                 dev_err(dev, "Indirect write completion error (%i)\n", ret);
 884                 goto failwr;
 885         }
 886
 887         /* Disable interrupt. */
 888         writel(0, reg_base + CQSPI_REG_IRQMASK);
 889
 890         /* Clear indirect completion status */
 891         writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
 892
 893         cqspi_wait_idle(cqspi);
 894
 895         return 0;
 896
 897 failwr:
 898         /* Disable interrupt. */
 899         writel(0, reg_base + CQSPI_REG_IRQMASK);
 900
 901         /* Cancel the indirect write */
 902         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 903                reg_base + CQSPI_REG_INDIRECTWR);
 904         return ret;
 905 }
 906
 907 static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata)
 908 {
 909         struct cqspi_st *cqspi = f_pdata->cqspi;
 910         void __iomem *reg_base = cqspi->iobase;
 911         unsigned int chip_select = f_pdata->cs;
 912         unsigned int reg;
 913
 914         reg = readl(reg_base + CQSPI_REG_CONFIG);
 915         if (cqspi->is_decoded_cs) {
 916                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
 917         } else {
 918                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
 919
 920                 /* Convert CS if without decoder.
 921                  * CS0 to 4b'1110
 922                  * CS1 to 4b'1101
 923                  * CS2 to 4b'1011
 924                  * CS3 to 4b'0111
 925                  */
 926                 chip_select = 0xF & ~(1 << chip_select);
 927         }
 928
 929         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 930                  << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 931         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 932             << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 933         writel(reg, reg_base + CQSPI_REG_CONFIG);
 934 }
 935
 936 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
 937                                            const unsigned int ns_val)
 938 {
 939         unsigned int ticks;
 940
 941         ticks = ref_clk_hz / 1000;      /* kHz */
 942         ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
 943
 944         return ticks;
 945 }
 946
 947 static void cqspi_delay(struct cqspi_flash_pdata *f_pdata)
 948 {
 949         struct cqspi_st *cqspi = f_pdata->cqspi;
 950         void __iomem *iobase = cqspi->iobase;
 951         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 952         unsigned int tshsl, tchsh, tslch, tsd2d;
 953         unsigned int reg;
 954         unsigned int tsclk;
 955
 956         /* calculate the number of ref ticks for one sclk tick */
 957         tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
 958
 959         tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
 960         /* this particular value must be at least one sclk */
 961         if (tshsl < tsclk)
 962                 tshsl = tsclk;
 963
 964         tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
 965         tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
 966         tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
 967
 968         reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 969                << CQSPI_REG_DELAY_TSHSL_LSB;
 970         reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 971                 << CQSPI_REG_DELAY_TCHSH_LSB;
 972         reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 973                 << CQSPI_REG_DELAY_TSLCH_LSB;
 974         reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 975                 << CQSPI_REG_DELAY_TSD2D_LSB;
 976         writel(reg, iobase + CQSPI_REG_DELAY);
 977 }
 978
 979 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
 980 {
 981         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 982         void __iomem *reg_base = cqspi->iobase;
 983         u32 reg, div;
 984
 985         /* Recalculate the baudrate divisor based on QSPI specification. */
 986         div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
 987
 988         reg = readl(reg_base + CQSPI_REG_CONFIG);
 989         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 990         reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
 991         writel(reg, reg_base + CQSPI_REG_CONFIG);
 992 }
 993
 994 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
 995                                    const bool bypass,
 996                                    const unsigned int delay)
 997 {
 998         void __iomem *reg_base = cqspi->iobase;
 999         unsigned int reg;
1000
1001         reg = readl(reg_base + CQSPI_REG_READCAPTURE);
1002
1003         if (bypass)
1004                 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
1005         else
1006                 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
1007
1008         reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
1009                  << CQSPI_REG_READCAPTURE_DELAY_LSB);
1010
1011         reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
1012                 << CQSPI_REG_READCAPTURE_DELAY_LSB;
1013
1014         writel(reg, reg_base + CQSPI_REG_READCAPTURE);
1015 }
1016
1017 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
1018 {
1019         void __iomem *reg_base = cqspi->iobase;
1020         unsigned int reg;
1021
1022         reg = readl(reg_base + CQSPI_REG_CONFIG);
1023
1024         if (enable)
1025                 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
1026         else
1027                 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
1028
1029         writel(reg, reg_base + CQSPI_REG_CONFIG);
1030 }
1031
1032 static void cqspi_configure(struct cqspi_flash_pdata *f_pdata,
1033                             unsigned long sclk)
1034 {
1035         struct cqspi_st *cqspi = f_pdata->cqspi;
1036         int switch_cs = (cqspi->current_cs != f_pdata->cs);
1037         int switch_ck = (cqspi->sclk != sclk);
1038
1039         if (switch_cs || switch_ck)
1040                 cqspi_controller_enable(cqspi, 0);
1041
1042         /* Switch chip select. */
1043         if (switch_cs) {
1044                 cqspi->current_cs = f_pdata->cs;
1045                 cqspi_chipselect(f_pdata);
1046         }
1047
1048         /* Setup baudrate divisor and delays */
1049         if (switch_ck) {
1050                 cqspi->sclk = sclk;
1051                 cqspi_config_baudrate_div(cqspi);
1052                 cqspi_delay(f_pdata);
1053                 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
1054                                        f_pdata->read_delay);
1055         }
1056
1057         if (switch_cs || switch_ck)
1058                 cqspi_controller_enable(cqspi, 1);
1059 }
1060
1061 static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
1062                            const struct spi_mem_op *op)
1063 {
1064         struct cqspi_st *cqspi = f_pdata->cqspi;
1065         loff_t to = op->addr.val;
1066         size_t len = op->data.nbytes;
1067         const u_char *buf = op->data.buf.out;
1068         int ret;
1069
1070         ret = cqspi_set_protocol(f_pdata, op);
1071         if (ret)
1072                 return ret;
1073
1074         ret = cqspi_write_setup(f_pdata, op);
1075         if (ret)
1076                 return ret;
1077
1078         /*
1079          * Some flashes like the Cypress Semper flash expect a dummy 4-byte
1080          * address (all 0s) with the read status register command in DTR mode.
1081          * But this controller does not support sending dummy address bytes to
1082          * the flash when it is polling the write completion register in DTR
1083          * mode. So, we can not use direct mode when in DTR mode for writing
1084          * data.
1085          */
1086         if (!f_pdata->dtr && cqspi->use_direct_mode &&
1087             ((to + len) <= cqspi->ahb_size)) {
1088                 memcpy_toio(cqspi->ahb_base + to, buf, len);
1089                 return cqspi_wait_idle(cqspi);
1090         }
1091
1092         return cqspi_indirect_write_execute(f_pdata, to, buf, len);
1093 }
1094
1095 static void cqspi_rx_dma_callback(void *param)
1096 {
1097         struct cqspi_st *cqspi = param;
1098
1099         complete(&cqspi->rx_dma_complete);
1100 }
1101
1102 static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
1103                                      u_char *buf, loff_t from, size_t len)
1104 {
1105         struct cqspi_st *cqspi = f_pdata->cqspi;
1106         struct device *dev = &cqspi->pdev->dev;
1107         enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
1108         dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
1109         int ret = 0;
1110         struct dma_async_tx_descriptor *tx;
1111         dma_cookie_t cookie;
1112         dma_addr_t dma_dst;
1113         struct device *ddev;
1114
1115         if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
1116                 memcpy_fromio(buf, cqspi->ahb_base + from, len);
1117                 return 0;
1118         }
1119
1120         ddev = cqspi->rx_chan->device->dev;
1121         dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE);
1122         if (dma_mapping_error(ddev, dma_dst)) {
1123                 dev_err(dev, "dma mapping failed\n");
1124                 return -ENOMEM;
1125         }
1126         tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
1127                                        len, flags);
1128         if (!tx) {
1129                 dev_err(dev, "device_prep_dma_memcpy error\n");
1130                 ret = -EIO;
1131                 goto err_unmap;
1132         }
1133
1134         tx->callback = cqspi_rx_dma_callback;
1135         tx->callback_param = cqspi;
1136         cookie = tx->tx_submit(tx);
1137         reinit_completion(&cqspi->rx_dma_complete);
1138
1139         ret = dma_submit_error(cookie);
1140         if (ret) {
1141                 dev_err(dev, "dma_submit_error %d\n", cookie);
1142                 ret = -EIO;
1143                 goto err_unmap;
1144         }
1145
1146         dma_async_issue_pending(cqspi->rx_chan);
1147         if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
1148                                          msecs_to_jiffies(max_t(size_t, len, 500)))) {
1149                 dmaengine_terminate_sync(cqspi->rx_chan);
1150                 dev_err(dev, "DMA wait_for_completion_timeout\n");
1151                 ret = -ETIMEDOUT;
1152                 goto err_unmap;
1153         }
1154
1155 err_unmap:
1156         dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE);
1157
1158         return ret;
1159 }
1160
1161 static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
1162                           const struct spi_mem_op *op)
1163 {
1164         struct cqspi_st *cqspi = f_pdata->cqspi;
1165         loff_t from = op->addr.val;
1166         size_t len = op->data.nbytes;
1167         u_char *buf = op->data.buf.in;
1168         int ret;
1169
1170         ret = cqspi_set_protocol(f_pdata, op);
1171         if (ret)
1172                 return ret;
1173
1174         ret = cqspi_read_setup(f_pdata, op);
1175         if (ret)
1176                 return ret;
1177
1178         if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
1179                 return cqspi_direct_read_execute(f_pdata, buf, from, len);
1180
1181         return cqspi_indirect_read_execute(f_pdata, buf, from, len);
1182 }
1183
1184 static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
1185 {
1186         struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
1187         struct cqspi_flash_pdata *f_pdata;
1188
1189         f_pdata = &cqspi->f_pdata[mem->spi->chip_select];
1190         cqspi_configure(f_pdata, mem->spi->max_speed_hz);
1191
1192         if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
1193                 if (!op->addr.nbytes)
1194                         return cqspi_command_read(f_pdata, op);
1195
1196                 return cqspi_read(f_pdata, op);
1197         }
1198
1199         if (!op->addr.nbytes || !op->data.buf.out)
1200                 return cqspi_command_write(f_pdata, op);
1201
1202         return cqspi_write(f_pdata, op);
1203 }
1204
1205 static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
1206 {
1207         int ret;
1208
1209         ret = cqspi_mem_process(mem, op);
1210         if (ret)
1211                 dev_err(&mem->spi->dev, "operation failed with %d\n", ret);
1212
1213         return ret;
1214 }
1215
1216 static bool cqspi_supports_mem_op(struct spi_mem *mem,
1217                                   const struct spi_mem_op *op)
1218 {
1219         bool all_true, all_false;
1220
1221         /*
1222          * op->dummy.dtr is required for converting nbytes into ncycles.
1223          * Also, don't check the dtr field of the op phase having zero nbytes.
1224          */
1225         all_true = op->cmd.dtr &&
1226                    (!op->addr.nbytes || op->addr.dtr) &&
1227                    (!op->dummy.nbytes || op->dummy.dtr) &&
1228                    (!op->data.nbytes || op->data.dtr);
1229
1230         all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
1231                     !op->data.dtr;
1232
1233         if (all_true) {
1234                 /* Right now we only support 8-8-8 DTR mode. */
1235                 if (op->cmd.nbytes && op->cmd.buswidth != 8)
1236                         return false;
1237                 if (op->addr.nbytes && op->addr.buswidth != 8)
1238                         return false;
1239                 if (op->data.nbytes && op->data.buswidth != 8)
1240                         return false;
1241         } else if (all_false) {
1242                 /* Only 1-1-X ops are supported without DTR */
1243                 if (op->cmd.nbytes && op->cmd.buswidth > 1)
1244                         return false;
1245                 if (op->addr.nbytes && op->addr.buswidth > 1)
1246                         return false;
1247         } else {
1248                 /* Mixed DTR modes are not supported. */
1249                 return false;
1250         }
1251
1252         if (all_true)
1253                 return spi_mem_dtr_supports_op(mem, op);
1254         else
1255                 return spi_mem_default_supports_op(mem, op);
1256 }
1257
1258 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1259                                     struct cqspi_flash_pdata *f_pdata,
1260                                     struct device_node *np)
1261 {
1262         if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1263                 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1264                 return -ENXIO;
1265         }
1266
1267         if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1268                 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1269                 return -ENXIO;
1270         }
1271
1272         if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1273                 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1274                 return -ENXIO;
1275         }
1276
1277         if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1278                 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1279                 return -ENXIO;
1280         }
1281
1282         if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1283                 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1284                 return -ENXIO;
1285         }
1286
1287         if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1288                 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1289                 return -ENXIO;
1290         }
1291
1292         return 0;
1293 }
1294
1295 static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
1296 {
1297         struct device *dev = &cqspi->pdev->dev;
1298         struct device_node *np = dev->of_node;
1299
1300         cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1301
1302         if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1303                 dev_err(dev, "couldn't determine fifo-depth\n");
1304                 return -ENXIO;
1305         }
1306
1307         if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1308                 dev_err(dev, "couldn't determine fifo-width\n");
1309                 return -ENXIO;
1310         }
1311
1312         if (of_property_read_u32(np, "cdns,trigger-address",
1313                                  &cqspi->trigger_address)) {
1314                 dev_err(dev, "couldn't determine trigger-address\n");
1315                 return -ENXIO;
1316         }
1317
1318         if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
1319                 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;
1320
1321         cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1322
1323         return 0;
1324 }
1325
1326 static void cqspi_controller_init(struct cqspi_st *cqspi)
1327 {
1328         u32 reg;
1329
1330         cqspi_controller_enable(cqspi, 0);
1331
1332         /* Configure the remap address register, no remap */
1333         writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1334
1335         /* Disable all interrupts. */
1336         writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1337
1338         /* Configure the SRAM split to 1:1 . */
1339         writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1340
1341         /* Load indirect trigger address. */
1342         writel(cqspi->trigger_address,
1343                cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1344
1345         /* Program read watermark -- 1/2 of the FIFO. */
1346         writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1347                cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1348         /* Program write watermark -- 1/8 of the FIFO. */
1349         writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1350                cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1351
1352         /* Disable direct access controller */
1353         if (!cqspi->use_direct_mode) {
1354                 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1355                 reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1356                 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1357         }
1358
1359         cqspi_controller_enable(cqspi, 1);
1360 }
1361
1362 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1363 {
1364         dma_cap_mask_t mask;
1365
1366         dma_cap_zero(mask);
1367         dma_cap_set(DMA_MEMCPY, mask);
1368
1369         cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1370         if (IS_ERR(cqspi->rx_chan)) {
1371                 int ret = PTR_ERR(cqspi->rx_chan);
1372                 cqspi->rx_chan = NULL;
1373                 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");
1374         }
1375         init_completion(&cqspi->rx_dma_complete);
1376
1377         return 0;
1378 }
1379
1380 static const char *cqspi_get_name(struct spi_mem *mem)
1381 {
1382         struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
1383         struct device *dev = &cqspi->pdev->dev;
1384
1385         return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
1386 }
1387
1388 static const struct spi_controller_mem_ops cqspi_mem_ops = {
1389         .exec_op = cqspi_exec_mem_op,
1390         .get_name = cqspi_get_name,
1391         .supports_op = cqspi_supports_mem_op,
1392 };
1393
1394 static int cqspi_setup_flash(struct cqspi_st *cqspi)
1395 {
1396         struct platform_device *pdev = cqspi->pdev;
1397         struct device *dev = &pdev->dev;
1398         struct device_node *np = dev->of_node;
1399         struct cqspi_flash_pdata *f_pdata;
1400         unsigned int cs;
1401         int ret;
1402
1403         /* Get flash device data */
1404         for_each_available_child_of_node(dev->of_node, np) {
1405                 ret = of_property_read_u32(np, "reg", &cs);
1406                 if (ret) {
1407                         dev_err(dev, "Couldn't determine chip select.\n");
1408                         of_node_put(np);
1409                         return ret;
1410                 }
1411
1412                 if (cs >= CQSPI_MAX_CHIPSELECT) {
1413                         dev_err(dev, "Chip select %d out of range.\n", cs);
1414                         of_node_put(np);
1415                         return -EINVAL;
1416                 }
1417
1418                 f_pdata = &cqspi->f_pdata[cs];
1419                 f_pdata->cqspi = cqspi;
1420                 f_pdata->cs = cs;
1421
1422                 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1423                 if (ret) {
1424                         of_node_put(np);
1425                         return ret;
1426                 }
1427         }
1428
1429         return 0;
1430 }
1431
1432 static int cqspi_probe(struct platform_device *pdev)
1433 {
1434         const struct cqspi_driver_platdata *ddata;
1435         struct reset_control *rstc, *rstc_ocp;
1436         struct device *dev = &pdev->dev;
1437         struct spi_master *master;
1438         struct resource *res_ahb;
1439         struct cqspi_st *cqspi;
1440         struct resource *res;
1441         int ret;
1442         int irq;
1443
1444         master = spi_alloc_master(&pdev->dev, sizeof(*cqspi));
1445         if (!master) {
1446                 dev_err(&pdev->dev, "spi_alloc_master failed\n");
1447                 return -ENOMEM;
1448         }
1449         master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
1450         master->mem_ops = &cqspi_mem_ops;
1451         master->dev.of_node = pdev->dev.of_node;
1452
1453         cqspi = spi_master_get_devdata(master);
1454
1455         cqspi->pdev = pdev;
1456         platform_set_drvdata(pdev, cqspi);
1457
1458         /* Obtain configuration from OF. */
1459         ret = cqspi_of_get_pdata(cqspi);
1460         if (ret) {
1461                 dev_err(dev, "Cannot get mandatory OF data.\n");
1462                 ret = -ENODEV;
1463                 goto probe_master_put;
1464         }
1465
1466         /* Obtain QSPI clock. */
1467         cqspi->clk = devm_clk_get(dev, NULL);
1468         if (IS_ERR(cqspi->clk)) {
1469                 dev_err(dev, "Cannot claim QSPI clock.\n");
1470                 ret = PTR_ERR(cqspi->clk);
1471                 goto probe_master_put;
1472         }
1473
1474         /* Obtain and remap controller address. */
1475         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1476         cqspi->iobase = devm_ioremap_resource(dev, res);
1477         if (IS_ERR(cqspi->iobase)) {
1478                 dev_err(dev, "Cannot remap controller address.\n");
1479                 ret = PTR_ERR(cqspi->iobase);
1480                 goto probe_master_put;
1481         }
1482
1483         /* Obtain and remap AHB address. */
1484         res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1485         cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1486         if (IS_ERR(cqspi->ahb_base)) {
1487                 dev_err(dev, "Cannot remap AHB address.\n");
1488                 ret = PTR_ERR(cqspi->ahb_base);
1489                 goto probe_master_put;
1490         }
1491         cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1492         cqspi->ahb_size = resource_size(res_ahb);
1493
1494         init_completion(&cqspi->transfer_complete);
1495
1496         /* Obtain IRQ line. */
1497         irq = platform_get_irq(pdev, 0);
1498         if (irq < 0) {
1499                 ret = -ENXIO;
1500                 goto probe_master_put;
1501         }
1502
1503         pm_runtime_enable(dev);
1504         ret = pm_runtime_get_sync(dev);
1505         if (ret < 0) {
1506                 pm_runtime_put_noidle(dev);
1507                 goto probe_master_put;
1508         }
1509
1510         ret = clk_prepare_enable(cqspi->clk);
1511         if (ret) {
1512                 dev_err(dev, "Cannot enable QSPI clock.\n");
1513                 goto probe_clk_failed;
1514         }
1515
1516         /* Obtain QSPI reset control */
1517         rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
1518         if (IS_ERR(rstc)) {
1519                 ret = PTR_ERR(rstc);
1520                 dev_err(dev, "Cannot get QSPI reset.\n");
1521                 goto probe_reset_failed;
1522         }
1523
1524         rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
1525         if (IS_ERR(rstc_ocp)) {
1526                 ret = PTR_ERR(rstc_ocp);
1527                 dev_err(dev, "Cannot get QSPI OCP reset.\n");
1528                 goto probe_reset_failed;
1529         }
1530
1531         reset_control_assert(rstc);
1532         reset_control_deassert(rstc);
1533
1534         reset_control_assert(rstc_ocp);
1535         reset_control_deassert(rstc_ocp);
1536
1537         cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1538         master->max_speed_hz = cqspi->master_ref_clk_hz;
1539
1540         /* write completion is supported by default */
1541         cqspi->wr_completion = true;
1542
1543         ddata  = of_device_get_match_data(dev);
1544         if (ddata) {
1545                 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
1546                         cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
1547                                                 cqspi->master_ref_clk_hz);
1548                 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
1549                         master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
1550                 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE))
1551                         cqspi->use_direct_mode = true;
1552                 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION)
1553                         cqspi->wr_completion = false;
1554         }
1555
1556         ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1557                                pdev->name, cqspi);
1558         if (ret) {
1559                 dev_err(dev, "Cannot request IRQ.\n");
1560                 goto probe_reset_failed;
1561         }
1562
1563         cqspi_wait_idle(cqspi);
1564         cqspi_controller_init(cqspi);
1565         cqspi->current_cs = -1;
1566         cqspi->sclk = 0;
1567
1568         master->num_chipselect = cqspi->num_chipselect;
1569
1570         ret = cqspi_setup_flash(cqspi);
1571         if (ret) {
1572                 dev_err(dev, "failed to setup flash parameters %d\n", ret);
1573                 goto probe_setup_failed;
1574         }
1575
1576         if (cqspi->use_direct_mode) {
1577                 ret = cqspi_request_mmap_dma(cqspi);
1578                 if (ret == -EPROBE_DEFER)
1579                         goto probe_setup_failed;
1580         }
1581
1582         ret = devm_spi_register_master(dev, master);
1583         if (ret) {
1584                 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
1585                 goto probe_setup_failed;
1586         }
1587
1588         return 0;
1589 probe_setup_failed:
1590         cqspi_controller_enable(cqspi, 0);
1591 probe_reset_failed:
1592         clk_disable_unprepare(cqspi->clk);
1593 probe_clk_failed:
1594         pm_runtime_put_sync(dev);
1595         pm_runtime_disable(dev);
1596 probe_master_put:
1597         spi_master_put(master);
1598         return ret;
1599 }
1600
1601 static int cqspi_remove(struct platform_device *pdev)
1602 {
1603         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1604
1605         cqspi_controller_enable(cqspi, 0);
1606
1607         if (cqspi->rx_chan)
1608                 dma_release_channel(cqspi->rx_chan);
1609
1610         clk_disable_unprepare(cqspi->clk);
1611
1612         pm_runtime_put_sync(&pdev->dev);
1613         pm_runtime_disable(&pdev->dev);
1614
1615         return 0;
1616 }
1617
1618 #ifdef CONFIG_PM_SLEEP
1619 static int cqspi_suspend(struct device *dev)
1620 {
1621         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1622
1623         cqspi_controller_enable(cqspi, 0);
1624         return 0;
1625 }
1626
1627 static int cqspi_resume(struct device *dev)
1628 {
1629         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1630
1631         cqspi_controller_enable(cqspi, 1);
1632         return 0;
1633 }
1634
1635 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1636         .suspend = cqspi_suspend,
1637         .resume = cqspi_resume,
1638 };
1639
1640 #define CQSPI_DEV_PM_OPS        (&cqspi__dev_pm_ops)
1641 #else
1642 #define CQSPI_DEV_PM_OPS        NULL
1643 #endif
1644
1645 static const struct cqspi_driver_platdata cdns_qspi = {
1646         .quirks = CQSPI_DISABLE_DAC_MODE,
1647 };
1648
1649 static const struct cqspi_driver_platdata k2g_qspi = {
1650         .quirks = CQSPI_NEEDS_WR_DELAY,
1651 };
1652
1653 static const struct cqspi_driver_platdata am654_ospi = {
1654         .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
1655         .quirks = CQSPI_NEEDS_WR_DELAY,
1656 };
1657
1658 static const struct cqspi_driver_platdata intel_lgm_qspi = {
1659         .quirks = CQSPI_DISABLE_DAC_MODE,
1660 };
1661
1662 static const struct cqspi_driver_platdata socfpga_qspi = {
1663         .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION,
1664 };
1665
1666 static const struct of_device_id cqspi_dt_ids[] = {
1667         {
1668                 .compatible = "cdns,qspi-nor",
1669                 .data = &cdns_qspi,
1670         },
1671         {
1672                 .compatible = "ti,k2g-qspi",
1673                 .data = &k2g_qspi,
1674         },
1675         {
1676                 .compatible = "ti,am654-ospi",
1677                 .data = &am654_ospi,
1678         },
1679         {
1680                 .compatible = "intel,lgm-qspi",
1681                 .data = &intel_lgm_qspi,
1682         },
1683         {
1684                 .compatible = "intel,socfpga-qspi",
1685                 .data = (void *)&socfpga_qspi,
1686         },
1687         { /* end of table */ }
1688 };
1689
1690 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1691
1692 static struct platform_driver cqspi_platform_driver = {
1693         .probe = cqspi_probe,
1694         .remove = cqspi_remove,
1695         .driver = {
1696                 .name = CQSPI_NAME,
1697                 .pm = CQSPI_DEV_PM_OPS,
1698                 .of_match_table = cqspi_dt_ids,
1699         },
1700 };
1701
1702 module_platform_driver(cqspi_platform_driver);
1703
1704 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1705 MODULE_LICENSE("GPL v2");
1706 MODULE_ALIAS("platform:" CQSPI_NAME);
1707 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1708 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
1709 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
1710 MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>");
1711 MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>");