drivers/spi/spi-cadence-quadspi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 //
   3 // Driver for Cadence QSPI Controller
   4 //
   5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
   6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
   7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
   8
   9 #include <linux/clk.h>
  10 #include <linux/completion.h>
  11 #include <linux/delay.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/dmaengine.h>
  14 #include <linux/err.h>
  15 #include <linux/errno.h>
  16 #include <linux/firmware/xlnx-zynqmp.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/jiffies.h>
  21 #include <linux/kernel.h>
  22 #include <linux/log2.h>
  23 #include <linux/module.h>
  24 #include <linux/of_device.h>
  25 #include <linux/of.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/reset.h>
  29 #include <linux/sched.h>
  30 #include <linux/spi/spi.h>
  31 #include <linux/spi/spi-mem.h>
  32 #include <linux/timer.h>
  33
  34 #define CQSPI_NAME                      "cadence-qspi"
  35 #define CQSPI_MAX_CHIPSELECT            16
  36
  37 /* Quirks */
  38 #define CQSPI_NEEDS_WR_DELAY            BIT(0)
  39 #define CQSPI_DISABLE_DAC_MODE          BIT(1)
  40 #define CQSPI_SUPPORT_EXTERNAL_DMA      BIT(2)
  41 #define CQSPI_NO_SUPPORT_WR_COMPLETION  BIT(3)
  42 #define CQSPI_SLOW_SRAM         BIT(4)
  43
  44 /* Capabilities */
  45 #define CQSPI_SUPPORTS_OCTAL            BIT(0)
  46
  47 #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0)
  48
  49 struct cqspi_st;
  50
  51 struct cqspi_flash_pdata {
  52         struct cqspi_st *cqspi;
  53         u32             clk_rate;
  54         u32             read_delay;
  55         u32             tshsl_ns;
  56         u32             tsd2d_ns;
  57         u32             tchsh_ns;
  58         u32             tslch_ns;
  59         u8              cs;
  60 };
  61
  62 struct cqspi_st {
  63         struct platform_device  *pdev;
  64         struct spi_master       *master;
  65         struct clk              *clk;
  66         unsigned int            sclk;
  67
  68         void __iomem            *iobase;
  69         void __iomem            *ahb_base;
  70         resource_size_t         ahb_size;
  71         struct completion       transfer_complete;
  72
  73         struct dma_chan         *rx_chan;
  74         struct completion       rx_dma_complete;
  75         dma_addr_t              mmap_phys_base;
  76
  77         int                     current_cs;
  78         unsigned long           master_ref_clk_hz;
  79         bool                    is_decoded_cs;
  80         u32                     fifo_depth;
  81         u32                     fifo_width;
  82         u32                     num_chipselect;
  83         bool                    rclk_en;
  84         u32                     trigger_address;
  85         u32                     wr_delay;
  86         bool                    use_direct_mode;
  87         struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
  88         bool                    use_dma_read;
  89         u32                     pd_dev_id;
  90         bool                    wr_completion;
  91         bool                    slow_sram;
  92 };
  93
  94 struct cqspi_driver_platdata {
  95         u32 hwcaps_mask;
  96         u8 quirks;
  97         int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata,
  98                                  u_char *rxbuf, loff_t from_addr, size_t n_rx);
  99         u32 (*get_dma_status)(struct cqspi_st *cqspi);
 100 };
 101
 102 /* Operation timeout value */
 103 #define CQSPI_TIMEOUT_MS                        500
 104 #define CQSPI_READ_TIMEOUT_MS                   10
 105
 106 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
 107 #define CQSPI_DUMMY_BYTES_MAX                   4
 108 #define CQSPI_DUMMY_CLKS_MAX                    31
 109
 110 #define CQSPI_STIG_DATA_LEN_MAX                 8
 111
 112 /* Register map */
 113 #define CQSPI_REG_CONFIG                        0x00
 114 #define CQSPI_REG_CONFIG_ENABLE_MASK            BIT(0)
 115 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL       BIT(7)
 116 #define CQSPI_REG_CONFIG_DECODE_MASK            BIT(9)
 117 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
 118 #define CQSPI_REG_CONFIG_DMA_MASK               BIT(15)
 119 #define CQSPI_REG_CONFIG_BAUD_LSB               19
 120 #define CQSPI_REG_CONFIG_DTR_PROTO              BIT(24)
 121 #define CQSPI_REG_CONFIG_DUAL_OPCODE            BIT(30)
 122 #define CQSPI_REG_CONFIG_IDLE_LSB               31
 123 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
 124 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
 125
 126 #define CQSPI_REG_RD_INSTR                      0x04
 127 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
 128 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
 129 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
 130 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
 131 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
 132 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
 133 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
 134 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
 135 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
 136 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
 137
 138 #define CQSPI_REG_WR_INSTR                      0x08
 139 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
 140 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB        12
 141 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
 142
 143 #define CQSPI_REG_DELAY                         0x0C
 144 #define CQSPI_REG_DELAY_TSLCH_LSB               0
 145 #define CQSPI_REG_DELAY_TCHSH_LSB               8
 146 #define CQSPI_REG_DELAY_TSD2D_LSB               16
 147 #define CQSPI_REG_DELAY_TSHSL_LSB               24
 148 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
 149 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
 150 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
 151 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
 152
 153 #define CQSPI_REG_READCAPTURE                   0x10
 154 #define CQSPI_REG_READCAPTURE_BYPASS_LSB        0
 155 #define CQSPI_REG_READCAPTURE_DELAY_LSB         1
 156 #define CQSPI_REG_READCAPTURE_DELAY_MASK        0xF
 157
 158 #define CQSPI_REG_SIZE                          0x14
 159 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 160 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 161 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 162 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 163 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 164 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 165
 166 #define CQSPI_REG_SRAMPARTITION                 0x18
 167 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 168
 169 #define CQSPI_REG_DMA                           0x20
 170 #define CQSPI_REG_DMA_SINGLE_LSB                0
 171 #define CQSPI_REG_DMA_BURST_LSB                 8
 172 #define CQSPI_REG_DMA_SINGLE_MASK               0xFF
 173 #define CQSPI_REG_DMA_BURST_MASK                0xFF
 174
 175 #define CQSPI_REG_REMAP                         0x24
 176 #define CQSPI_REG_MODE_BIT                      0x28
 177
 178 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 179 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 180 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 181 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 182 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 183
 184 #define CQSPI_REG_WR_COMPLETION_CTRL            0x38
 185 #define CQSPI_REG_WR_DISABLE_AUTO_POLL          BIT(14)
 186
 187 #define CQSPI_REG_IRQSTATUS                     0x40
 188 #define CQSPI_REG_IRQMASK                       0x44
 189
 190 #define CQSPI_REG_INDIRECTRD                    0x60
 191 #define CQSPI_REG_INDIRECTRD_START_MASK         BIT(0)
 192 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        BIT(1)
 193 #define CQSPI_REG_INDIRECTRD_DONE_MASK          BIT(5)
 194
 195 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 196 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 197 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 198
 199 #define CQSPI_REG_CMDCTRL                       0x90
 200 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          BIT(0)
 201 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       BIT(1)
 202 #define CQSPI_REG_CMDCTRL_DUMMY_LSB             7
 203 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 204 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 205 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 206 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 207 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 208 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 209 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 210 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 211 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 212 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 213 #define CQSPI_REG_CMDCTRL_DUMMY_MASK            0x1F
 214
 215 #define CQSPI_REG_INDIRECTWR                    0x70
 216 #define CQSPI_REG_INDIRECTWR_START_MASK         BIT(0)
 217 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        BIT(1)
 218 #define CQSPI_REG_INDIRECTWR_DONE_MASK          BIT(5)
 219
 220 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 221 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 222 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 223
 224 #define CQSPI_REG_INDTRIG_ADDRRANGE             0x80
 225
 226 #define CQSPI_REG_CMDADDRESS                    0x94
 227 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 228 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 229 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 230 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 231
 232 #define CQSPI_REG_POLLING_STATUS                0xB0
 233 #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB      16
 234
 235 #define CQSPI_REG_OP_EXT_LOWER                  0xE0
 236 #define CQSPI_REG_OP_EXT_READ_LSB               24
 237 #define CQSPI_REG_OP_EXT_WRITE_LSB              16
 238 #define CQSPI_REG_OP_EXT_STIG_LSB               0
 239
 240 #define CQSPI_REG_VERSAL_DMA_SRC_ADDR           0x1000
 241
 242 #define CQSPI_REG_VERSAL_DMA_DST_ADDR           0x1800
 243 #define CQSPI_REG_VERSAL_DMA_DST_SIZE           0x1804
 244
 245 #define CQSPI_REG_VERSAL_DMA_DST_CTRL           0x180C
 246
 247 #define CQSPI_REG_VERSAL_DMA_DST_I_STS          0x1814
 248 #define CQSPI_REG_VERSAL_DMA_DST_I_EN           0x1818
 249 #define CQSPI_REG_VERSAL_DMA_DST_I_DIS          0x181C
 250 #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK      BIT(1)
 251
 252 #define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB       0x1828
 253
 254 #define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL       0xF43FFA00
 255 #define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL    0x6
 256
 257 /* Interrupt status bits */
 258 #define CQSPI_REG_IRQ_MODE_ERR                  BIT(0)
 259 #define CQSPI_REG_IRQ_UNDERFLOW                 BIT(1)
 260 #define CQSPI_REG_IRQ_IND_COMP                  BIT(2)
 261 #define CQSPI_REG_IRQ_IND_RD_REJECT             BIT(3)
 262 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR          BIT(4)
 263 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR           BIT(5)
 264 #define CQSPI_REG_IRQ_WATERMARK                 BIT(6)
 265 #define CQSPI_REG_IRQ_IND_SRAM_FULL             BIT(12)
 266
 267 #define CQSPI_IRQ_MASK_RD               (CQSPI_REG_IRQ_WATERMARK        | \
 268                                          CQSPI_REG_IRQ_IND_SRAM_FULL    | \
 269                                          CQSPI_REG_IRQ_IND_COMP)
 270
 271 #define CQSPI_IRQ_MASK_WR               (CQSPI_REG_IRQ_IND_COMP         | \
 272                                          CQSPI_REG_IRQ_WATERMARK        | \
 273                                          CQSPI_REG_IRQ_UNDERFLOW)
 274
 275 #define CQSPI_IRQ_STATUS_MASK           0x1FFFF
 276 #define CQSPI_DMA_UNALIGN               0x3
 277
 278 #define CQSPI_REG_VERSAL_DMA_VAL                0x602
 279
 280 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
 281 {
 282         u32 val;
 283
 284         return readl_relaxed_poll_timeout(reg, val,
 285                                           (((clr ? ~val : val) & mask) == mask),
 286                                           10, CQSPI_TIMEOUT_MS * 1000);
 287 }
 288
 289 static bool cqspi_is_idle(struct cqspi_st *cqspi)
 290 {
 291         u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 292
 293         return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB);
 294 }
 295
 296 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
 297 {
 298         u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
 299
 300         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 301         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 302 }
 303
 304 static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi)
 305 {
 306         u32 dma_status;
 307
 308         dma_status = readl(cqspi->iobase +
 309                                            CQSPI_REG_VERSAL_DMA_DST_I_STS);
 310         writel(dma_status, cqspi->iobase +
 311                    CQSPI_REG_VERSAL_DMA_DST_I_STS);
 312
 313         return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK;
 314 }
 315
 316 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
 317 {
 318         struct cqspi_st *cqspi = dev;
 319         unsigned int irq_status;
 320         struct device *device = &cqspi->pdev->dev;
 321         const struct cqspi_driver_platdata *ddata;
 322
 323         ddata = of_device_get_match_data(device);
 324
 325         /* Read interrupt status */
 326         irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
 327
 328         /* Clear interrupt */
 329         writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
 330
 331         if (cqspi->use_dma_read && ddata && ddata->get_dma_status) {
 332                 if (ddata->get_dma_status(cqspi)) {
 333                         complete(&cqspi->transfer_complete);
 334                         return IRQ_HANDLED;
 335                 }
 336         }
 337
 338         else if (!cqspi->slow_sram)
 339                 irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
 340         else
 341                 irq_status &= CQSPI_REG_IRQ_WATERMARK | CQSPI_IRQ_MASK_WR;
 342
 343         if (irq_status)
 344                 complete(&cqspi->transfer_complete);
 345
 346         return IRQ_HANDLED;
 347 }
 348
 349 static unsigned int cqspi_calc_rdreg(const struct spi_mem_op *op)
 350 {
 351         u32 rdreg = 0;
 352
 353         rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
 354         rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
 355         rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 356
 357         return rdreg;
 358 }
 359
 360 static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op)
 361 {
 362         unsigned int dummy_clk;
 363
 364         if (!op->dummy.nbytes)
 365                 return 0;
 366
 367         dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
 368         if (op->cmd.dtr)
 369                 dummy_clk /= 2;
 370
 371         return dummy_clk;
 372 }
 373
 374 static int cqspi_wait_idle(struct cqspi_st *cqspi)
 375 {
 376         const unsigned int poll_idle_retry = 3;
 377         unsigned int count = 0;
 378         unsigned long timeout;
 379
 380         timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 381         while (1) {
 382                 /*
 383                  * Read few times in succession to ensure the controller
 384                  * is indeed idle, that is, the bit does not transition
 385                  * low again.
 386                  */
 387                 if (cqspi_is_idle(cqspi))
 388                         count++;
 389                 else
 390                         count = 0;
 391
 392                 if (count >= poll_idle_retry)
 393                         return 0;
 394
 395                 if (time_after(jiffies, timeout)) {
 396                         /* Timeout, in busy mode. */
 397                         dev_err(&cqspi->pdev->dev,
 398                                 "QSPI is still busy after %dms timeout.\n",
 399                                 CQSPI_TIMEOUT_MS);
 400                         return -ETIMEDOUT;
 401                 }
 402
 403                 cpu_relax();
 404         }
 405 }
 406
 407 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
 408 {
 409         void __iomem *reg_base = cqspi->iobase;
 410         int ret;
 411
 412         /* Write the CMDCTRL without start execution. */
 413         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 414         /* Start execute */
 415         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 416         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 417
 418         /* Polling for completion. */
 419         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
 420                                  CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
 421         if (ret) {
 422                 dev_err(&cqspi->pdev->dev,
 423                         "Flash command execution timed out.\n");
 424                 return ret;
 425         }
 426
 427         /* Polling QSPI idle status. */
 428         return cqspi_wait_idle(cqspi);
 429 }
 430
 431 static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata,
 432                                   const struct spi_mem_op *op,
 433                                   unsigned int shift)
 434 {
 435         struct cqspi_st *cqspi = f_pdata->cqspi;
 436         void __iomem *reg_base = cqspi->iobase;
 437         unsigned int reg;
 438         u8 ext;
 439
 440         if (op->cmd.nbytes != 2)
 441                 return -EINVAL;
 442
 443         /* Opcode extension is the LSB. */
 444         ext = op->cmd.opcode & 0xff;
 445
 446         reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER);
 447         reg &= ~(0xff << shift);
 448         reg |= ext << shift;
 449         writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER);
 450
 451         return 0;
 452 }
 453
 454 static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata,
 455                             const struct spi_mem_op *op, unsigned int shift)
 456 {
 457         struct cqspi_st *cqspi = f_pdata->cqspi;
 458         void __iomem *reg_base = cqspi->iobase;
 459         unsigned int reg;
 460         int ret;
 461
 462         reg = readl(reg_base + CQSPI_REG_CONFIG);
 463
 464         /*
 465          * We enable dual byte opcode here. The callers have to set up the
 466          * extension opcode based on which type of operation it is.
 467          */
 468         if (op->cmd.dtr) {
 469                 reg |= CQSPI_REG_CONFIG_DTR_PROTO;
 470                 reg |= CQSPI_REG_CONFIG_DUAL_OPCODE;
 471
 472                 /* Set up command opcode extension. */
 473                 ret = cqspi_setup_opcode_ext(f_pdata, op, shift);
 474                 if (ret)
 475                         return ret;
 476         } else {
 477                 reg &= ~CQSPI_REG_CONFIG_DTR_PROTO;
 478                 reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE;
 479         }
 480
 481         writel(reg, reg_base + CQSPI_REG_CONFIG);
 482
 483         return cqspi_wait_idle(cqspi);
 484 }
 485
 486 static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
 487                               const struct spi_mem_op *op)
 488 {
 489         struct cqspi_st *cqspi = f_pdata->cqspi;
 490         void __iomem *reg_base = cqspi->iobase;
 491         u8 *rxbuf = op->data.buf.in;
 492         u8 opcode;
 493         size_t n_rx = op->data.nbytes;
 494         unsigned int rdreg;
 495         unsigned int reg;
 496         unsigned int dummy_clk;
 497         size_t read_len;
 498         int status;
 499
 500         status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB);
 501         if (status)
 502                 return status;
 503
 504         if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 505                 dev_err(&cqspi->pdev->dev,
 506                         "Invalid input argument, len %zu rxbuf 0x%p\n",
 507                         n_rx, rxbuf);
 508                 return -EINVAL;
 509         }
 510
 511         if (op->cmd.dtr)
 512                 opcode = op->cmd.opcode >> 8;
 513         else
 514                 opcode = op->cmd.opcode;
 515
 516         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 517
 518         rdreg = cqspi_calc_rdreg(op);
 519         writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
 520
 521         dummy_clk = cqspi_calc_dummy(op);
 522         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 523                 return -EOPNOTSUPP;
 524
 525         if (dummy_clk)
 526                 reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)
 527                      << CQSPI_REG_CMDCTRL_DUMMY_LSB;
 528
 529         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 530
 531         /* 0 means 1 byte. */
 532         reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 533                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 534         status = cqspi_exec_flash_cmd(cqspi, reg);
 535         if (status)
 536                 return status;
 537
 538         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 539
 540         /* Put the read value into rx_buf */
 541         read_len = (n_rx > 4) ? 4 : n_rx;
 542         memcpy(rxbuf, &reg, read_len);
 543         rxbuf += read_len;
 544
 545         if (n_rx > 4) {
 546                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 547
 548                 read_len = n_rx - read_len;
 549                 memcpy(rxbuf, &reg, read_len);
 550         }
 551
 552         return 0;
 553 }
 554
 555 static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata,
 556                                const struct spi_mem_op *op)
 557 {
 558         struct cqspi_st *cqspi = f_pdata->cqspi;
 559         void __iomem *reg_base = cqspi->iobase;
 560         u8 opcode;
 561         const u8 *txbuf = op->data.buf.out;
 562         size_t n_tx = op->data.nbytes;
 563         unsigned int reg;
 564         unsigned int data;
 565         size_t write_len;
 566         int ret;
 567
 568         ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB);
 569         if (ret)
 570                 return ret;
 571
 572         if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
 573                 dev_err(&cqspi->pdev->dev,
 574                         "Invalid input argument, cmdlen %zu txbuf 0x%p\n",
 575                         n_tx, txbuf);
 576                 return -EINVAL;
 577         }
 578
 579         reg = cqspi_calc_rdreg(op);
 580         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 581
 582         if (op->cmd.dtr)
 583                 opcode = op->cmd.opcode >> 8;
 584         else
 585                 opcode = op->cmd.opcode;
 586
 587         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 588
 589         if (op->addr.nbytes) {
 590                 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 591                 reg |= ((op->addr.nbytes - 1) &
 592                         CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 593                         << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 594
 595                 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
 596         }
 597
 598         if (n_tx) {
 599                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 600                 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 601                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 602                 data = 0;
 603                 write_len = (n_tx > 4) ? 4 : n_tx;
 604                 memcpy(&data, txbuf, write_len);
 605                 txbuf += write_len;
 606                 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
 607
 608                 if (n_tx > 4) {
 609                         data = 0;
 610                         write_len = n_tx - 4;
 611                         memcpy(&data, txbuf, write_len);
 612                         writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
 613                 }
 614         }
 615
 616         return cqspi_exec_flash_cmd(cqspi, reg);
 617 }
 618
 619 static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
 620                             const struct spi_mem_op *op)
 621 {
 622         struct cqspi_st *cqspi = f_pdata->cqspi;
 623         void __iomem *reg_base = cqspi->iobase;
 624         unsigned int dummy_clk = 0;
 625         unsigned int reg;
 626         int ret;
 627         u8 opcode;
 628
 629         ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB);
 630         if (ret)
 631                 return ret;
 632
 633         if (op->cmd.dtr)
 634                 opcode = op->cmd.opcode >> 8;
 635         else
 636                 opcode = op->cmd.opcode;
 637
 638         reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 639         reg |= cqspi_calc_rdreg(op);
 640
 641         /* Setup dummy clock cycles */
 642         dummy_clk = cqspi_calc_dummy(op);
 643
 644         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 645                 return -EOPNOTSUPP;
 646
 647         if (dummy_clk)
 648                 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 649                        << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 650
 651         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 652
 653         /* Set address width */
 654         reg = readl(reg_base + CQSPI_REG_SIZE);
 655         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 656         reg |= (op->addr.nbytes - 1);
 657         writel(reg, reg_base + CQSPI_REG_SIZE);
 658         return 0;
 659 }
 660
 661 static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
 662                                        u8 *rxbuf, loff_t from_addr,
 663                                        const size_t n_rx)
 664 {
 665         struct cqspi_st *cqspi = f_pdata->cqspi;
 666         struct device *dev = &cqspi->pdev->dev;
 667         void __iomem *reg_base = cqspi->iobase;
 668         void __iomem *ahb_base = cqspi->ahb_base;
 669         unsigned int remaining = n_rx;
 670         unsigned int mod_bytes = n_rx % 4;
 671         unsigned int bytes_to_read = 0;
 672         u8 *rxbuf_end = rxbuf + n_rx;
 673         int ret = 0;
 674
 675         writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
 676         writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
 677
 678         /* Clear all interrupts. */
 679         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 680
 681         /*
 682          * On SoCFPGA platform reading the SRAM is slow due to
 683          * hardware limitation and causing read interrupt storm to CPU,
 684          * so enabling only watermark interrupt to disable all read
 685          * interrupts later as we want to run "bytes to read" loop with
 686          * all the read interrupts disabled for max performance.
 687          */
 688
 689         if (!cqspi->slow_sram)
 690                 writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
 691         else
 692                 writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
 693
 694         reinit_completion(&cqspi->transfer_complete);
 695         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 696                reg_base + CQSPI_REG_INDIRECTRD);
 697
 698         while (remaining > 0) {
 699                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 700                                                  msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
 701                         ret = -ETIMEDOUT;
 702
 703                 /*
 704                  * Disable all read interrupts until
 705                  * we are out of "bytes to read"
 706                  */
 707                 if (cqspi->slow_sram)
 708                         writel(0x0, reg_base + CQSPI_REG_IRQMASK);
 709
 710                 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 711
 712                 if (ret && bytes_to_read == 0) {
 713                         dev_err(dev, "Indirect read timeout, no bytes\n");
 714                         goto failrd;
 715                 }
 716
 717                 while (bytes_to_read != 0) {
 718                         unsigned int word_remain = round_down(remaining, 4);
 719
 720                         bytes_to_read *= cqspi->fifo_width;
 721                         bytes_to_read = bytes_to_read > remaining ?
 722                                         remaining : bytes_to_read;
 723                         bytes_to_read = round_down(bytes_to_read, 4);
 724                         /* Read 4 byte word chunks then single bytes */
 725                         if (bytes_to_read) {
 726                                 ioread32_rep(ahb_base, rxbuf,
 727                                              (bytes_to_read / 4));
 728                         } else if (!word_remain && mod_bytes) {
 729                                 unsigned int temp = ioread32(ahb_base);
 730
 731                                 bytes_to_read = mod_bytes;
 732                                 memcpy(rxbuf, &temp, min((unsigned int)
 733                                                          (rxbuf_end - rxbuf),
 734                                                          bytes_to_read));
 735                         }
 736                         rxbuf += bytes_to_read;
 737                         remaining -= bytes_to_read;
 738                         bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 739                 }
 740
 741                 if (remaining > 0) {
 742                         reinit_completion(&cqspi->transfer_complete);
 743                         if (cqspi->slow_sram)
 744                                 writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
 745                 }
 746         }
 747
 748         /* Check indirect done status */
 749         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
 750                                  CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
 751         if (ret) {
 752                 dev_err(dev, "Indirect read completion error (%i)\n", ret);
 753                 goto failrd;
 754         }
 755
 756         /* Disable interrupt */
 757         writel(0, reg_base + CQSPI_REG_IRQMASK);
 758
 759         /* Clear indirect completion status */
 760         writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
 761
 762         return 0;
 763
 764 failrd:
 765         /* Disable interrupt */
 766         writel(0, reg_base + CQSPI_REG_IRQMASK);
 767
 768         /* Cancel the indirect read */
 769         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 770                reg_base + CQSPI_REG_INDIRECTRD);
 771         return ret;
 772 }
 773
 774 static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata,
 775                                           u_char *rxbuf, loff_t from_addr,
 776                                           size_t n_rx)
 777 {
 778         struct cqspi_st *cqspi = f_pdata->cqspi;
 779         struct device *dev = &cqspi->pdev->dev;
 780         void __iomem *reg_base = cqspi->iobase;
 781         u32 reg, bytes_to_dma;
 782         loff_t addr = from_addr;
 783         void *buf = rxbuf;
 784         dma_addr_t dma_addr;
 785         u8 bytes_rem;
 786         int ret = 0;
 787
 788         bytes_rem = n_rx % 4;
 789         bytes_to_dma = (n_rx - bytes_rem);
 790
 791         if (!bytes_to_dma)
 792                 goto nondmard;
 793
 794         ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA);
 795         if (ret)
 796                 return ret;
 797
 798         reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 799         reg |= CQSPI_REG_CONFIG_DMA_MASK;
 800         writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
 801
 802         dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE);
 803         if (dma_mapping_error(dev, dma_addr)) {
 804                 dev_err(dev, "dma mapping failed\n");
 805                 return -ENOMEM;
 806         }
 807
 808         writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
 809         writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES);
 810         writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL,
 811                reg_base + CQSPI_REG_INDTRIG_ADDRRANGE);
 812
 813         /* Clear all interrupts. */
 814         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 815
 816         /* Enable DMA done interrupt */
 817         writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK,
 818                reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN);
 819
 820         /* Default DMA periph configuration */
 821         writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA);
 822
 823         /* Configure DMA Dst address */
 824         writel(lower_32_bits(dma_addr),
 825                reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR);
 826         writel(upper_32_bits(dma_addr),
 827                reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB);
 828
 829         /* Configure DMA Src address */
 830         writel(cqspi->trigger_address, reg_base +
 831                CQSPI_REG_VERSAL_DMA_SRC_ADDR);
 832
 833         /* Set DMA destination size */
 834         writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE);
 835
 836         /* Set DMA destination control */
 837         writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL,
 838                reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL);
 839
 840         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 841                reg_base + CQSPI_REG_INDIRECTRD);
 842
 843         reinit_completion(&cqspi->transfer_complete);
 844
 845         if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 846                                          msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) {
 847                 ret = -ETIMEDOUT;
 848                 goto failrd;
 849         }
 850
 851         /* Disable DMA interrupt */
 852         writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
 853
 854         /* Clear indirect completion status */
 855         writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
 856                cqspi->iobase + CQSPI_REG_INDIRECTRD);
 857         dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE);
 858
 859         reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 860         reg &= ~CQSPI_REG_CONFIG_DMA_MASK;
 861         writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
 862
 863         ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id,
 864                                         PM_OSPI_MUX_SEL_LINEAR);
 865         if (ret)
 866                 return ret;
 867
 868 nondmard:
 869         if (bytes_rem) {
 870                 addr += bytes_to_dma;
 871                 buf += bytes_to_dma;
 872                 ret = cqspi_indirect_read_execute(f_pdata, buf, addr,
 873                                                   bytes_rem);
 874                 if (ret)
 875                         return ret;
 876         }
 877
 878         return 0;
 879
 880 failrd:
 881         /* Disable DMA interrupt */
 882         writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
 883
 884         /* Cancel the indirect read */
 885         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 886                reg_base + CQSPI_REG_INDIRECTRD);
 887
 888         dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE);
 889
 890         reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 891         reg &= ~CQSPI_REG_CONFIG_DMA_MASK;
 892         writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
 893
 894         zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR);
 895
 896         return ret;
 897 }
 898
 899 static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
 900                              const struct spi_mem_op *op)
 901 {
 902         unsigned int reg;
 903         int ret;
 904         struct cqspi_st *cqspi = f_pdata->cqspi;
 905         void __iomem *reg_base = cqspi->iobase;
 906         u8 opcode;
 907
 908         ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB);
 909         if (ret)
 910                 return ret;
 911
 912         if (op->cmd.dtr)
 913                 opcode = op->cmd.opcode >> 8;
 914         else
 915                 opcode = op->cmd.opcode;
 916
 917         /* Set opcode. */
 918         reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 919         reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
 920         reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
 921         writel(reg, reg_base + CQSPI_REG_WR_INSTR);
 922         reg = cqspi_calc_rdreg(op);
 923         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 924
 925         /*
 926          * SPI NAND flashes require the address of the status register to be
 927          * passed in the Read SR command. Also, some SPI NOR flashes like the
 928          * cypress Semper flash expect a 4-byte dummy address in the Read SR
 929          * command in DTR mode.
 930          *
 931          * But this controller does not support address phase in the Read SR
 932          * command when doing auto-HW polling. So, disable write completion
 933          * polling on the controller's side. spinand and spi-nor will take
 934          * care of polling the status register.
 935          */
 936         if (cqspi->wr_completion) {
 937                 reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
 938                 reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
 939                 writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
 940         }
 941
 942         reg = readl(reg_base + CQSPI_REG_SIZE);
 943         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 944         reg |= (op->addr.nbytes - 1);
 945         writel(reg, reg_base + CQSPI_REG_SIZE);
 946         return 0;
 947 }
 948
 949 static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
 950                                         loff_t to_addr, const u8 *txbuf,
 951                                         const size_t n_tx)
 952 {
 953         struct cqspi_st *cqspi = f_pdata->cqspi;
 954         struct device *dev = &cqspi->pdev->dev;
 955         void __iomem *reg_base = cqspi->iobase;
 956         unsigned int remaining = n_tx;
 957         unsigned int write_bytes;
 958         int ret;
 959
 960         writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
 961         writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
 962
 963         /* Clear all interrupts. */
 964         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 965
 966         writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
 967
 968         reinit_completion(&cqspi->transfer_complete);
 969         writel(CQSPI_REG_INDIRECTWR_START_MASK,
 970                reg_base + CQSPI_REG_INDIRECTWR);
 971         /*
 972          * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
 973          * Controller programming sequence, couple of cycles of
 974          * QSPI_REF_CLK delay is required for the above bit to
 975          * be internally synchronized by the QSPI module. Provide 5
 976          * cycles of delay.
 977          */
 978         if (cqspi->wr_delay)
 979                 ndelay(cqspi->wr_delay);
 980
 981         while (remaining > 0) {
 982                 size_t write_words, mod_bytes;
 983
 984                 write_bytes = remaining;
 985                 write_words = write_bytes / 4;
 986                 mod_bytes = write_bytes % 4;
 987                 /* Write 4 bytes at a time then single bytes. */
 988                 if (write_words) {
 989                         iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
 990                         txbuf += (write_words * 4);
 991                 }
 992                 if (mod_bytes) {
 993                         unsigned int temp = 0xFFFFFFFF;
 994
 995                         memcpy(&temp, txbuf, mod_bytes);
 996                         iowrite32(temp, cqspi->ahb_base);
 997                         txbuf += mod_bytes;
 998                 }
 999
1000                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
1001                                                  msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
1002                         dev_err(dev, "Indirect write timeout\n");
1003                         ret = -ETIMEDOUT;
1004                         goto failwr;
1005                 }
1006
1007                 remaining -= write_bytes;
1008
1009                 if (remaining > 0)
1010                         reinit_completion(&cqspi->transfer_complete);
1011         }
1012
1013         /* Check indirect done status */
1014         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
1015                                  CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
1016         if (ret) {
1017                 dev_err(dev, "Indirect write completion error (%i)\n", ret);
1018                 goto failwr;
1019         }
1020
1021         /* Disable interrupt. */
1022         writel(0, reg_base + CQSPI_REG_IRQMASK);
1023
1024         /* Clear indirect completion status */
1025         writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
1026
1027         cqspi_wait_idle(cqspi);
1028
1029         return 0;
1030
1031 failwr:
1032         /* Disable interrupt. */
1033         writel(0, reg_base + CQSPI_REG_IRQMASK);
1034
1035         /* Cancel the indirect write */
1036         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
1037                reg_base + CQSPI_REG_INDIRECTWR);
1038         return ret;
1039 }
1040
1041 static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata)
1042 {
1043         struct cqspi_st *cqspi = f_pdata->cqspi;
1044         void __iomem *reg_base = cqspi->iobase;
1045         unsigned int chip_select = f_pdata->cs;
1046         unsigned int reg;
1047
1048         reg = readl(reg_base + CQSPI_REG_CONFIG);
1049         if (cqspi->is_decoded_cs) {
1050                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
1051         } else {
1052                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
1053
1054                 /* Convert CS if without decoder.
1055                  * CS0 to 4b'1110
1056                  * CS1 to 4b'1101
1057                  * CS2 to 4b'1011
1058                  * CS3 to 4b'0111
1059                  */
1060                 chip_select = 0xF & ~(1 << chip_select);
1061         }
1062
1063         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
1064                  << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
1065         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
1066             << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
1067         writel(reg, reg_base + CQSPI_REG_CONFIG);
1068 }
1069
1070 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
1071                                            const unsigned int ns_val)
1072 {
1073         unsigned int ticks;
1074
1075         ticks = ref_clk_hz / 1000;      /* kHz */
1076         ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
1077
1078         return ticks;
1079 }
1080
1081 static void cqspi_delay(struct cqspi_flash_pdata *f_pdata)
1082 {
1083         struct cqspi_st *cqspi = f_pdata->cqspi;
1084         void __iomem *iobase = cqspi->iobase;
1085         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
1086         unsigned int tshsl, tchsh, tslch, tsd2d;
1087         unsigned int reg;
1088         unsigned int tsclk;
1089
1090         /* calculate the number of ref ticks for one sclk tick */
1091         tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
1092
1093         tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
1094         /* this particular value must be at least one sclk */
1095         if (tshsl < tsclk)
1096                 tshsl = tsclk;
1097
1098         tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
1099         tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
1100         tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
1101
1102         reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
1103                << CQSPI_REG_DELAY_TSHSL_LSB;
1104         reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
1105                 << CQSPI_REG_DELAY_TCHSH_LSB;
1106         reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
1107                 << CQSPI_REG_DELAY_TSLCH_LSB;
1108         reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
1109                 << CQSPI_REG_DELAY_TSD2D_LSB;
1110         writel(reg, iobase + CQSPI_REG_DELAY);
1111 }
1112
1113 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
1114 {
1115         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
1116         void __iomem *reg_base = cqspi->iobase;
1117         u32 reg, div;
1118
1119         /* Recalculate the baudrate divisor based on QSPI specification. */
1120         div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
1121
1122         reg = readl(reg_base + CQSPI_REG_CONFIG);
1123         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
1124         reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
1125         writel(reg, reg_base + CQSPI_REG_CONFIG);
1126 }
1127
1128 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
1129                                    const bool bypass,
1130                                    const unsigned int delay)
1131 {
1132         void __iomem *reg_base = cqspi->iobase;
1133         unsigned int reg;
1134
1135         reg = readl(reg_base + CQSPI_REG_READCAPTURE);
1136
1137         if (bypass)
1138                 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
1139         else
1140                 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
1141
1142         reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
1143                  << CQSPI_REG_READCAPTURE_DELAY_LSB);
1144
1145         reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
1146                 << CQSPI_REG_READCAPTURE_DELAY_LSB;
1147
1148         writel(reg, reg_base + CQSPI_REG_READCAPTURE);
1149 }
1150
1151 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
1152 {
1153         void __iomem *reg_base = cqspi->iobase;
1154         unsigned int reg;
1155
1156         reg = readl(reg_base + CQSPI_REG_CONFIG);
1157
1158         if (enable)
1159                 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
1160         else
1161                 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
1162
1163         writel(reg, reg_base + CQSPI_REG_CONFIG);
1164 }
1165
1166 static void cqspi_configure(struct cqspi_flash_pdata *f_pdata,
1167                             unsigned long sclk)
1168 {
1169         struct cqspi_st *cqspi = f_pdata->cqspi;
1170         int switch_cs = (cqspi->current_cs != f_pdata->cs);
1171         int switch_ck = (cqspi->sclk != sclk);
1172
1173         if (switch_cs || switch_ck)
1174                 cqspi_controller_enable(cqspi, 0);
1175
1176         /* Switch chip select. */
1177         if (switch_cs) {
1178                 cqspi->current_cs = f_pdata->cs;
1179                 cqspi_chipselect(f_pdata);
1180         }
1181
1182         /* Setup baudrate divisor and delays */
1183         if (switch_ck) {
1184                 cqspi->sclk = sclk;
1185                 cqspi_config_baudrate_div(cqspi);
1186                 cqspi_delay(f_pdata);
1187                 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
1188                                        f_pdata->read_delay);
1189         }
1190
1191         if (switch_cs || switch_ck)
1192                 cqspi_controller_enable(cqspi, 1);
1193 }
1194
1195 static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
1196                            const struct spi_mem_op *op)
1197 {
1198         struct cqspi_st *cqspi = f_pdata->cqspi;
1199         loff_t to = op->addr.val;
1200         size_t len = op->data.nbytes;
1201         const u_char *buf = op->data.buf.out;
1202         int ret;
1203
1204         ret = cqspi_write_setup(f_pdata, op);
1205         if (ret)
1206                 return ret;
1207
1208         /*
1209          * Some flashes like the Cypress Semper flash expect a dummy 4-byte
1210          * address (all 0s) with the read status register command in DTR mode.
1211          * But this controller does not support sending dummy address bytes to
1212          * the flash when it is polling the write completion register in DTR
1213          * mode. So, we can not use direct mode when in DTR mode for writing
1214          * data.
1215          */
1216         if (!op->cmd.dtr && cqspi->use_direct_mode &&
1217             ((to + len) <= cqspi->ahb_size)) {
1218                 memcpy_toio(cqspi->ahb_base + to, buf, len);
1219                 return cqspi_wait_idle(cqspi);
1220         }
1221
1222         return cqspi_indirect_write_execute(f_pdata, to, buf, len);
1223 }
1224
1225 static void cqspi_rx_dma_callback(void *param)
1226 {
1227         struct cqspi_st *cqspi = param;
1228
1229         complete(&cqspi->rx_dma_complete);
1230 }
1231
1232 static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
1233                                      u_char *buf, loff_t from, size_t len)
1234 {
1235         struct cqspi_st *cqspi = f_pdata->cqspi;
1236         struct device *dev = &cqspi->pdev->dev;
1237         enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
1238         dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
1239         int ret = 0;
1240         struct dma_async_tx_descriptor *tx;
1241         dma_cookie_t cookie;
1242         dma_addr_t dma_dst;
1243         struct device *ddev;
1244
1245         if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
1246                 memcpy_fromio(buf, cqspi->ahb_base + from, len);
1247                 return 0;
1248         }
1249
1250         ddev = cqspi->rx_chan->device->dev;
1251         dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE);
1252         if (dma_mapping_error(ddev, dma_dst)) {
1253                 dev_err(dev, "dma mapping failed\n");
1254                 return -ENOMEM;
1255         }
1256         tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
1257                                        len, flags);
1258         if (!tx) {
1259                 dev_err(dev, "device_prep_dma_memcpy error\n");
1260                 ret = -EIO;
1261                 goto err_unmap;
1262         }
1263
1264         tx->callback = cqspi_rx_dma_callback;
1265         tx->callback_param = cqspi;
1266         cookie = tx->tx_submit(tx);
1267         reinit_completion(&cqspi->rx_dma_complete);
1268
1269         ret = dma_submit_error(cookie);
1270         if (ret) {
1271                 dev_err(dev, "dma_submit_error %d\n", cookie);
1272                 ret = -EIO;
1273                 goto err_unmap;
1274         }
1275
1276         dma_async_issue_pending(cqspi->rx_chan);
1277         if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
1278                                          msecs_to_jiffies(max_t(size_t, len, 500)))) {
1279                 dmaengine_terminate_sync(cqspi->rx_chan);
1280                 dev_err(dev, "DMA wait_for_completion_timeout\n");
1281                 ret = -ETIMEDOUT;
1282                 goto err_unmap;
1283         }
1284
1285 err_unmap:
1286         dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE);
1287
1288         return ret;
1289 }
1290
1291 static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
1292                           const struct spi_mem_op *op)
1293 {
1294         struct cqspi_st *cqspi = f_pdata->cqspi;
1295         struct device *dev = &cqspi->pdev->dev;
1296         const struct cqspi_driver_platdata *ddata;
1297         loff_t from = op->addr.val;
1298         size_t len = op->data.nbytes;
1299         u_char *buf = op->data.buf.in;
1300         u64 dma_align = (u64)(uintptr_t)buf;
1301         int ret;
1302
1303         ddata = of_device_get_match_data(dev);
1304
1305         ret = cqspi_read_setup(f_pdata, op);
1306         if (ret)
1307                 return ret;
1308
1309         if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
1310                 return cqspi_direct_read_execute(f_pdata, buf, from, len);
1311
1312         if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma &&
1313             virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0))
1314                 return ddata->indirect_read_dma(f_pdata, buf, from, len);
1315
1316         return cqspi_indirect_read_execute(f_pdata, buf, from, len);
1317 }
1318
1319 static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
1320 {
1321         struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
1322         struct cqspi_flash_pdata *f_pdata;
1323
1324         f_pdata = &cqspi->f_pdata[mem->spi->chip_select];
1325         cqspi_configure(f_pdata, mem->spi->max_speed_hz);
1326
1327         if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
1328                 if (!op->addr.nbytes)
1329                         return cqspi_command_read(f_pdata, op);
1330
1331                 return cqspi_read(f_pdata, op);
1332         }
1333
1334         if (!op->addr.nbytes || !op->data.buf.out)
1335                 return cqspi_command_write(f_pdata, op);
1336
1337         return cqspi_write(f_pdata, op);
1338 }
1339
1340 static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
1341 {
1342         int ret;
1343
1344         ret = cqspi_mem_process(mem, op);
1345         if (ret)
1346                 dev_err(&mem->spi->dev, "operation failed with %d\n", ret);
1347
1348         return ret;
1349 }
1350
1351 static bool cqspi_supports_mem_op(struct spi_mem *mem,
1352                                   const struct spi_mem_op *op)
1353 {
1354         bool all_true, all_false;
1355
1356         /*
1357          * op->dummy.dtr is required for converting nbytes into ncycles.
1358          * Also, don't check the dtr field of the op phase having zero nbytes.
1359          */
1360         all_true = op->cmd.dtr &&
1361                    (!op->addr.nbytes || op->addr.dtr) &&
1362                    (!op->dummy.nbytes || op->dummy.dtr) &&
1363                    (!op->data.nbytes || op->data.dtr);
1364
1365         all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
1366                     !op->data.dtr;
1367
1368         if (all_true) {
1369                 /* Right now we only support 8-8-8 DTR mode. */
1370                 if (op->cmd.nbytes && op->cmd.buswidth != 8)
1371                         return false;
1372                 if (op->addr.nbytes && op->addr.buswidth != 8)
1373                         return false;
1374                 if (op->data.nbytes && op->data.buswidth != 8)
1375                         return false;
1376         } else if (!all_false) {
1377                 /* Mixed DTR modes are not supported. */
1378                 return false;
1379         }
1380
1381         return spi_mem_default_supports_op(mem, op);
1382 }
1383
1384 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1385                                     struct cqspi_flash_pdata *f_pdata,
1386                                     struct device_node *np)
1387 {
1388         if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1389                 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1390                 return -ENXIO;
1391         }
1392
1393         if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1394                 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1395                 return -ENXIO;
1396         }
1397
1398         if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1399                 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1400                 return -ENXIO;
1401         }
1402
1403         if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1404                 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1405                 return -ENXIO;
1406         }
1407
1408         if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1409                 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1410                 return -ENXIO;
1411         }
1412
1413         if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1414                 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1415                 return -ENXIO;
1416         }
1417
1418         return 0;
1419 }
1420
1421 static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
1422 {
1423         struct device *dev = &cqspi->pdev->dev;
1424         struct device_node *np = dev->of_node;
1425         u32 id[2];
1426
1427         cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1428
1429         if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1430                 dev_err(dev, "couldn't determine fifo-depth\n");
1431                 return -ENXIO;
1432         }
1433
1434         if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1435                 dev_err(dev, "couldn't determine fifo-width\n");
1436                 return -ENXIO;
1437         }
1438
1439         if (of_property_read_u32(np, "cdns,trigger-address",
1440                                  &cqspi->trigger_address)) {
1441                 dev_err(dev, "couldn't determine trigger-address\n");
1442                 return -ENXIO;
1443         }
1444
1445         if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
1446                 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;
1447
1448         cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1449
1450         if (!of_property_read_u32_array(np, "power-domains", id,
1451                                         ARRAY_SIZE(id)))
1452                 cqspi->pd_dev_id = id[1];
1453
1454         return 0;
1455 }
1456
1457 static void cqspi_controller_init(struct cqspi_st *cqspi)
1458 {
1459         u32 reg;
1460
1461         cqspi_controller_enable(cqspi, 0);
1462
1463         /* Configure the remap address register, no remap */
1464         writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1465
1466         /* Disable all interrupts. */
1467         writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1468
1469         /* Configure the SRAM split to 1:1 . */
1470         writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1471
1472         /* Load indirect trigger address. */
1473         writel(cqspi->trigger_address,
1474                cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1475
1476         /* Program read watermark -- 1/2 of the FIFO. */
1477         writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1478                cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1479         /* Program write watermark -- 1/8 of the FIFO. */
1480         writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1481                cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1482
1483         /* Disable direct access controller */
1484         if (!cqspi->use_direct_mode) {
1485                 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1486                 reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1487                 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1488         }
1489
1490         /* Enable DMA interface */
1491         if (cqspi->use_dma_read) {
1492                 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1493                 reg |= CQSPI_REG_CONFIG_DMA_MASK;
1494                 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1495         }
1496
1497         cqspi_controller_enable(cqspi, 1);
1498 }
1499
1500 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1501 {
1502         dma_cap_mask_t mask;
1503
1504         dma_cap_zero(mask);
1505         dma_cap_set(DMA_MEMCPY, mask);
1506
1507         cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1508         if (IS_ERR(cqspi->rx_chan)) {
1509                 int ret = PTR_ERR(cqspi->rx_chan);
1510
1511                 cqspi->rx_chan = NULL;
1512                 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");
1513         }
1514         init_completion(&cqspi->rx_dma_complete);
1515
1516         return 0;
1517 }
1518
1519 static const char *cqspi_get_name(struct spi_mem *mem)
1520 {
1521         struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
1522         struct device *dev = &cqspi->pdev->dev;
1523
1524         return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
1525 }
1526
1527 static const struct spi_controller_mem_ops cqspi_mem_ops = {
1528         .exec_op = cqspi_exec_mem_op,
1529         .get_name = cqspi_get_name,
1530         .supports_op = cqspi_supports_mem_op,
1531 };
1532
1533 static const struct spi_controller_mem_caps cqspi_mem_caps = {
1534         .dtr = true,
1535 };
1536
1537 static int cqspi_setup_flash(struct cqspi_st *cqspi)
1538 {
1539         struct platform_device *pdev = cqspi->pdev;
1540         struct device *dev = &pdev->dev;
1541         struct device_node *np = dev->of_node;
1542         struct cqspi_flash_pdata *f_pdata;
1543         unsigned int cs;
1544         int ret;
1545
1546         /* Get flash device data */
1547         for_each_available_child_of_node(dev->of_node, np) {
1548                 ret = of_property_read_u32(np, "reg", &cs);
1549                 if (ret) {
1550                         dev_err(dev, "Couldn't determine chip select.\n");
1551                         of_node_put(np);
1552                         return ret;
1553                 }
1554
1555                 if (cs >= CQSPI_MAX_CHIPSELECT) {
1556                         dev_err(dev, "Chip select %d out of range.\n", cs);
1557                         of_node_put(np);
1558                         return -EINVAL;
1559                 }
1560
1561                 f_pdata = &cqspi->f_pdata[cs];
1562                 f_pdata->cqspi = cqspi;
1563                 f_pdata->cs = cs;
1564
1565                 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1566                 if (ret) {
1567                         of_node_put(np);
1568                         return ret;
1569                 }
1570         }
1571
1572         return 0;
1573 }
1574
1575 static int cqspi_probe(struct platform_device *pdev)
1576 {
1577         const struct cqspi_driver_platdata *ddata;
1578         struct reset_control *rstc, *rstc_ocp;
1579         struct device *dev = &pdev->dev;
1580         struct spi_master *master;
1581         struct resource *res_ahb;
1582         struct cqspi_st *cqspi;
1583         struct resource *res;
1584         int ret;
1585         int irq;
1586
1587         master = devm_spi_alloc_master(&pdev->dev, sizeof(*cqspi));
1588         if (!master) {
1589                 dev_err(&pdev->dev, "spi_alloc_master failed\n");
1590                 return -ENOMEM;
1591         }
1592         master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
1593         master->mem_ops = &cqspi_mem_ops;
1594         master->mem_caps = &cqspi_mem_caps;
1595         master->dev.of_node = pdev->dev.of_node;
1596
1597         cqspi = spi_master_get_devdata(master);
1598
1599         cqspi->pdev = pdev;
1600         cqspi->master = master;
1601         platform_set_drvdata(pdev, cqspi);
1602
1603         /* Obtain configuration from OF. */
1604         ret = cqspi_of_get_pdata(cqspi);
1605         if (ret) {
1606                 dev_err(dev, "Cannot get mandatory OF data.\n");
1607                 return -ENODEV;
1608         }
1609
1610         /* Obtain QSPI clock. */
1611         cqspi->clk = devm_clk_get(dev, NULL);
1612         if (IS_ERR(cqspi->clk)) {
1613                 dev_err(dev, "Cannot claim QSPI clock.\n");
1614                 ret = PTR_ERR(cqspi->clk);
1615                 return ret;
1616         }
1617
1618         /* Obtain and remap controller address. */
1619         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1620         cqspi->iobase = devm_ioremap_resource(dev, res);
1621         if (IS_ERR(cqspi->iobase)) {
1622                 dev_err(dev, "Cannot remap controller address.\n");
1623                 ret = PTR_ERR(cqspi->iobase);
1624                 return ret;
1625         }
1626
1627         /* Obtain and remap AHB address. */
1628         res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1629         cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1630         if (IS_ERR(cqspi->ahb_base)) {
1631                 dev_err(dev, "Cannot remap AHB address.\n");
1632                 ret = PTR_ERR(cqspi->ahb_base);
1633                 return ret;
1634         }
1635         cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1636         cqspi->ahb_size = resource_size(res_ahb);
1637
1638         init_completion(&cqspi->transfer_complete);
1639
1640         /* Obtain IRQ line. */
1641         irq = platform_get_irq(pdev, 0);
1642         if (irq < 0)
1643                 return -ENXIO;
1644
1645         pm_runtime_enable(dev);
1646         ret = pm_runtime_resume_and_get(dev);
1647         if (ret < 0)
1648                 goto probe_pm_failed;
1649
1650         ret = clk_prepare_enable(cqspi->clk);
1651         if (ret) {
1652                 dev_err(dev, "Cannot enable QSPI clock.\n");
1653                 goto probe_clk_failed;
1654         }
1655
1656         /* Obtain QSPI reset control */
1657         rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
1658         if (IS_ERR(rstc)) {
1659                 ret = PTR_ERR(rstc);
1660                 dev_err(dev, "Cannot get QSPI reset.\n");
1661                 goto probe_reset_failed;
1662         }
1663
1664         rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
1665         if (IS_ERR(rstc_ocp)) {
1666                 ret = PTR_ERR(rstc_ocp);
1667                 dev_err(dev, "Cannot get QSPI OCP reset.\n");
1668                 goto probe_reset_failed;
1669         }
1670
1671         reset_control_assert(rstc);
1672         reset_control_deassert(rstc);
1673
1674         reset_control_assert(rstc_ocp);
1675         reset_control_deassert(rstc_ocp);
1676
1677         cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1678         master->max_speed_hz = cqspi->master_ref_clk_hz;
1679
1680         /* write completion is supported by default */
1681         cqspi->wr_completion = true;
1682
1683         ddata  = of_device_get_match_data(dev);
1684         if (ddata) {
1685                 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
1686                         cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
1687                                                 cqspi->master_ref_clk_hz);
1688                 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
1689                         master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
1690                 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE))
1691                         cqspi->use_direct_mode = true;
1692                 if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA)
1693                         cqspi->use_dma_read = true;
1694                 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION)
1695                         cqspi->wr_completion = false;
1696                 if (ddata->quirks & CQSPI_SLOW_SRAM)
1697                         cqspi->slow_sram = true;
1698
1699                 if (of_device_is_compatible(pdev->dev.of_node,
1700                                             "xlnx,versal-ospi-1.0"))
1701                         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1702         }
1703
1704         ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1705                                pdev->name, cqspi);
1706         if (ret) {
1707                 dev_err(dev, "Cannot request IRQ.\n");
1708                 goto probe_reset_failed;
1709         }
1710
1711         cqspi_wait_idle(cqspi);
1712         cqspi_controller_init(cqspi);
1713         cqspi->current_cs = -1;
1714         cqspi->sclk = 0;
1715
1716         master->num_chipselect = cqspi->num_chipselect;
1717
1718         ret = cqspi_setup_flash(cqspi);
1719         if (ret) {
1720                 dev_err(dev, "failed to setup flash parameters %d\n", ret);
1721                 goto probe_setup_failed;
1722         }
1723
1724         if (cqspi->use_direct_mode) {
1725                 ret = cqspi_request_mmap_dma(cqspi);
1726                 if (ret == -EPROBE_DEFER)
1727                         goto probe_setup_failed;
1728         }
1729
1730         ret = spi_register_master(master);
1731         if (ret) {
1732                 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
1733                 goto probe_setup_failed;
1734         }
1735
1736         return 0;
1737 probe_setup_failed:
1738         cqspi_controller_enable(cqspi, 0);
1739 probe_reset_failed:
1740         clk_disable_unprepare(cqspi->clk);
1741 probe_clk_failed:
1742         pm_runtime_put_sync(dev);
1743 probe_pm_failed:
1744         pm_runtime_disable(dev);
1745         return ret;
1746 }
1747
1748 static int cqspi_remove(struct platform_device *pdev)
1749 {
1750         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1751
1752         spi_unregister_master(cqspi->master);
1753         cqspi_controller_enable(cqspi, 0);
1754
1755         if (cqspi->rx_chan)
1756                 dma_release_channel(cqspi->rx_chan);
1757
1758         clk_disable_unprepare(cqspi->clk);
1759
1760         pm_runtime_put_sync(&pdev->dev);
1761         pm_runtime_disable(&pdev->dev);
1762
1763         return 0;
1764 }
1765
1766 #ifdef CONFIG_PM_SLEEP
1767 static int cqspi_suspend(struct device *dev)
1768 {
1769         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1770
1771         cqspi_controller_enable(cqspi, 0);
1772         return 0;
1773 }
1774
1775 static int cqspi_resume(struct device *dev)
1776 {
1777         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1778
1779         cqspi_controller_enable(cqspi, 1);
1780         return 0;
1781 }
1782
1783 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1784         .suspend = cqspi_suspend,
1785         .resume = cqspi_resume,
1786 };
1787
1788 #define CQSPI_DEV_PM_OPS        (&cqspi__dev_pm_ops)
1789 #else
1790 #define CQSPI_DEV_PM_OPS        NULL
1791 #endif
1792
1793 static const struct cqspi_driver_platdata cdns_qspi = {
1794         .quirks = CQSPI_DISABLE_DAC_MODE,
1795 };
1796
1797 static const struct cqspi_driver_platdata k2g_qspi = {
1798         .quirks = CQSPI_NEEDS_WR_DELAY,
1799 };
1800
1801 static const struct cqspi_driver_platdata am654_ospi = {
1802         .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
1803         .quirks = CQSPI_NEEDS_WR_DELAY,
1804 };
1805
1806 static const struct cqspi_driver_platdata intel_lgm_qspi = {
1807         .quirks = CQSPI_DISABLE_DAC_MODE,
1808 };
1809
1810 static const struct cqspi_driver_platdata socfpga_qspi = {
1811         .quirks = CQSPI_DISABLE_DAC_MODE
1812                         | CQSPI_NO_SUPPORT_WR_COMPLETION
1813                         | CQSPI_SLOW_SRAM,
1814 };
1815
1816 static const struct cqspi_driver_platdata versal_ospi = {
1817         .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
1818         .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA,
1819         .indirect_read_dma = cqspi_versal_indirect_read_dma,
1820         .get_dma_status = cqspi_get_versal_dma_status,
1821 };
1822
1823 static const struct of_device_id cqspi_dt_ids[] = {
1824         {
1825                 .compatible = "cdns,qspi-nor",
1826                 .data = &cdns_qspi,
1827         },
1828         {
1829                 .compatible = "ti,k2g-qspi",
1830                 .data = &k2g_qspi,
1831         },
1832         {
1833                 .compatible = "ti,am654-ospi",
1834                 .data = &am654_ospi,
1835         },
1836         {
1837                 .compatible = "intel,lgm-qspi",
1838                 .data = &intel_lgm_qspi,
1839         },
1840         {
1841                 .compatible = "xlnx,versal-ospi-1.0",
1842                 .data = &versal_ospi,
1843         },
1844         {
1845                 .compatible = "intel,socfpga-qspi",
1846                 .data = &socfpga_qspi,
1847         },
1848         { /* end of table */ }
1849 };
1850
1851 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1852
1853 static struct platform_driver cqspi_platform_driver = {
1854         .probe = cqspi_probe,
1855         .remove = cqspi_remove,
1856         .driver = {
1857                 .name = CQSPI_NAME,
1858                 .pm = CQSPI_DEV_PM_OPS,
1859                 .of_match_table = cqspi_dt_ids,
1860         },
1861 };
1862
1863 module_platform_driver(cqspi_platform_driver);
1864
1865 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1866 MODULE_LICENSE("GPL v2");
1867 MODULE_ALIAS("platform:" CQSPI_NAME);
1868 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1869 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
1870 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
1871 MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>");
1872 MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>");