1 // SPDX-License-Identifier: GPL-2.0-only
3 // Driver for Cadence QSPI Controller
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
10 #include <linux/completion.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmaengine.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
16 #include <linux/interrupt.h>
18 #include <linux/iopoll.h>
19 #include <linux/jiffies.h>
20 #include <linux/kernel.h>
21 #include <linux/log2.h>
22 #include <linux/module.h>
23 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/reset.h>
28 #include <linux/sched.h>
29 #include <linux/spi/spi.h>
30 #include <linux/spi/spi-mem.h>
31 #include <linux/timer.h>
33 #define CQSPI_NAME "cadence-qspi"
34 #define CQSPI_MAX_CHIPSELECT 16
37 #define CQSPI_NEEDS_WR_DELAY BIT(0)
38 #define CQSPI_DISABLE_DAC_MODE BIT(1)
39 #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3)
42 #define CQSPI_SUPPORTS_OCTAL BIT(0)
46 struct cqspi_flash_pdata {
47 struct cqspi_st *cqspi;
62 struct platform_device *pdev;
68 void __iomem *ahb_base;
69 resource_size_t ahb_size;
70 struct completion transfer_complete;
72 struct dma_chan *rx_chan;
73 struct completion rx_dma_complete;
74 dma_addr_t mmap_phys_base;
77 unsigned long master_ref_clk_hz;
86 struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
90 struct cqspi_driver_platdata {
95 /* Operation timeout value */
96 #define CQSPI_TIMEOUT_MS 500
97 #define CQSPI_READ_TIMEOUT_MS 10
99 #define CQSPI_DUMMY_CLKS_PER_BYTE 8
100 #define CQSPI_DUMMY_BYTES_MAX 4
101 #define CQSPI_DUMMY_CLKS_MAX 31
103 #define CQSPI_STIG_DATA_LEN_MAX 8
106 #define CQSPI_REG_CONFIG 0x00
107 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
108 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7)
109 #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
110 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
111 #define CQSPI_REG_CONFIG_DMA_MASK BIT(15)
112 #define CQSPI_REG_CONFIG_BAUD_LSB 19
113 #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24)
114 #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30)
115 #define CQSPI_REG_CONFIG_IDLE_LSB 31
116 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
117 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
119 #define CQSPI_REG_RD_INSTR 0x04
120 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
121 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
122 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
123 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
124 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
125 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
126 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
127 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
128 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
129 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
131 #define CQSPI_REG_WR_INSTR 0x08
132 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
133 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
134 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
136 #define CQSPI_REG_DELAY 0x0C
137 #define CQSPI_REG_DELAY_TSLCH_LSB 0
138 #define CQSPI_REG_DELAY_TCHSH_LSB 8
139 #define CQSPI_REG_DELAY_TSD2D_LSB 16
140 #define CQSPI_REG_DELAY_TSHSL_LSB 24
141 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
142 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
143 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
144 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
146 #define CQSPI_REG_READCAPTURE 0x10
147 #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0
148 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1
149 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF
151 #define CQSPI_REG_SIZE 0x14
152 #define CQSPI_REG_SIZE_ADDRESS_LSB 0
153 #define CQSPI_REG_SIZE_PAGE_LSB 4
154 #define CQSPI_REG_SIZE_BLOCK_LSB 16
155 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
156 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
157 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
159 #define CQSPI_REG_SRAMPARTITION 0x18
160 #define CQSPI_REG_INDIRECTTRIGGER 0x1C
162 #define CQSPI_REG_DMA 0x20
163 #define CQSPI_REG_DMA_SINGLE_LSB 0
164 #define CQSPI_REG_DMA_BURST_LSB 8
165 #define CQSPI_REG_DMA_SINGLE_MASK 0xFF
166 #define CQSPI_REG_DMA_BURST_MASK 0xFF
168 #define CQSPI_REG_REMAP 0x24
169 #define CQSPI_REG_MODE_BIT 0x28
171 #define CQSPI_REG_SDRAMLEVEL 0x2C
172 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
173 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
174 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
175 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
177 #define CQSPI_REG_WR_COMPLETION_CTRL 0x38
178 #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14)
180 #define CQSPI_REG_IRQSTATUS 0x40
181 #define CQSPI_REG_IRQMASK 0x44
183 #define CQSPI_REG_INDIRECTRD 0x60
184 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
185 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1)
186 #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5)
188 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
189 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
190 #define CQSPI_REG_INDIRECTRDBYTES 0x6C
192 #define CQSPI_REG_CMDCTRL 0x90
193 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
194 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
195 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
196 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
197 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
198 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
199 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
200 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
201 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
202 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
203 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
204 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
205 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
206 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
208 #define CQSPI_REG_INDIRECTWR 0x70
209 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
210 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1)
211 #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5)
213 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
214 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
215 #define CQSPI_REG_INDIRECTWRBYTES 0x7C
217 #define CQSPI_REG_CMDADDRESS 0x94
218 #define CQSPI_REG_CMDREADDATALOWER 0xA0
219 #define CQSPI_REG_CMDREADDATAUPPER 0xA4
220 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
221 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
223 #define CQSPI_REG_POLLING_STATUS 0xB0
224 #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16
226 #define CQSPI_REG_OP_EXT_LOWER 0xE0
227 #define CQSPI_REG_OP_EXT_READ_LSB 24
228 #define CQSPI_REG_OP_EXT_WRITE_LSB 16
229 #define CQSPI_REG_OP_EXT_STIG_LSB 0
231 /* Interrupt status bits */
232 #define CQSPI_REG_IRQ_MODE_ERR BIT(0)
233 #define CQSPI_REG_IRQ_UNDERFLOW BIT(1)
234 #define CQSPI_REG_IRQ_IND_COMP BIT(2)
235 #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3)
236 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4)
237 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5)
238 #define CQSPI_REG_IRQ_WATERMARK BIT(6)
239 #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12)
241 #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \
242 CQSPI_REG_IRQ_IND_SRAM_FULL | \
243 CQSPI_REG_IRQ_IND_COMP)
245 #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \
246 CQSPI_REG_IRQ_WATERMARK | \
247 CQSPI_REG_IRQ_UNDERFLOW)
249 #define CQSPI_IRQ_STATUS_MASK 0x1FFFF
251 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
255 return readl_relaxed_poll_timeout(reg, val,
256 (((clr ? ~val : val) & mask) == mask),
257 10, CQSPI_TIMEOUT_MS * 1000);
260 static bool cqspi_is_idle(struct cqspi_st *cqspi)
262 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
264 return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB);
267 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
269 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
271 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
272 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
275 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
277 struct cqspi_st *cqspi = dev;
278 unsigned int irq_status;
280 /* Read interrupt status */
281 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
283 /* Clear interrupt */
284 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
286 irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
289 complete(&cqspi->transfer_complete);
294 static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata)
298 rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
299 rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
300 rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
305 static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr)
307 unsigned int dummy_clk;
309 if (!op->dummy.nbytes)
312 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
319 static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata,
320 const struct spi_mem_op *op)
323 * For an op to be DTR, cmd phase along with every other non-empty
324 * phase should have dtr field set to 1. If an op phase has zero
325 * nbytes, ignore its dtr field; otherwise, check its dtr field.
327 f_pdata->dtr = op->cmd.dtr &&
328 (!op->addr.nbytes || op->addr.dtr) &&
329 (!op->data.nbytes || op->data.dtr);
331 f_pdata->inst_width = 0;
332 if (op->cmd.buswidth)
333 f_pdata->inst_width = ilog2(op->cmd.buswidth);
335 f_pdata->addr_width = 0;
336 if (op->addr.buswidth)
337 f_pdata->addr_width = ilog2(op->addr.buswidth);
339 f_pdata->data_width = 0;
340 if (op->data.buswidth)
341 f_pdata->data_width = ilog2(op->data.buswidth);
343 /* Right now we only support 8-8-8 DTR mode. */
345 switch (op->cmd.buswidth) {
353 switch (op->addr.buswidth) {
361 switch (op->data.buswidth) {
373 static int cqspi_wait_idle(struct cqspi_st *cqspi)
375 const unsigned int poll_idle_retry = 3;
376 unsigned int count = 0;
377 unsigned long timeout;
379 timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
382 * Read few times in succession to ensure the controller
383 * is indeed idle, that is, the bit does not transition
386 if (cqspi_is_idle(cqspi))
391 if (count >= poll_idle_retry)
394 if (time_after(jiffies, timeout)) {
395 /* Timeout, in busy mode. */
396 dev_err(&cqspi->pdev->dev,
397 "QSPI is still busy after %dms timeout.\n",
406 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
408 void __iomem *reg_base = cqspi->iobase;
411 /* Write the CMDCTRL without start execution. */
412 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
414 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
415 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
417 /* Polling for completion. */
418 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
419 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
421 dev_err(&cqspi->pdev->dev,
422 "Flash command execution timed out.\n");
426 /* Polling QSPI idle status. */
427 return cqspi_wait_idle(cqspi);
430 static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata,
431 const struct spi_mem_op *op,
434 struct cqspi_st *cqspi = f_pdata->cqspi;
435 void __iomem *reg_base = cqspi->iobase;
439 if (op->cmd.nbytes != 2)
442 /* Opcode extension is the LSB. */
443 ext = op->cmd.opcode & 0xff;
445 reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER);
446 reg &= ~(0xff << shift);
448 writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER);
453 static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata,
454 const struct spi_mem_op *op, unsigned int shift,
457 struct cqspi_st *cqspi = f_pdata->cqspi;
458 void __iomem *reg_base = cqspi->iobase;
462 reg = readl(reg_base + CQSPI_REG_CONFIG);
465 * We enable dual byte opcode here. The callers have to set up the
466 * extension opcode based on which type of operation it is.
469 reg |= CQSPI_REG_CONFIG_DTR_PROTO;
470 reg |= CQSPI_REG_CONFIG_DUAL_OPCODE;
472 /* Set up command opcode extension. */
473 ret = cqspi_setup_opcode_ext(f_pdata, op, shift);
477 reg &= ~CQSPI_REG_CONFIG_DTR_PROTO;
478 reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE;
481 writel(reg, reg_base + CQSPI_REG_CONFIG);
483 return cqspi_wait_idle(cqspi);
486 static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
487 const struct spi_mem_op *op)
489 struct cqspi_st *cqspi = f_pdata->cqspi;
490 void __iomem *reg_base = cqspi->iobase;
491 u8 *rxbuf = op->data.buf.in;
493 size_t n_rx = op->data.nbytes;
496 unsigned int dummy_clk;
500 status = cqspi_set_protocol(f_pdata, op);
504 status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB,
509 if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
510 dev_err(&cqspi->pdev->dev,
511 "Invalid input argument, len %zu rxbuf 0x%p\n",
517 opcode = op->cmd.opcode >> 8;
519 opcode = op->cmd.opcode;
521 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
523 rdreg = cqspi_calc_rdreg(f_pdata);
524 writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
526 dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr);
527 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
531 reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)
532 << CQSPI_REG_CMDCTRL_DUMMY_LSB;
534 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
536 /* 0 means 1 byte. */
537 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
538 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
539 status = cqspi_exec_flash_cmd(cqspi, reg);
543 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
545 /* Put the read value into rx_buf */
546 read_len = (n_rx > 4) ? 4 : n_rx;
547 memcpy(rxbuf, ®, read_len);
551 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
553 read_len = n_rx - read_len;
554 memcpy(rxbuf, ®, read_len);
560 static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata,
561 const struct spi_mem_op *op)
563 struct cqspi_st *cqspi = f_pdata->cqspi;
564 void __iomem *reg_base = cqspi->iobase;
566 const u8 *txbuf = op->data.buf.out;
567 size_t n_tx = op->data.nbytes;
573 ret = cqspi_set_protocol(f_pdata, op);
577 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB,
582 if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
583 dev_err(&cqspi->pdev->dev,
584 "Invalid input argument, cmdlen %zu txbuf 0x%p\n",
589 reg = cqspi_calc_rdreg(f_pdata);
590 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
593 opcode = op->cmd.opcode >> 8;
595 opcode = op->cmd.opcode;
597 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
599 if (op->addr.nbytes) {
600 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
601 reg |= ((op->addr.nbytes - 1) &
602 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
603 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
605 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
609 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
610 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
611 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
613 write_len = (n_tx > 4) ? 4 : n_tx;
614 memcpy(&data, txbuf, write_len);
616 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
620 write_len = n_tx - 4;
621 memcpy(&data, txbuf, write_len);
622 writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
626 return cqspi_exec_flash_cmd(cqspi, reg);
629 static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
630 const struct spi_mem_op *op)
632 struct cqspi_st *cqspi = f_pdata->cqspi;
633 void __iomem *reg_base = cqspi->iobase;
634 unsigned int dummy_clk = 0;
639 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB,
645 opcode = op->cmd.opcode >> 8;
647 opcode = op->cmd.opcode;
649 reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
650 reg |= cqspi_calc_rdreg(f_pdata);
652 /* Setup dummy clock cycles */
653 dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr);
655 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
659 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
660 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
662 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
664 /* Set address width */
665 reg = readl(reg_base + CQSPI_REG_SIZE);
666 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
667 reg |= (op->addr.nbytes - 1);
668 writel(reg, reg_base + CQSPI_REG_SIZE);
672 static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
673 u8 *rxbuf, loff_t from_addr,
676 struct cqspi_st *cqspi = f_pdata->cqspi;
677 struct device *dev = &cqspi->pdev->dev;
678 void __iomem *reg_base = cqspi->iobase;
679 void __iomem *ahb_base = cqspi->ahb_base;
680 unsigned int remaining = n_rx;
681 unsigned int mod_bytes = n_rx % 4;
682 unsigned int bytes_to_read = 0;
683 u8 *rxbuf_end = rxbuf + n_rx;
686 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
687 writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
689 /* Clear all interrupts. */
690 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
692 writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
694 reinit_completion(&cqspi->transfer_complete);
695 writel(CQSPI_REG_INDIRECTRD_START_MASK,
696 reg_base + CQSPI_REG_INDIRECTRD);
698 while (remaining > 0) {
699 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
700 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
703 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
705 if (ret && bytes_to_read == 0) {
706 dev_err(dev, "Indirect read timeout, no bytes\n");
710 while (bytes_to_read != 0) {
711 unsigned int word_remain = round_down(remaining, 4);
713 bytes_to_read *= cqspi->fifo_width;
714 bytes_to_read = bytes_to_read > remaining ?
715 remaining : bytes_to_read;
716 bytes_to_read = round_down(bytes_to_read, 4);
717 /* Read 4 byte word chunks then single bytes */
719 ioread32_rep(ahb_base, rxbuf,
720 (bytes_to_read / 4));
721 } else if (!word_remain && mod_bytes) {
722 unsigned int temp = ioread32(ahb_base);
724 bytes_to_read = mod_bytes;
725 memcpy(rxbuf, &temp, min((unsigned int)
729 rxbuf += bytes_to_read;
730 remaining -= bytes_to_read;
731 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
735 reinit_completion(&cqspi->transfer_complete);
738 /* Check indirect done status */
739 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
740 CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
742 dev_err(dev, "Indirect read completion error (%i)\n", ret);
746 /* Disable interrupt */
747 writel(0, reg_base + CQSPI_REG_IRQMASK);
749 /* Clear indirect completion status */
750 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
755 /* Disable interrupt */
756 writel(0, reg_base + CQSPI_REG_IRQMASK);
758 /* Cancel the indirect read */
759 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
760 reg_base + CQSPI_REG_INDIRECTRD);
764 static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
765 const struct spi_mem_op *op)
769 struct cqspi_st *cqspi = f_pdata->cqspi;
770 void __iomem *reg_base = cqspi->iobase;
773 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB,
779 opcode = op->cmd.opcode >> 8;
781 opcode = op->cmd.opcode;
784 reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
785 reg |= f_pdata->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
786 reg |= f_pdata->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
787 writel(reg, reg_base + CQSPI_REG_WR_INSTR);
788 reg = cqspi_calc_rdreg(f_pdata);
789 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
792 * SPI NAND flashes require the address of the status register to be
793 * passed in the Read SR command. Also, some SPI NOR flashes like the
794 * cypress Semper flash expect a 4-byte dummy address in the Read SR
795 * command in DTR mode.
797 * But this controller does not support address phase in the Read SR
798 * command when doing auto-HW polling. So, disable write completion
799 * polling on the controller's side. spinand and spi-nor will take
800 * care of polling the status register.
802 if (cqspi->wr_completion) {
803 reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
804 reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
805 writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
808 reg = readl(reg_base + CQSPI_REG_SIZE);
809 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
810 reg |= (op->addr.nbytes - 1);
811 writel(reg, reg_base + CQSPI_REG_SIZE);
815 static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
816 loff_t to_addr, const u8 *txbuf,
819 struct cqspi_st *cqspi = f_pdata->cqspi;
820 struct device *dev = &cqspi->pdev->dev;
821 void __iomem *reg_base = cqspi->iobase;
822 unsigned int remaining = n_tx;
823 unsigned int write_bytes;
826 writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
827 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
829 /* Clear all interrupts. */
830 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
832 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
834 reinit_completion(&cqspi->transfer_complete);
835 writel(CQSPI_REG_INDIRECTWR_START_MASK,
836 reg_base + CQSPI_REG_INDIRECTWR);
838 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
839 * Controller programming sequence, couple of cycles of
840 * QSPI_REF_CLK delay is required for the above bit to
841 * be internally synchronized by the QSPI module. Provide 5
845 ndelay(cqspi->wr_delay);
847 while (remaining > 0) {
848 size_t write_words, mod_bytes;
850 write_bytes = remaining;
851 write_words = write_bytes / 4;
852 mod_bytes = write_bytes % 4;
853 /* Write 4 bytes at a time then single bytes. */
855 iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
856 txbuf += (write_words * 4);
859 unsigned int temp = 0xFFFFFFFF;
861 memcpy(&temp, txbuf, mod_bytes);
862 iowrite32(temp, cqspi->ahb_base);
866 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
867 msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
868 dev_err(dev, "Indirect write timeout\n");
873 remaining -= write_bytes;
876 reinit_completion(&cqspi->transfer_complete);
879 /* Check indirect done status */
880 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
881 CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
883 dev_err(dev, "Indirect write completion error (%i)\n", ret);
887 /* Disable interrupt. */
888 writel(0, reg_base + CQSPI_REG_IRQMASK);
890 /* Clear indirect completion status */
891 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
893 cqspi_wait_idle(cqspi);
898 /* Disable interrupt. */
899 writel(0, reg_base + CQSPI_REG_IRQMASK);
901 /* Cancel the indirect write */
902 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
903 reg_base + CQSPI_REG_INDIRECTWR);
907 static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata)
909 struct cqspi_st *cqspi = f_pdata->cqspi;
910 void __iomem *reg_base = cqspi->iobase;
911 unsigned int chip_select = f_pdata->cs;
914 reg = readl(reg_base + CQSPI_REG_CONFIG);
915 if (cqspi->is_decoded_cs) {
916 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
918 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
920 /* Convert CS if without decoder.
926 chip_select = 0xF & ~(1 << chip_select);
929 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
930 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
931 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
932 << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
933 writel(reg, reg_base + CQSPI_REG_CONFIG);
936 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
937 const unsigned int ns_val)
941 ticks = ref_clk_hz / 1000; /* kHz */
942 ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
947 static void cqspi_delay(struct cqspi_flash_pdata *f_pdata)
949 struct cqspi_st *cqspi = f_pdata->cqspi;
950 void __iomem *iobase = cqspi->iobase;
951 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
952 unsigned int tshsl, tchsh, tslch, tsd2d;
956 /* calculate the number of ref ticks for one sclk tick */
957 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
959 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
960 /* this particular value must be at least one sclk */
964 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
965 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
966 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
968 reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
969 << CQSPI_REG_DELAY_TSHSL_LSB;
970 reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
971 << CQSPI_REG_DELAY_TCHSH_LSB;
972 reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
973 << CQSPI_REG_DELAY_TSLCH_LSB;
974 reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
975 << CQSPI_REG_DELAY_TSD2D_LSB;
976 writel(reg, iobase + CQSPI_REG_DELAY);
979 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
981 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
982 void __iomem *reg_base = cqspi->iobase;
985 /* Recalculate the baudrate divisor based on QSPI specification. */
986 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
988 reg = readl(reg_base + CQSPI_REG_CONFIG);
989 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
990 reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
991 writel(reg, reg_base + CQSPI_REG_CONFIG);
994 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
996 const unsigned int delay)
998 void __iomem *reg_base = cqspi->iobase;
1001 reg = readl(reg_base + CQSPI_REG_READCAPTURE);
1004 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
1006 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
1008 reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
1009 << CQSPI_REG_READCAPTURE_DELAY_LSB);
1011 reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
1012 << CQSPI_REG_READCAPTURE_DELAY_LSB;
1014 writel(reg, reg_base + CQSPI_REG_READCAPTURE);
1017 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
1019 void __iomem *reg_base = cqspi->iobase;
1022 reg = readl(reg_base + CQSPI_REG_CONFIG);
1025 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
1027 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
1029 writel(reg, reg_base + CQSPI_REG_CONFIG);
1032 static void cqspi_configure(struct cqspi_flash_pdata *f_pdata,
1035 struct cqspi_st *cqspi = f_pdata->cqspi;
1036 int switch_cs = (cqspi->current_cs != f_pdata->cs);
1037 int switch_ck = (cqspi->sclk != sclk);
1039 if (switch_cs || switch_ck)
1040 cqspi_controller_enable(cqspi, 0);
1042 /* Switch chip select. */
1044 cqspi->current_cs = f_pdata->cs;
1045 cqspi_chipselect(f_pdata);
1048 /* Setup baudrate divisor and delays */
1051 cqspi_config_baudrate_div(cqspi);
1052 cqspi_delay(f_pdata);
1053 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
1054 f_pdata->read_delay);
1057 if (switch_cs || switch_ck)
1058 cqspi_controller_enable(cqspi, 1);
1061 static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
1062 const struct spi_mem_op *op)
1064 struct cqspi_st *cqspi = f_pdata->cqspi;
1065 loff_t to = op->addr.val;
1066 size_t len = op->data.nbytes;
1067 const u_char *buf = op->data.buf.out;
1070 ret = cqspi_set_protocol(f_pdata, op);
1074 ret = cqspi_write_setup(f_pdata, op);
1079 * Some flashes like the Cypress Semper flash expect a dummy 4-byte
1080 * address (all 0s) with the read status register command in DTR mode.
1081 * But this controller does not support sending dummy address bytes to
1082 * the flash when it is polling the write completion register in DTR
1083 * mode. So, we can not use direct mode when in DTR mode for writing
1086 if (!f_pdata->dtr && cqspi->use_direct_mode &&
1087 ((to + len) <= cqspi->ahb_size)) {
1088 memcpy_toio(cqspi->ahb_base + to, buf, len);
1089 return cqspi_wait_idle(cqspi);
1092 return cqspi_indirect_write_execute(f_pdata, to, buf, len);
1095 static void cqspi_rx_dma_callback(void *param)
1097 struct cqspi_st *cqspi = param;
1099 complete(&cqspi->rx_dma_complete);
1102 static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
1103 u_char *buf, loff_t from, size_t len)
1105 struct cqspi_st *cqspi = f_pdata->cqspi;
1106 struct device *dev = &cqspi->pdev->dev;
1107 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
1108 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
1110 struct dma_async_tx_descriptor *tx;
1111 dma_cookie_t cookie;
1113 struct device *ddev;
1115 if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
1116 memcpy_fromio(buf, cqspi->ahb_base + from, len);
1120 ddev = cqspi->rx_chan->device->dev;
1121 dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE);
1122 if (dma_mapping_error(ddev, dma_dst)) {
1123 dev_err(dev, "dma mapping failed\n");
1126 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
1129 dev_err(dev, "device_prep_dma_memcpy error\n");
1134 tx->callback = cqspi_rx_dma_callback;
1135 tx->callback_param = cqspi;
1136 cookie = tx->tx_submit(tx);
1137 reinit_completion(&cqspi->rx_dma_complete);
1139 ret = dma_submit_error(cookie);
1141 dev_err(dev, "dma_submit_error %d\n", cookie);
1146 dma_async_issue_pending(cqspi->rx_chan);
1147 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
1148 msecs_to_jiffies(max_t(size_t, len, 500)))) {
1149 dmaengine_terminate_sync(cqspi->rx_chan);
1150 dev_err(dev, "DMA wait_for_completion_timeout\n");
1156 dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE);
1161 static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
1162 const struct spi_mem_op *op)
1164 struct cqspi_st *cqspi = f_pdata->cqspi;
1165 loff_t from = op->addr.val;
1166 size_t len = op->data.nbytes;
1167 u_char *buf = op->data.buf.in;
1170 ret = cqspi_set_protocol(f_pdata, op);
1174 ret = cqspi_read_setup(f_pdata, op);
1178 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
1179 return cqspi_direct_read_execute(f_pdata, buf, from, len);
1181 return cqspi_indirect_read_execute(f_pdata, buf, from, len);
1184 static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
1186 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
1187 struct cqspi_flash_pdata *f_pdata;
1189 f_pdata = &cqspi->f_pdata[mem->spi->chip_select];
1190 cqspi_configure(f_pdata, mem->spi->max_speed_hz);
1192 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
1193 if (!op->addr.nbytes)
1194 return cqspi_command_read(f_pdata, op);
1196 return cqspi_read(f_pdata, op);
1199 if (!op->addr.nbytes || !op->data.buf.out)
1200 return cqspi_command_write(f_pdata, op);
1202 return cqspi_write(f_pdata, op);
1205 static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
1209 ret = cqspi_mem_process(mem, op);
1211 dev_err(&mem->spi->dev, "operation failed with %d\n", ret);
1216 static bool cqspi_supports_mem_op(struct spi_mem *mem,
1217 const struct spi_mem_op *op)
1219 bool all_true, all_false;
1222 * op->dummy.dtr is required for converting nbytes into ncycles.
1223 * Also, don't check the dtr field of the op phase having zero nbytes.
1225 all_true = op->cmd.dtr &&
1226 (!op->addr.nbytes || op->addr.dtr) &&
1227 (!op->dummy.nbytes || op->dummy.dtr) &&
1228 (!op->data.nbytes || op->data.dtr);
1230 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
1234 /* Right now we only support 8-8-8 DTR mode. */
1235 if (op->cmd.nbytes && op->cmd.buswidth != 8)
1237 if (op->addr.nbytes && op->addr.buswidth != 8)
1239 if (op->data.nbytes && op->data.buswidth != 8)
1241 } else if (all_false) {
1242 /* Only 1-1-X ops are supported without DTR */
1243 if (op->cmd.nbytes && op->cmd.buswidth > 1)
1245 if (op->addr.nbytes && op->addr.buswidth > 1)
1248 /* Mixed DTR modes are not supported. */
1253 return spi_mem_dtr_supports_op(mem, op);
1255 return spi_mem_default_supports_op(mem, op);
1258 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1259 struct cqspi_flash_pdata *f_pdata,
1260 struct device_node *np)
1262 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1263 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1267 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1268 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1272 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1273 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1277 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1278 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1282 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1283 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1287 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1288 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1295 static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
1297 struct device *dev = &cqspi->pdev->dev;
1298 struct device_node *np = dev->of_node;
1300 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1302 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1303 dev_err(dev, "couldn't determine fifo-depth\n");
1307 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1308 dev_err(dev, "couldn't determine fifo-width\n");
1312 if (of_property_read_u32(np, "cdns,trigger-address",
1313 &cqspi->trigger_address)) {
1314 dev_err(dev, "couldn't determine trigger-address\n");
1318 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
1319 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;
1321 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1326 static void cqspi_controller_init(struct cqspi_st *cqspi)
1330 cqspi_controller_enable(cqspi, 0);
1332 /* Configure the remap address register, no remap */
1333 writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1335 /* Disable all interrupts. */
1336 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1338 /* Configure the SRAM split to 1:1 . */
1339 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1341 /* Load indirect trigger address. */
1342 writel(cqspi->trigger_address,
1343 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1345 /* Program read watermark -- 1/2 of the FIFO. */
1346 writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1347 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1348 /* Program write watermark -- 1/8 of the FIFO. */
1349 writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1350 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1352 /* Disable direct access controller */
1353 if (!cqspi->use_direct_mode) {
1354 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1355 reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1356 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1359 cqspi_controller_enable(cqspi, 1);
1362 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1364 dma_cap_mask_t mask;
1367 dma_cap_set(DMA_MEMCPY, mask);
1369 cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1370 if (IS_ERR(cqspi->rx_chan)) {
1371 int ret = PTR_ERR(cqspi->rx_chan);
1372 cqspi->rx_chan = NULL;
1373 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");
1375 init_completion(&cqspi->rx_dma_complete);
1380 static const char *cqspi_get_name(struct spi_mem *mem)
1382 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
1383 struct device *dev = &cqspi->pdev->dev;
1385 return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
1388 static const struct spi_controller_mem_ops cqspi_mem_ops = {
1389 .exec_op = cqspi_exec_mem_op,
1390 .get_name = cqspi_get_name,
1391 .supports_op = cqspi_supports_mem_op,
1394 static int cqspi_setup_flash(struct cqspi_st *cqspi)
1396 struct platform_device *pdev = cqspi->pdev;
1397 struct device *dev = &pdev->dev;
1398 struct device_node *np = dev->of_node;
1399 struct cqspi_flash_pdata *f_pdata;
1403 /* Get flash device data */
1404 for_each_available_child_of_node(dev->of_node, np) {
1405 ret = of_property_read_u32(np, "reg", &cs);
1407 dev_err(dev, "Couldn't determine chip select.\n");
1412 if (cs >= CQSPI_MAX_CHIPSELECT) {
1413 dev_err(dev, "Chip select %d out of range.\n", cs);
1418 f_pdata = &cqspi->f_pdata[cs];
1419 f_pdata->cqspi = cqspi;
1422 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1432 static int cqspi_probe(struct platform_device *pdev)
1434 const struct cqspi_driver_platdata *ddata;
1435 struct reset_control *rstc, *rstc_ocp;
1436 struct device *dev = &pdev->dev;
1437 struct spi_master *master;
1438 struct resource *res_ahb;
1439 struct cqspi_st *cqspi;
1440 struct resource *res;
1444 master = spi_alloc_master(&pdev->dev, sizeof(*cqspi));
1446 dev_err(&pdev->dev, "spi_alloc_master failed\n");
1449 master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
1450 master->mem_ops = &cqspi_mem_ops;
1451 master->dev.of_node = pdev->dev.of_node;
1453 cqspi = spi_master_get_devdata(master);
1456 platform_set_drvdata(pdev, cqspi);
1458 /* Obtain configuration from OF. */
1459 ret = cqspi_of_get_pdata(cqspi);
1461 dev_err(dev, "Cannot get mandatory OF data.\n");
1463 goto probe_master_put;
1466 /* Obtain QSPI clock. */
1467 cqspi->clk = devm_clk_get(dev, NULL);
1468 if (IS_ERR(cqspi->clk)) {
1469 dev_err(dev, "Cannot claim QSPI clock.\n");
1470 ret = PTR_ERR(cqspi->clk);
1471 goto probe_master_put;
1474 /* Obtain and remap controller address. */
1475 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1476 cqspi->iobase = devm_ioremap_resource(dev, res);
1477 if (IS_ERR(cqspi->iobase)) {
1478 dev_err(dev, "Cannot remap controller address.\n");
1479 ret = PTR_ERR(cqspi->iobase);
1480 goto probe_master_put;
1483 /* Obtain and remap AHB address. */
1484 res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1485 cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1486 if (IS_ERR(cqspi->ahb_base)) {
1487 dev_err(dev, "Cannot remap AHB address.\n");
1488 ret = PTR_ERR(cqspi->ahb_base);
1489 goto probe_master_put;
1491 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1492 cqspi->ahb_size = resource_size(res_ahb);
1494 init_completion(&cqspi->transfer_complete);
1496 /* Obtain IRQ line. */
1497 irq = platform_get_irq(pdev, 0);
1500 goto probe_master_put;
1503 pm_runtime_enable(dev);
1504 ret = pm_runtime_get_sync(dev);
1506 pm_runtime_put_noidle(dev);
1507 goto probe_master_put;
1510 ret = clk_prepare_enable(cqspi->clk);
1512 dev_err(dev, "Cannot enable QSPI clock.\n");
1513 goto probe_clk_failed;
1516 /* Obtain QSPI reset control */
1517 rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
1519 ret = PTR_ERR(rstc);
1520 dev_err(dev, "Cannot get QSPI reset.\n");
1521 goto probe_reset_failed;
1524 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
1525 if (IS_ERR(rstc_ocp)) {
1526 ret = PTR_ERR(rstc_ocp);
1527 dev_err(dev, "Cannot get QSPI OCP reset.\n");
1528 goto probe_reset_failed;
1531 reset_control_assert(rstc);
1532 reset_control_deassert(rstc);
1534 reset_control_assert(rstc_ocp);
1535 reset_control_deassert(rstc_ocp);
1537 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1538 master->max_speed_hz = cqspi->master_ref_clk_hz;
1540 /* write completion is supported by default */
1541 cqspi->wr_completion = true;
1543 ddata = of_device_get_match_data(dev);
1545 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
1546 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
1547 cqspi->master_ref_clk_hz);
1548 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
1549 master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
1550 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE))
1551 cqspi->use_direct_mode = true;
1552 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION)
1553 cqspi->wr_completion = false;
1556 ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1559 dev_err(dev, "Cannot request IRQ.\n");
1560 goto probe_reset_failed;
1563 cqspi_wait_idle(cqspi);
1564 cqspi_controller_init(cqspi);
1565 cqspi->current_cs = -1;
1568 master->num_chipselect = cqspi->num_chipselect;
1570 ret = cqspi_setup_flash(cqspi);
1572 dev_err(dev, "failed to setup flash parameters %d\n", ret);
1573 goto probe_setup_failed;
1576 if (cqspi->use_direct_mode) {
1577 ret = cqspi_request_mmap_dma(cqspi);
1578 if (ret == -EPROBE_DEFER)
1579 goto probe_setup_failed;
1582 ret = devm_spi_register_master(dev, master);
1584 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
1585 goto probe_setup_failed;
1590 cqspi_controller_enable(cqspi, 0);
1592 clk_disable_unprepare(cqspi->clk);
1594 pm_runtime_put_sync(dev);
1595 pm_runtime_disable(dev);
1597 spi_master_put(master);
1601 static int cqspi_remove(struct platform_device *pdev)
1603 struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1605 cqspi_controller_enable(cqspi, 0);
1608 dma_release_channel(cqspi->rx_chan);
1610 clk_disable_unprepare(cqspi->clk);
1612 pm_runtime_put_sync(&pdev->dev);
1613 pm_runtime_disable(&pdev->dev);
1618 #ifdef CONFIG_PM_SLEEP
1619 static int cqspi_suspend(struct device *dev)
1621 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1623 cqspi_controller_enable(cqspi, 0);
1627 static int cqspi_resume(struct device *dev)
1629 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1631 cqspi_controller_enable(cqspi, 1);
1635 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1636 .suspend = cqspi_suspend,
1637 .resume = cqspi_resume,
1640 #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops)
1642 #define CQSPI_DEV_PM_OPS NULL
1645 static const struct cqspi_driver_platdata cdns_qspi = {
1646 .quirks = CQSPI_DISABLE_DAC_MODE,
1649 static const struct cqspi_driver_platdata k2g_qspi = {
1650 .quirks = CQSPI_NEEDS_WR_DELAY,
1653 static const struct cqspi_driver_platdata am654_ospi = {
1654 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
1655 .quirks = CQSPI_NEEDS_WR_DELAY,
1658 static const struct cqspi_driver_platdata intel_lgm_qspi = {
1659 .quirks = CQSPI_DISABLE_DAC_MODE,
1662 static const struct cqspi_driver_platdata socfpga_qspi = {
1663 .quirks = CQSPI_NO_SUPPORT_WR_COMPLETION,
1666 static const struct of_device_id cqspi_dt_ids[] = {
1668 .compatible = "cdns,qspi-nor",
1672 .compatible = "ti,k2g-qspi",
1676 .compatible = "ti,am654-ospi",
1677 .data = &am654_ospi,
1680 .compatible = "intel,lgm-qspi",
1681 .data = &intel_lgm_qspi,
1684 .compatible = "intel,socfpga-qspi",
1685 .data = (void *)&socfpga_qspi,
1687 { /* end of table */ }
1690 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1692 static struct platform_driver cqspi_platform_driver = {
1693 .probe = cqspi_probe,
1694 .remove = cqspi_remove,
1697 .pm = CQSPI_DEV_PM_OPS,
1698 .of_match_table = cqspi_dt_ids,
1702 module_platform_driver(cqspi_platform_driver);
1704 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1705 MODULE_LICENSE("GPL v2");
1706 MODULE_ALIAS("platform:" CQSPI_NAME);
1707 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1708 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
1709 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
1710 MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>");
1711 MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>");