drivers/spi/spi-bfin5xx.c

   1 /*
   2  * Blackfin On-Chip SPI Driver
   3  *
   4  * Copyright 2004-2010 Analog Devices Inc.
   5  *
   6  * Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/module.h>
  13 #include <linux/delay.h>
  14 #include <linux/device.h>
  15 #include <linux/slab.h>
  16 #include <linux/io.h>
  17 #include <linux/ioport.h>
  18 #include <linux/irq.h>
  19 #include <linux/errno.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/spi/spi.h>
  24 #include <linux/workqueue.h>
  25
  26 #include <asm/dma.h>
  27 #include <asm/portmux.h>
  28 #include <asm/bfin5xx_spi.h>
  29 #include <asm/cacheflush.h>
  30
  31 #define DRV_NAME        "bfin-spi"
  32 #define DRV_AUTHOR      "Bryan Wu, Luke Yang"
  33 #define DRV_DESC        "Blackfin on-chip SPI Controller Driver"
  34 #define DRV_VERSION     "1.0"
  35
  36 MODULE_AUTHOR(DRV_AUTHOR);
  37 MODULE_DESCRIPTION(DRV_DESC);
  38 MODULE_LICENSE("GPL");
  39
  40 #define START_STATE     ((void *)0)
  41 #define RUNNING_STATE   ((void *)1)
  42 #define DONE_STATE      ((void *)2)
  43 #define ERROR_STATE     ((void *)-1)
  44
  45 struct bfin_spi_master_data;
  46
  47 struct bfin_spi_transfer_ops {
  48         void (*write) (struct bfin_spi_master_data *);
  49         void (*read) (struct bfin_spi_master_data *);
  50         void (*duplex) (struct bfin_spi_master_data *);
  51 };
  52
  53 struct bfin_spi_master_data {
  54         /* Driver model hookup */
  55         struct platform_device *pdev;
  56
  57         /* SPI framework hookup */
  58         struct spi_master *master;
  59
  60         /* Regs base of SPI controller */
  61         struct bfin_spi_regs __iomem *regs;
  62
  63         /* Pin request list */
  64         u16 *pin_req;
  65
  66         /* BFIN hookup */
  67         struct bfin5xx_spi_master *master_info;
  68
  69         /* Driver message queue */
  70         struct workqueue_struct *workqueue;
  71         struct work_struct pump_messages;
  72         spinlock_t lock;
  73         struct list_head queue;
  74         int busy;
  75         bool running;
  76
  77         /* Message Transfer pump */
  78         struct tasklet_struct pump_transfers;
  79
  80         /* Current message transfer state info */
  81         struct spi_message *cur_msg;
  82         struct spi_transfer *cur_transfer;
  83         struct bfin_spi_slave_data *cur_chip;
  84         size_t len_in_bytes;
  85         size_t len;
  86         void *tx;
  87         void *tx_end;
  88         void *rx;
  89         void *rx_end;
  90
  91         /* DMA stuffs */
  92         int dma_channel;
  93         int dma_mapped;
  94         int dma_requested;
  95         dma_addr_t rx_dma;
  96         dma_addr_t tx_dma;
  97
  98         int irq_requested;
  99         int spi_irq;
 100
 101         size_t rx_map_len;
 102         size_t tx_map_len;
 103         u8 n_bytes;
 104         u16 ctrl_reg;
 105         u16 flag_reg;
 106
 107         int cs_change;
 108         const struct bfin_spi_transfer_ops *ops;
 109 };
 110
 111 struct bfin_spi_slave_data {
 112         u16 ctl_reg;
 113         u16 baud;
 114         u16 flag;
 115
 116         u8 chip_select_num;
 117         u8 enable_dma;
 118         u16 cs_chg_udelay;      /* Some devices require > 255usec delay */
 119         u32 cs_gpio;
 120         u16 idle_tx_val;
 121         u8 pio_interrupt;       /* use spi data irq */
 122         const struct bfin_spi_transfer_ops *ops;
 123 };
 124
 125 static void bfin_spi_enable(struct bfin_spi_master_data *drv_data)
 126 {
 127         bfin_write_or(&drv_data->regs->ctl, BIT_CTL_ENABLE);
 128 }
 129
 130 static void bfin_spi_disable(struct bfin_spi_master_data *drv_data)
 131 {
 132         bfin_write_and(&drv_data->regs->ctl, ~BIT_CTL_ENABLE);
 133 }
 134
 135 /* Caculate the SPI_BAUD register value based on input HZ */
 136 static u16 hz_to_spi_baud(u32 speed_hz)
 137 {
 138         u_long sclk = get_sclk();
 139         u16 spi_baud = (sclk / (2 * speed_hz));
 140
 141         if ((sclk % (2 * speed_hz)) > 0)
 142                 spi_baud++;
 143
 144         if (spi_baud < MIN_SPI_BAUD_VAL)
 145                 spi_baud = MIN_SPI_BAUD_VAL;
 146
 147         return spi_baud;
 148 }
 149
 150 static int bfin_spi_flush(struct bfin_spi_master_data *drv_data)
 151 {
 152         unsigned long limit = loops_per_jiffy << 1;
 153
 154         /* wait for stop and clear stat */
 155         while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF) && --limit)
 156                 cpu_relax();
 157
 158         bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
 159
 160         return limit;
 161 }
 162
 163 /* Chip select operation functions for cs_change flag */
 164 static void bfin_spi_cs_active(struct bfin_spi_master_data *drv_data, struct bfin_spi_slave_data *chip)
 165 {
 166         if (likely(chip->chip_select_num < MAX_CTRL_CS))
 167                 bfin_write_and(&drv_data->regs->flg, ~chip->flag);
 168         else
 169                 gpio_set_value(chip->cs_gpio, 0);
 170 }
 171
 172 static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data,
 173                                  struct bfin_spi_slave_data *chip)
 174 {
 175         if (likely(chip->chip_select_num < MAX_CTRL_CS))
 176                 bfin_write_or(&drv_data->regs->flg, chip->flag);
 177         else
 178                 gpio_set_value(chip->cs_gpio, 1);
 179
 180         /* Move delay here for consistency */
 181         if (chip->cs_chg_udelay)
 182                 udelay(chip->cs_chg_udelay);
 183 }
 184
 185 /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
 186 static inline void bfin_spi_cs_enable(struct bfin_spi_master_data *drv_data,
 187                                       struct bfin_spi_slave_data *chip)
 188 {
 189         if (chip->chip_select_num < MAX_CTRL_CS)
 190                 bfin_write_or(&drv_data->regs->flg, chip->flag >> 8);
 191 }
 192
 193 static inline void bfin_spi_cs_disable(struct bfin_spi_master_data *drv_data,
 194                                        struct bfin_spi_slave_data *chip)
 195 {
 196         if (chip->chip_select_num < MAX_CTRL_CS)
 197                 bfin_write_and(&drv_data->regs->flg, ~(chip->flag >> 8));
 198 }
 199
 200 /* stop controller and re-config current chip*/
 201 static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data)
 202 {
 203         struct bfin_spi_slave_data *chip = drv_data->cur_chip;
 204
 205         /* Clear status and disable clock */
 206         bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
 207         bfin_spi_disable(drv_data);
 208         dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
 209
 210         SSYNC();
 211
 212         /* Load the registers */
 213         bfin_write(&drv_data->regs->ctl, chip->ctl_reg);
 214         bfin_write(&drv_data->regs->baud, chip->baud);
 215
 216         bfin_spi_enable(drv_data);
 217         bfin_spi_cs_active(drv_data, chip);
 218 }
 219
 220 /* used to kick off transfer in rx mode and read unwanted RX data */
 221 static inline void bfin_spi_dummy_read(struct bfin_spi_master_data *drv_data)
 222 {
 223         (void) bfin_read(&drv_data->regs->rdbr);
 224 }
 225
 226 static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data)
 227 {
 228         /* clear RXS (we check for RXS inside the loop) */
 229         bfin_spi_dummy_read(drv_data);
 230
 231         while (drv_data->tx < drv_data->tx_end) {
 232                 bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
 233                 /* wait until transfer finished.
 234                    checking SPIF or TXS may not guarantee transfer completion */
 235                 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
 236                         cpu_relax();
 237                 /* discard RX data and clear RXS */
 238                 bfin_spi_dummy_read(drv_data);
 239         }
 240 }
 241
 242 static void bfin_spi_u8_reader(struct bfin_spi_master_data *drv_data)
 243 {
 244         u16 tx_val = drv_data->cur_chip->idle_tx_val;
 245
 246         /* discard old RX data and clear RXS */
 247         bfin_spi_dummy_read(drv_data);
 248
 249         while (drv_data->rx < drv_data->rx_end) {
 250                 bfin_write(&drv_data->regs->tdbr, tx_val);
 251                 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
 252                         cpu_relax();
 253                 *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
 254         }
 255 }
 256
 257 static void bfin_spi_u8_duplex(struct bfin_spi_master_data *drv_data)
 258 {
 259         /* discard old RX data and clear RXS */
 260         bfin_spi_dummy_read(drv_data);
 261
 262         while (drv_data->rx < drv_data->rx_end) {
 263                 bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
 264                 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
 265                         cpu_relax();
 266                 *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
 267         }
 268 }
 269
 270 static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8 = {
 271         .write  = bfin_spi_u8_writer,
 272         .read   = bfin_spi_u8_reader,
 273         .duplex = bfin_spi_u8_duplex,
 274 };
 275
 276 static void bfin_spi_u16_writer(struct bfin_spi_master_data *drv_data)
 277 {
 278         /* clear RXS (we check for RXS inside the loop) */
 279         bfin_spi_dummy_read(drv_data);
 280
 281         while (drv_data->tx < drv_data->tx_end) {
 282                 bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
 283                 drv_data->tx += 2;
 284                 /* wait until transfer finished.
 285                    checking SPIF or TXS may not guarantee transfer completion */
 286                 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
 287                         cpu_relax();
 288                 /* discard RX data and clear RXS */
 289                 bfin_spi_dummy_read(drv_data);
 290         }
 291 }
 292
 293 static void bfin_spi_u16_reader(struct bfin_spi_master_data *drv_data)
 294 {
 295         u16 tx_val = drv_data->cur_chip->idle_tx_val;
 296
 297         /* discard old RX data and clear RXS */
 298         bfin_spi_dummy_read(drv_data);
 299
 300         while (drv_data->rx < drv_data->rx_end) {
 301                 bfin_write(&drv_data->regs->tdbr, tx_val);
 302                 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
 303                         cpu_relax();
 304                 *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
 305                 drv_data->rx += 2;
 306         }
 307 }
 308
 309 static void bfin_spi_u16_duplex(struct bfin_spi_master_data *drv_data)
 310 {
 311         /* discard old RX data and clear RXS */
 312         bfin_spi_dummy_read(drv_data);
 313
 314         while (drv_data->rx < drv_data->rx_end) {
 315                 bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
 316                 drv_data->tx += 2;
 317                 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
 318                         cpu_relax();
 319                 *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
 320                 drv_data->rx += 2;
 321         }
 322 }
 323
 324 static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16 = {
 325         .write  = bfin_spi_u16_writer,
 326         .read   = bfin_spi_u16_reader,
 327         .duplex = bfin_spi_u16_duplex,
 328 };
 329
 330 /* test if there is more transfer to be done */
 331 static void *bfin_spi_next_transfer(struct bfin_spi_master_data *drv_data)
 332 {
 333         struct spi_message *msg = drv_data->cur_msg;
 334         struct spi_transfer *trans = drv_data->cur_transfer;
 335
 336         /* Move to next transfer */
 337         if (trans->transfer_list.next != &msg->transfers) {
 338                 drv_data->cur_transfer =
 339                     list_entry(trans->transfer_list.next,
 340                                struct spi_transfer, transfer_list);
 341                 return RUNNING_STATE;
 342         } else
 343                 return DONE_STATE;
 344 }
 345
 346 /*
 347  * caller already set message->status;
 348  * dma and pio irqs are blocked give finished message back
 349  */
 350 static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data)
 351 {
 352         struct bfin_spi_slave_data *chip = drv_data->cur_chip;
 353         struct spi_transfer *last_transfer;
 354         unsigned long flags;
 355         struct spi_message *msg;
 356
 357         spin_lock_irqsave(&drv_data->lock, flags);
 358         msg = drv_data->cur_msg;
 359         drv_data->cur_msg = NULL;
 360         drv_data->cur_transfer = NULL;
 361         drv_data->cur_chip = NULL;
 362         queue_work(drv_data->workqueue, &drv_data->pump_messages);
 363         spin_unlock_irqrestore(&drv_data->lock, flags);
 364
 365         last_transfer = list_entry(msg->transfers.prev,
 366                                    struct spi_transfer, transfer_list);
 367
 368         msg->state = NULL;
 369
 370         if (!drv_data->cs_change)
 371                 bfin_spi_cs_deactive(drv_data, chip);
 372
 373         /* Not stop spi in autobuffer mode */
 374         if (drv_data->tx_dma != 0xFFFF)
 375                 bfin_spi_disable(drv_data);
 376
 377         if (msg->complete)
 378                 msg->complete(msg->context);
 379 }
 380
 381 /* spi data irq handler */
 382 static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
 383 {
 384         struct bfin_spi_master_data *drv_data = dev_id;
 385         struct bfin_spi_slave_data *chip = drv_data->cur_chip;
 386         struct spi_message *msg = drv_data->cur_msg;
 387         int n_bytes = drv_data->n_bytes;
 388         int loop = 0;
 389
 390         /* wait until transfer finished. */
 391         while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
 392                 cpu_relax();
 393
 394         if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
 395                 (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
 396                 /* last read */
 397                 if (drv_data->rx) {
 398                         dev_dbg(&drv_data->pdev->dev, "last read\n");
 399                         if (!(n_bytes % 2)) {
 400                                 u16 *buf = (u16 *)drv_data->rx;
 401                                 for (loop = 0; loop < n_bytes / 2; loop++)
 402                                         *buf++ = bfin_read(&drv_data->regs->rdbr);
 403                         } else {
 404                                 u8 *buf = (u8 *)drv_data->rx;
 405                                 for (loop = 0; loop < n_bytes; loop++)
 406                                         *buf++ = bfin_read(&drv_data->regs->rdbr);
 407                         }
 408                         drv_data->rx += n_bytes;
 409                 }
 410
 411                 msg->actual_length += drv_data->len_in_bytes;
 412                 if (drv_data->cs_change)
 413                         bfin_spi_cs_deactive(drv_data, chip);
 414                 /* Move to next transfer */
 415                 msg->state = bfin_spi_next_transfer(drv_data);
 416
 417                 disable_irq_nosync(drv_data->spi_irq);
 418
 419                 /* Schedule transfer tasklet */
 420                 tasklet_schedule(&drv_data->pump_transfers);
 421                 return IRQ_HANDLED;
 422         }
 423
 424         if (drv_data->rx && drv_data->tx) {
 425                 /* duplex */
 426                 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
 427                 if (!(n_bytes % 2)) {
 428                         u16 *buf = (u16 *)drv_data->rx;
 429                         u16 *buf2 = (u16 *)drv_data->tx;
 430                         for (loop = 0; loop < n_bytes / 2; loop++) {
 431                                 *buf++ = bfin_read(&drv_data->regs->rdbr);
 432                                 bfin_write(&drv_data->regs->tdbr, *buf2++);
 433                         }
 434                 } else {
 435                         u8 *buf = (u8 *)drv_data->rx;
 436                         u8 *buf2 = (u8 *)drv_data->tx;
 437                         for (loop = 0; loop < n_bytes; loop++) {
 438                                 *buf++ = bfin_read(&drv_data->regs->rdbr);
 439                                 bfin_write(&drv_data->regs->tdbr, *buf2++);
 440                         }
 441                 }
 442         } else if (drv_data->rx) {
 443                 /* read */
 444                 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
 445                 if (!(n_bytes % 2)) {
 446                         u16 *buf = (u16 *)drv_data->rx;
 447                         for (loop = 0; loop < n_bytes / 2; loop++) {
 448                                 *buf++ = bfin_read(&drv_data->regs->rdbr);
 449                                 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
 450                         }
 451                 } else {
 452                         u8 *buf = (u8 *)drv_data->rx;
 453                         for (loop = 0; loop < n_bytes; loop++) {
 454                                 *buf++ = bfin_read(&drv_data->regs->rdbr);
 455                                 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
 456                         }
 457                 }
 458         } else if (drv_data->tx) {
 459                 /* write */
 460                 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
 461                 if (!(n_bytes % 2)) {
 462                         u16 *buf = (u16 *)drv_data->tx;
 463                         for (loop = 0; loop < n_bytes / 2; loop++) {
 464                                 bfin_read(&drv_data->regs->rdbr);
 465                                 bfin_write(&drv_data->regs->tdbr, *buf++);
 466                         }
 467                 } else {
 468                         u8 *buf = (u8 *)drv_data->tx;
 469                         for (loop = 0; loop < n_bytes; loop++) {
 470                                 bfin_read(&drv_data->regs->rdbr);
 471                                 bfin_write(&drv_data->regs->tdbr, *buf++);
 472                         }
 473                 }
 474         }
 475
 476         if (drv_data->tx)
 477                 drv_data->tx += n_bytes;
 478         if (drv_data->rx)
 479                 drv_data->rx += n_bytes;
 480
 481         return IRQ_HANDLED;
 482 }
 483
 484 static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
 485 {
 486         struct bfin_spi_master_data *drv_data = dev_id;
 487         struct bfin_spi_slave_data *chip = drv_data->cur_chip;
 488         struct spi_message *msg = drv_data->cur_msg;
 489         unsigned long timeout;
 490         unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
 491         u16 spistat = bfin_read(&drv_data->regs->stat);
 492
 493         dev_dbg(&drv_data->pdev->dev,
 494                 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
 495                 dmastat, spistat);
 496
 497         if (drv_data->rx != NULL) {
 498                 u16 cr = bfin_read(&drv_data->regs->ctl);
 499                 /* discard old RX data and clear RXS */
 500                 bfin_spi_dummy_read(drv_data);
 501                 bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_ENABLE); /* Disable SPI */
 502                 bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_TIMOD); /* Restore State */
 503                 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); /* Clear Status */
 504         }
 505
 506         clear_dma_irqstat(drv_data->dma_channel);
 507
 508         /*
 509          * wait for the last transaction shifted out.  HRM states:
 510          * at this point there may still be data in the SPI DMA FIFO waiting
 511          * to be transmitted ... software needs to poll TXS in the SPI_STAT
 512          * register until it goes low for 2 successive reads
 513          */
 514         if (drv_data->tx != NULL) {
 515                 while ((bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS) ||
 516                        (bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS))
 517                         cpu_relax();
 518         }
 519
 520         dev_dbg(&drv_data->pdev->dev,
 521                 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
 522                 dmastat, bfin_read(&drv_data->regs->stat));
 523
 524         timeout = jiffies + HZ;
 525         while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
 526                 if (!time_before(jiffies, timeout)) {
 527                         dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF\n");
 528                         break;
 529                 } else
 530                         cpu_relax();
 531
 532         if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) {
 533                 msg->state = ERROR_STATE;
 534                 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
 535         } else {
 536                 msg->actual_length += drv_data->len_in_bytes;
 537
 538                 if (drv_data->cs_change)
 539                         bfin_spi_cs_deactive(drv_data, chip);
 540
 541                 /* Move to next transfer */
 542                 msg->state = bfin_spi_next_transfer(drv_data);
 543         }
 544
 545         /* Schedule transfer tasklet */
 546         tasklet_schedule(&drv_data->pump_transfers);
 547
 548         /* free the irq handler before next transfer */
 549         dev_dbg(&drv_data->pdev->dev,
 550                 "disable dma channel irq%d\n",
 551                 drv_data->dma_channel);
 552         dma_disable_irq_nosync(drv_data->dma_channel);
 553
 554         return IRQ_HANDLED;
 555 }
 556
 557 static void bfin_spi_pump_transfers(unsigned long data)
 558 {
 559         struct bfin_spi_master_data *drv_data = (struct bfin_spi_master_data *)data;
 560         struct spi_message *message = NULL;
 561         struct spi_transfer *transfer = NULL;
 562         struct spi_transfer *previous = NULL;
 563         struct bfin_spi_slave_data *chip = NULL;
 564         unsigned int bits_per_word;
 565         u16 cr, cr_width, dma_width, dma_config;
 566         u32 tranf_success = 1;
 567         u8 full_duplex = 0;
 568
 569         /* Get current state information */
 570         message = drv_data->cur_msg;
 571         transfer = drv_data->cur_transfer;
 572         chip = drv_data->cur_chip;
 573
 574         /*
 575          * if msg is error or done, report it back using complete() callback
 576          */
 577
 578          /* Handle for abort */
 579         if (message->state == ERROR_STATE) {
 580                 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
 581                 message->status = -EIO;
 582                 bfin_spi_giveback(drv_data);
 583                 return;
 584         }
 585
 586         /* Handle end of message */
 587         if (message->state == DONE_STATE) {
 588                 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
 589                 message->status = 0;
 590                 bfin_spi_flush(drv_data);
 591                 bfin_spi_giveback(drv_data);
 592                 return;
 593         }
 594
 595         /* Delay if requested at end of transfer */
 596         if (message->state == RUNNING_STATE) {
 597                 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
 598                 previous = list_entry(transfer->transfer_list.prev,
 599                                       struct spi_transfer, transfer_list);
 600                 if (previous->delay_usecs)
 601                         udelay(previous->delay_usecs);
 602         }
 603
 604         /* Flush any existing transfers that may be sitting in the hardware */
 605         if (bfin_spi_flush(drv_data) == 0) {
 606                 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
 607                 message->status = -EIO;
 608                 bfin_spi_giveback(drv_data);
 609                 return;
 610         }
 611
 612         if (transfer->len == 0) {
 613                 /* Move to next transfer of this msg */
 614                 message->state = bfin_spi_next_transfer(drv_data);
 615                 /* Schedule next transfer tasklet */
 616                 tasklet_schedule(&drv_data->pump_transfers);
 617                 return;
 618         }
 619
 620         if (transfer->tx_buf != NULL) {
 621                 drv_data->tx = (void *)transfer->tx_buf;
 622                 drv_data->tx_end = drv_data->tx + transfer->len;
 623                 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
 624                         transfer->tx_buf, drv_data->tx_end);
 625         } else {
 626                 drv_data->tx = NULL;
 627         }
 628
 629         if (transfer->rx_buf != NULL) {
 630                 full_duplex = transfer->tx_buf != NULL;
 631                 drv_data->rx = transfer->rx_buf;
 632                 drv_data->rx_end = drv_data->rx + transfer->len;
 633                 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
 634                         transfer->rx_buf, drv_data->rx_end);
 635         } else {
 636                 drv_data->rx = NULL;
 637         }
 638
 639         drv_data->rx_dma = transfer->rx_dma;
 640         drv_data->tx_dma = transfer->tx_dma;
 641         drv_data->len_in_bytes = transfer->len;
 642         drv_data->cs_change = transfer->cs_change;
 643
 644         /* Bits per word setup */
 645         bits_per_word = transfer->bits_per_word;
 646         if (bits_per_word == 16) {
 647                 drv_data->n_bytes = bits_per_word/8;
 648                 drv_data->len = (transfer->len) >> 1;
 649                 cr_width = BIT_CTL_WORDSIZE;
 650                 drv_data->ops = &bfin_bfin_spi_transfer_ops_u16;
 651         } else if (bits_per_word == 8) {
 652                 drv_data->n_bytes = bits_per_word/8;
 653                 drv_data->len = transfer->len;
 654                 cr_width = 0;
 655                 drv_data->ops = &bfin_bfin_spi_transfer_ops_u8;
 656         }
 657         cr = bfin_read(&drv_data->regs->ctl) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE);
 658         cr |= cr_width;
 659         bfin_write(&drv_data->regs->ctl, cr);
 660
 661         dev_dbg(&drv_data->pdev->dev,
 662                 "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
 663                 drv_data->ops, chip->ops, &bfin_bfin_spi_transfer_ops_u8);
 664
 665         message->state = RUNNING_STATE;
 666         dma_config = 0;
 667
 668         /* Speed setup (surely valid because already checked) */
 669         if (transfer->speed_hz)
 670                 bfin_write(&drv_data->regs->baud, hz_to_spi_baud(transfer->speed_hz));
 671         else
 672                 bfin_write(&drv_data->regs->baud, chip->baud);
 673
 674         bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
 675         bfin_spi_cs_active(drv_data, chip);
 676
 677         dev_dbg(&drv_data->pdev->dev,
 678                 "now pumping a transfer: width is %d, len is %d\n",
 679                 cr_width, transfer->len);
 680
 681         /*
 682          * Try to map dma buffer and do a dma transfer.  If successful use,
 683          * different way to r/w according to the enable_dma settings and if
 684          * we are not doing a full duplex transfer (since the hardware does
 685          * not support full duplex DMA transfers).
 686          */
 687         if (!full_duplex && drv_data->cur_chip->enable_dma
 688                                 && drv_data->len > 6) {
 689
 690                 unsigned long dma_start_addr, flags;
 691
 692                 disable_dma(drv_data->dma_channel);
 693                 clear_dma_irqstat(drv_data->dma_channel);
 694
 695                 /* config dma channel */
 696                 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
 697                 set_dma_x_count(drv_data->dma_channel, drv_data->len);
 698                 if (cr_width == BIT_CTL_WORDSIZE) {
 699                         set_dma_x_modify(drv_data->dma_channel, 2);
 700                         dma_width = WDSIZE_16;
 701                 } else {
 702                         set_dma_x_modify(drv_data->dma_channel, 1);
 703                         dma_width = WDSIZE_8;
 704                 }
 705
 706                 /* poll for SPI completion before start */
 707                 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
 708                         cpu_relax();
 709
 710                 /* dirty hack for autobuffer DMA mode */
 711                 if (drv_data->tx_dma == 0xFFFF) {
 712                         dev_dbg(&drv_data->pdev->dev,
 713                                 "doing autobuffer DMA out.\n");
 714
 715                         /* no irq in autobuffer mode */
 716                         dma_config =
 717                             (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
 718                         set_dma_config(drv_data->dma_channel, dma_config);
 719                         set_dma_start_addr(drv_data->dma_channel,
 720                                         (unsigned long)drv_data->tx);
 721                         enable_dma(drv_data->dma_channel);
 722
 723                         /* start SPI transfer */
 724                         bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TIMOD_DMA_TX);
 725
 726                         /* just return here, there can only be one transfer
 727                          * in this mode
 728                          */
 729                         message->status = 0;
 730                         bfin_spi_giveback(drv_data);
 731                         return;
 732                 }
 733
 734                 /* In dma mode, rx or tx must be NULL in one transfer */
 735                 dma_config = (RESTART | dma_width | DI_EN);
 736                 if (drv_data->rx != NULL) {
 737                         /* set transfer mode, and enable SPI */
 738                         dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
 739                                 drv_data->rx, drv_data->len_in_bytes);
 740
 741                         /* invalidate caches, if needed */
 742                         if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
 743                                 invalidate_dcache_range((unsigned long) drv_data->rx,
 744                                                         (unsigned long) (drv_data->rx +
 745                                                         drv_data->len_in_bytes));
 746
 747                         dma_config |= WNR;
 748                         dma_start_addr = (unsigned long)drv_data->rx;
 749                         cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
 750
 751                 } else if (drv_data->tx != NULL) {
 752                         dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
 753
 754                         /* flush caches, if needed */
 755                         if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
 756                                 flush_dcache_range((unsigned long) drv_data->tx,
 757                                                 (unsigned long) (drv_data->tx +
 758                                                 drv_data->len_in_bytes));
 759
 760                         dma_start_addr = (unsigned long)drv_data->tx;
 761                         cr |= BIT_CTL_TIMOD_DMA_TX;
 762
 763                 } else
 764                         BUG();
 765
 766                 /* oh man, here there be monsters ... and i dont mean the
 767                  * fluffy cute ones from pixar, i mean the kind that'll eat
 768                  * your data, kick your dog, and love it all.  do *not* try
 769                  * and change these lines unless you (1) heavily test DMA
 770                  * with SPI flashes on a loaded system (e.g. ping floods),
 771                  * (2) know just how broken the DMA engine interaction with
 772                  * the SPI peripheral is, and (3) have someone else to blame
 773                  * when you screw it all up anyways.
 774                  */
 775                 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
 776                 set_dma_config(drv_data->dma_channel, dma_config);
 777                 local_irq_save(flags);
 778                 SSYNC();
 779                 bfin_write(&drv_data->regs->ctl, cr);
 780                 enable_dma(drv_data->dma_channel);
 781                 dma_enable_irq(drv_data->dma_channel);
 782                 local_irq_restore(flags);
 783
 784                 return;
 785         }
 786
 787         /*
 788          * We always use SPI_WRITE mode (transfer starts with TDBR write).
 789          * SPI_READ mode (transfer starts with RDBR read) seems to have
 790          * problems with setting up the output value in TDBR prior to the
 791          * start of the transfer.
 792          */
 793         bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TXMOD);
 794
 795         if (chip->pio_interrupt) {
 796                 /* SPI irq should have been disabled by now */
 797
 798                 /* discard old RX data and clear RXS */
 799                 bfin_spi_dummy_read(drv_data);
 800
 801                 /* start transfer */
 802                 if (drv_data->tx == NULL)
 803                         bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
 804                 else {
 805                         int loop;
 806                         if (bits_per_word == 16) {
 807                                 u16 *buf = (u16 *)drv_data->tx;
 808                                 for (loop = 0; loop < bits_per_word / 16;
 809                                                 loop++) {
 810                                         bfin_write(&drv_data->regs->tdbr, *buf++);
 811                                 }
 812                         } else if (bits_per_word == 8) {
 813                                 u8 *buf = (u8 *)drv_data->tx;
 814                                 for (loop = 0; loop < bits_per_word / 8; loop++)
 815                                         bfin_write(&drv_data->regs->tdbr, *buf++);
 816                         }
 817
 818                         drv_data->tx += drv_data->n_bytes;
 819                 }
 820
 821                 /* once TDBR is empty, interrupt is triggered */
 822                 enable_irq(drv_data->spi_irq);
 823                 return;
 824         }
 825
 826         /* IO mode */
 827         dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
 828
 829         if (full_duplex) {
 830                 /* full duplex mode */
 831                 BUG_ON((drv_data->tx_end - drv_data->tx) !=
 832                        (drv_data->rx_end - drv_data->rx));
 833                 dev_dbg(&drv_data->pdev->dev,
 834                         "IO duplex: cr is 0x%x\n", cr);
 835
 836                 drv_data->ops->duplex(drv_data);
 837
 838                 if (drv_data->tx != drv_data->tx_end)
 839                         tranf_success = 0;
 840         } else if (drv_data->tx != NULL) {
 841                 /* write only half duplex */
 842                 dev_dbg(&drv_data->pdev->dev,
 843                         "IO write: cr is 0x%x\n", cr);
 844
 845                 drv_data->ops->write(drv_data);
 846
 847                 if (drv_data->tx != drv_data->tx_end)
 848                         tranf_success = 0;
 849         } else if (drv_data->rx != NULL) {
 850                 /* read only half duplex */
 851                 dev_dbg(&drv_data->pdev->dev,
 852                         "IO read: cr is 0x%x\n", cr);
 853
 854                 drv_data->ops->read(drv_data);
 855                 if (drv_data->rx != drv_data->rx_end)
 856                         tranf_success = 0;
 857         }
 858
 859         if (!tranf_success) {
 860                 dev_dbg(&drv_data->pdev->dev,
 861                         "IO write error!\n");
 862                 message->state = ERROR_STATE;
 863         } else {
 864                 /* Update total byte transferred */
 865                 message->actual_length += drv_data->len_in_bytes;
 866                 /* Move to next transfer of this msg */
 867                 message->state = bfin_spi_next_transfer(drv_data);
 868                 if (drv_data->cs_change && message->state != DONE_STATE) {
 869                         bfin_spi_flush(drv_data);
 870                         bfin_spi_cs_deactive(drv_data, chip);
 871                 }
 872         }
 873
 874         /* Schedule next transfer tasklet */
 875         tasklet_schedule(&drv_data->pump_transfers);
 876 }
 877
 878 /* pop a msg from queue and kick off real transfer */
 879 static void bfin_spi_pump_messages(struct work_struct *work)
 880 {
 881         struct bfin_spi_master_data *drv_data;
 882         unsigned long flags;
 883
 884         drv_data = container_of(work, struct bfin_spi_master_data, pump_messages);
 885
 886         /* Lock queue and check for queue work */
 887         spin_lock_irqsave(&drv_data->lock, flags);
 888         if (list_empty(&drv_data->queue) || !drv_data->running) {
 889                 /* pumper kicked off but no work to do */
 890                 drv_data->busy = 0;
 891                 spin_unlock_irqrestore(&drv_data->lock, flags);
 892                 return;
 893         }
 894
 895         /* Make sure we are not already running a message */
 896         if (drv_data->cur_msg) {
 897                 spin_unlock_irqrestore(&drv_data->lock, flags);
 898                 return;
 899         }
 900
 901         /* Extract head of queue */
 902         drv_data->cur_msg = list_entry(drv_data->queue.next,
 903                                        struct spi_message, queue);
 904
 905         /* Setup the SSP using the per chip configuration */
 906         drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
 907         bfin_spi_restore_state(drv_data);
 908
 909         list_del_init(&drv_data->cur_msg->queue);
 910
 911         /* Initial message state */
 912         drv_data->cur_msg->state = START_STATE;
 913         drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
 914                                             struct spi_transfer, transfer_list);
 915
 916         dev_dbg(&drv_data->pdev->dev,
 917                 "got a message to pump, state is set to: baud "
 918                 "%d, flag 0x%x, ctl 0x%x\n",
 919                 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
 920                 drv_data->cur_chip->ctl_reg);
 921
 922         dev_dbg(&drv_data->pdev->dev,
 923                 "the first transfer len is %d\n",
 924                 drv_data->cur_transfer->len);
 925
 926         /* Mark as busy and launch transfers */
 927         tasklet_schedule(&drv_data->pump_transfers);
 928
 929         drv_data->busy = 1;
 930         spin_unlock_irqrestore(&drv_data->lock, flags);
 931 }
 932
 933 /*
 934  * got a msg to transfer, queue it in drv_data->queue.
 935  * And kick off message pumper
 936  */
 937 static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 938 {
 939         struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
 940         unsigned long flags;
 941
 942         spin_lock_irqsave(&drv_data->lock, flags);
 943
 944         if (!drv_data->running) {
 945                 spin_unlock_irqrestore(&drv_data->lock, flags);
 946                 return -ESHUTDOWN;
 947         }
 948
 949         msg->actual_length = 0;
 950         msg->status = -EINPROGRESS;
 951         msg->state = START_STATE;
 952
 953         dev_dbg(&spi->dev, "adding an msg in transfer() \n");
 954         list_add_tail(&msg->queue, &drv_data->queue);
 955
 956         if (drv_data->running && !drv_data->busy)
 957                 queue_work(drv_data->workqueue, &drv_data->pump_messages);
 958
 959         spin_unlock_irqrestore(&drv_data->lock, flags);
 960
 961         return 0;
 962 }
 963
 964 #define MAX_SPI_SSEL    7
 965
 966 static const u16 ssel[][MAX_SPI_SSEL] = {
 967         {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
 968         P_SPI0_SSEL4, P_SPI0_SSEL5,
 969         P_SPI0_SSEL6, P_SPI0_SSEL7},
 970
 971         {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
 972         P_SPI1_SSEL4, P_SPI1_SSEL5,
 973         P_SPI1_SSEL6, P_SPI1_SSEL7},
 974
 975         {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
 976         P_SPI2_SSEL4, P_SPI2_SSEL5,
 977         P_SPI2_SSEL6, P_SPI2_SSEL7},
 978 };
 979
 980 /* setup for devices (may be called multiple times -- not just first setup) */
 981 static int bfin_spi_setup(struct spi_device *spi)
 982 {
 983         struct bfin5xx_spi_chip *chip_info;
 984         struct bfin_spi_slave_data *chip = NULL;
 985         struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
 986         u16 bfin_ctl_reg;
 987         int ret = -EINVAL;
 988
 989         /* Only alloc (or use chip_info) on first setup */
 990         chip_info = NULL;
 991         chip = spi_get_ctldata(spi);
 992         if (chip == NULL) {
 993                 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
 994                 if (!chip) {
 995                         dev_err(&spi->dev, "cannot allocate chip data\n");
 996                         ret = -ENOMEM;
 997                         goto error;
 998                 }
 999
1000                 chip->enable_dma = 0;
1001                 chip_info = spi->controller_data;
1002         }
1003
1004         /* Let people set non-standard bits directly */
1005         bfin_ctl_reg = BIT_CTL_OPENDRAIN | BIT_CTL_EMISO |
1006                 BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ;
1007
1008         /* chip_info isn't always needed */
1009         if (chip_info) {
1010                 /* Make sure people stop trying to set fields via ctl_reg
1011                  * when they should actually be using common SPI framework.
1012                  * Currently we let through: WOM EMISO PSSE GM SZ.
1013                  * Not sure if a user actually needs/uses any of these,
1014                  * but let's assume (for now) they do.
1015                  */
1016                 if (chip_info->ctl_reg & ~bfin_ctl_reg) {
1017                         dev_err(&spi->dev,
1018                                 "do not set bits in ctl_reg that the SPI framework manages\n");
1019                         goto error;
1020                 }
1021                 chip->enable_dma = chip_info->enable_dma != 0
1022                     && drv_data->master_info->enable_dma;
1023                 chip->ctl_reg = chip_info->ctl_reg;
1024                 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1025                 chip->idle_tx_val = chip_info->idle_tx_val;
1026                 chip->pio_interrupt = chip_info->pio_interrupt;
1027         } else {
1028                 /* force a default base state */
1029                 chip->ctl_reg &= bfin_ctl_reg;
1030         }
1031
1032         /* translate common spi framework into our register */
1033         if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1034                 dev_err(&spi->dev, "unsupported spi modes detected\n");
1035                 goto error;
1036         }
1037         if (spi->mode & SPI_CPOL)
1038                 chip->ctl_reg |= BIT_CTL_CPOL;
1039         if (spi->mode & SPI_CPHA)
1040                 chip->ctl_reg |= BIT_CTL_CPHA;
1041         if (spi->mode & SPI_LSB_FIRST)
1042                 chip->ctl_reg |= BIT_CTL_LSBF;
1043         /* we dont support running in slave mode (yet?) */
1044         chip->ctl_reg |= BIT_CTL_MASTER;
1045
1046         /*
1047          * Notice: for blackfin, the speed_hz is the value of register
1048          * SPI_BAUD, not the real baudrate
1049          */
1050         chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1051         chip->chip_select_num = spi->chip_select;
1052         if (chip->chip_select_num < MAX_CTRL_CS) {
1053                 if (!(spi->mode & SPI_CPHA))
1054                         dev_warn(&spi->dev,
1055                                 "Warning: SPI CPHA not set: Slave Select not under software control!\n"
1056                                 "See Documentation/blackfin/bfin-spi-notes.txt\n");
1057
1058                 chip->flag = (1 << spi->chip_select) << 8;
1059         } else
1060                 chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS;
1061
1062         if (chip->enable_dma && chip->pio_interrupt) {
1063                 dev_err(&spi->dev,
1064                         "enable_dma is set, do not set pio_interrupt\n");
1065                 goto error;
1066         }
1067         /*
1068          * if any one SPI chip is registered and wants DMA, request the
1069          * DMA channel for it
1070          */
1071         if (chip->enable_dma && !drv_data->dma_requested) {
1072                 /* register dma irq handler */
1073                 ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA");
1074                 if (ret) {
1075                         dev_err(&spi->dev,
1076                                 "Unable to request BlackFin SPI DMA channel\n");
1077                         goto error;
1078                 }
1079                 drv_data->dma_requested = 1;
1080
1081                 ret = set_dma_callback(drv_data->dma_channel,
1082                         bfin_spi_dma_irq_handler, drv_data);
1083                 if (ret) {
1084                         dev_err(&spi->dev, "Unable to set dma callback\n");
1085                         goto error;
1086                 }
1087                 dma_disable_irq(drv_data->dma_channel);
1088         }
1089
1090         if (chip->pio_interrupt && !drv_data->irq_requested) {
1091                 ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
1092                         0, "BFIN_SPI", drv_data);
1093                 if (ret) {
1094                         dev_err(&spi->dev, "Unable to register spi IRQ\n");
1095                         goto error;
1096                 }
1097                 drv_data->irq_requested = 1;
1098                 /* we use write mode, spi irq has to be disabled here */
1099                 disable_irq(drv_data->spi_irq);
1100         }
1101
1102         if (chip->chip_select_num >= MAX_CTRL_CS) {
1103                 /* Only request on first setup */
1104                 if (spi_get_ctldata(spi) == NULL) {
1105                         ret = gpio_request(chip->cs_gpio, spi->modalias);
1106                         if (ret) {
1107                                 dev_err(&spi->dev, "gpio_request() error\n");
1108                                 goto pin_error;
1109                         }
1110                         gpio_direction_output(chip->cs_gpio, 1);
1111                 }
1112         }
1113
1114         dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1115                         spi->modalias, spi->bits_per_word, chip->enable_dma);
1116         dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1117                         chip->ctl_reg, chip->flag);
1118
1119         spi_set_ctldata(spi, chip);
1120
1121         dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1122         if (chip->chip_select_num < MAX_CTRL_CS) {
1123                 ret = peripheral_request(ssel[spi->master->bus_num]
1124                                          [chip->chip_select_num-1], spi->modalias);
1125                 if (ret) {
1126                         dev_err(&spi->dev, "peripheral_request() error\n");
1127                         goto pin_error;
1128                 }
1129         }
1130
1131         bfin_spi_cs_enable(drv_data, chip);
1132         bfin_spi_cs_deactive(drv_data, chip);
1133
1134         return 0;
1135
1136  pin_error:
1137         if (chip->chip_select_num >= MAX_CTRL_CS)
1138                 gpio_free(chip->cs_gpio);
1139         else
1140                 peripheral_free(ssel[spi->master->bus_num]
1141                         [chip->chip_select_num - 1]);
1142  error:
1143         if (chip) {
1144                 if (drv_data->dma_requested)
1145                         free_dma(drv_data->dma_channel);
1146                 drv_data->dma_requested = 0;
1147
1148                 kfree(chip);
1149                 /* prevent free 'chip' twice */
1150                 spi_set_ctldata(spi, NULL);
1151         }
1152
1153         return ret;
1154 }
1155
1156 /*
1157  * callback for spi framework.
1158  * clean driver specific data
1159  */
1160 static void bfin_spi_cleanup(struct spi_device *spi)
1161 {
1162         struct bfin_spi_slave_data *chip = spi_get_ctldata(spi);
1163         struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
1164
1165         if (!chip)
1166                 return;
1167
1168         if (chip->chip_select_num < MAX_CTRL_CS) {
1169                 peripheral_free(ssel[spi->master->bus_num]
1170                                         [chip->chip_select_num-1]);
1171                 bfin_spi_cs_disable(drv_data, chip);
1172         } else
1173                 gpio_free(chip->cs_gpio);
1174
1175         kfree(chip);
1176         /* prevent free 'chip' twice */
1177         spi_set_ctldata(spi, NULL);
1178 }
1179
1180 static int bfin_spi_init_queue(struct bfin_spi_master_data *drv_data)
1181 {
1182         INIT_LIST_HEAD(&drv_data->queue);
1183         spin_lock_init(&drv_data->lock);
1184
1185         drv_data->running = false;
1186         drv_data->busy = 0;
1187
1188         /* init transfer tasklet */
1189         tasklet_init(&drv_data->pump_transfers,
1190                      bfin_spi_pump_transfers, (unsigned long)drv_data);
1191
1192         /* init messages workqueue */
1193         INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1194         drv_data->workqueue = create_singlethread_workqueue(
1195                                 dev_name(drv_data->master->dev.parent));
1196         if (drv_data->workqueue == NULL)
1197                 return -EBUSY;
1198
1199         return 0;
1200 }
1201
1202 static int bfin_spi_start_queue(struct bfin_spi_master_data *drv_data)
1203 {
1204         unsigned long flags;
1205
1206         spin_lock_irqsave(&drv_data->lock, flags);
1207
1208         if (drv_data->running || drv_data->busy) {
1209                 spin_unlock_irqrestore(&drv_data->lock, flags);
1210                 return -EBUSY;
1211         }
1212
1213         drv_data->running = true;
1214         drv_data->cur_msg = NULL;
1215         drv_data->cur_transfer = NULL;
1216         drv_data->cur_chip = NULL;
1217         spin_unlock_irqrestore(&drv_data->lock, flags);
1218
1219         queue_work(drv_data->workqueue, &drv_data->pump_messages);
1220
1221         return 0;
1222 }
1223
1224 static int bfin_spi_stop_queue(struct bfin_spi_master_data *drv_data)
1225 {
1226         unsigned long flags;
1227         unsigned limit = 500;
1228         int status = 0;
1229
1230         spin_lock_irqsave(&drv_data->lock, flags);
1231
1232         /*
1233          * This is a bit lame, but is optimized for the common execution path.
1234          * A wait_queue on the drv_data->busy could be used, but then the common
1235          * execution path (pump_messages) would be required to call wake_up or
1236          * friends on every SPI message. Do this instead
1237          */
1238         drv_data->running = false;
1239         while ((!list_empty(&drv_data->queue) || drv_data->busy) && limit--) {
1240                 spin_unlock_irqrestore(&drv_data->lock, flags);
1241                 msleep(10);
1242                 spin_lock_irqsave(&drv_data->lock, flags);
1243         }
1244
1245         if (!list_empty(&drv_data->queue) || drv_data->busy)
1246                 status = -EBUSY;
1247
1248         spin_unlock_irqrestore(&drv_data->lock, flags);
1249
1250         return status;
1251 }
1252
1253 static int bfin_spi_destroy_queue(struct bfin_spi_master_data *drv_data)
1254 {
1255         int status;
1256
1257         status = bfin_spi_stop_queue(drv_data);
1258         if (status != 0)
1259                 return status;
1260
1261         destroy_workqueue(drv_data->workqueue);
1262
1263         return 0;
1264 }
1265
1266 static int bfin_spi_probe(struct platform_device *pdev)
1267 {
1268         struct device *dev = &pdev->dev;
1269         struct bfin5xx_spi_master *platform_info;
1270         struct spi_master *master;
1271         struct bfin_spi_master_data *drv_data;
1272         struct resource *res;
1273         int status = 0;
1274
1275         platform_info = dev_get_platdata(dev);
1276
1277         /* Allocate master with space for drv_data */
1278         master = spi_alloc_master(dev, sizeof(*drv_data));
1279         if (!master) {
1280                 dev_err(&pdev->dev, "can not alloc spi_master\n");
1281                 return -ENOMEM;
1282         }
1283
1284         drv_data = spi_master_get_devdata(master);
1285         drv_data->master = master;
1286         drv_data->master_info = platform_info;
1287         drv_data->pdev = pdev;
1288         drv_data->pin_req = platform_info->pin_req;
1289
1290         /* the spi->mode bits supported by this driver: */
1291         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1292         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1293         master->bus_num = pdev->id;
1294         master->num_chipselect = platform_info->num_chipselect;
1295         master->cleanup = bfin_spi_cleanup;
1296         master->setup = bfin_spi_setup;
1297         master->transfer = bfin_spi_transfer;
1298
1299         /* Find and map our resources */
1300         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1301         if (res == NULL) {
1302                 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1303                 status = -ENOENT;
1304                 goto out_error_get_res;
1305         }
1306
1307         drv_data->regs = ioremap(res->start, resource_size(res));
1308         if (drv_data->regs == NULL) {
1309                 dev_err(dev, "Cannot map IO\n");
1310                 status = -ENXIO;
1311                 goto out_error_ioremap;
1312         }
1313
1314         res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1315         if (res == NULL) {
1316                 dev_err(dev, "No DMA channel specified\n");
1317                 status = -ENOENT;
1318                 goto out_error_free_io;
1319         }
1320         drv_data->dma_channel = res->start;
1321
1322         drv_data->spi_irq = platform_get_irq(pdev, 0);
1323         if (drv_data->spi_irq < 0) {
1324                 dev_err(dev, "No spi pio irq specified\n");
1325                 status = -ENOENT;
1326                 goto out_error_free_io;
1327         }
1328
1329         /* Initial and start queue */
1330         status = bfin_spi_init_queue(drv_data);
1331         if (status != 0) {
1332                 dev_err(dev, "problem initializing queue\n");
1333                 goto out_error_queue_alloc;
1334         }
1335
1336         status = bfin_spi_start_queue(drv_data);
1337         if (status != 0) {
1338                 dev_err(dev, "problem starting queue\n");
1339                 goto out_error_queue_alloc;
1340         }
1341
1342         status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1343         if (status != 0) {
1344                 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1345                 goto out_error_queue_alloc;
1346         }
1347
1348         /* Reset SPI registers. If these registers were used by the boot loader,
1349          * the sky may fall on your head if you enable the dma controller.
1350          */
1351         bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
1352         bfin_write(&drv_data->regs->flg, 0xFF00);
1353
1354         /* Register with the SPI framework */
1355         platform_set_drvdata(pdev, drv_data);
1356         status = spi_register_master(master);
1357         if (status != 0) {
1358                 dev_err(dev, "problem registering spi master\n");
1359                 goto out_error_queue_alloc;
1360         }
1361
1362         dev_info(dev, "%s, Version %s, regs@%p, dma channel@%d\n",
1363                 DRV_DESC, DRV_VERSION, drv_data->regs,
1364                 drv_data->dma_channel);
1365         return status;
1366
1367 out_error_queue_alloc:
1368         bfin_spi_destroy_queue(drv_data);
1369 out_error_free_io:
1370         iounmap(drv_data->regs);
1371 out_error_ioremap:
1372 out_error_get_res:
1373         spi_master_put(master);
1374
1375         return status;
1376 }
1377
1378 /* stop hardware and remove the driver */
1379 static int bfin_spi_remove(struct platform_device *pdev)
1380 {
1381         struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1382         int status = 0;
1383
1384         if (!drv_data)
1385                 return 0;
1386
1387         /* Remove the queue */
1388         status = bfin_spi_destroy_queue(drv_data);
1389         if (status != 0)
1390                 return status;
1391
1392         /* Disable the SSP at the peripheral and SOC level */
1393         bfin_spi_disable(drv_data);
1394
1395         /* Release DMA */
1396         if (drv_data->master_info->enable_dma) {
1397                 if (dma_channel_active(drv_data->dma_channel))
1398                         free_dma(drv_data->dma_channel);
1399         }
1400
1401         if (drv_data->irq_requested) {
1402                 free_irq(drv_data->spi_irq, drv_data);
1403                 drv_data->irq_requested = 0;
1404         }
1405
1406         /* Disconnect from the SPI framework */
1407         spi_unregister_master(drv_data->master);
1408
1409         peripheral_free_list(drv_data->pin_req);
1410
1411         return 0;
1412 }
1413
1414 #ifdef CONFIG_PM_SLEEP
1415 static int bfin_spi_suspend(struct device *dev)
1416 {
1417         struct bfin_spi_master_data *drv_data = dev_get_drvdata(dev);
1418         int status = 0;
1419
1420         status = bfin_spi_stop_queue(drv_data);
1421         if (status != 0)
1422                 return status;
1423
1424         drv_data->ctrl_reg = bfin_read(&drv_data->regs->ctl);
1425         drv_data->flag_reg = bfin_read(&drv_data->regs->flg);
1426
1427         /*
1428          * reset SPI_CTL and SPI_FLG registers
1429          */
1430         bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
1431         bfin_write(&drv_data->regs->flg, 0xFF00);
1432
1433         return 0;
1434 }
1435
1436 static int bfin_spi_resume(struct device *dev)
1437 {
1438         struct bfin_spi_master_data *drv_data = dev_get_drvdata(dev);
1439         int status = 0;
1440
1441         bfin_write(&drv_data->regs->ctl, drv_data->ctrl_reg);
1442         bfin_write(&drv_data->regs->flg, drv_data->flag_reg);
1443
1444         /* Start the queue running */
1445         status = bfin_spi_start_queue(drv_data);
1446         if (status != 0) {
1447                 dev_err(dev, "problem starting queue (%d)\n", status);
1448                 return status;
1449         }
1450
1451         return 0;
1452 }
1453
1454 static SIMPLE_DEV_PM_OPS(bfin_spi_pm_ops, bfin_spi_suspend, bfin_spi_resume);
1455
1456 #define BFIN_SPI_PM_OPS         (&bfin_spi_pm_ops)
1457 #else
1458 #define BFIN_SPI_PM_OPS         NULL
1459 #endif
1460
1461 MODULE_ALIAS("platform:bfin-spi");
1462 static struct platform_driver bfin_spi_driver = {
1463         .driver = {
1464                 .name   = DRV_NAME,
1465                 .owner  = THIS_MODULE,
1466                 .pm     = BFIN_SPI_PM_OPS,
1467         },
1468         .probe          = bfin_spi_probe,
1469         .remove         = bfin_spi_remove,
1470 };
1471
1472 static int __init bfin_spi_init(void)
1473 {
1474         return platform_driver_register(&bfin_spi_driver);
1475 }
1476 subsys_initcall(bfin_spi_init);
1477
1478 static void __exit bfin_spi_exit(void)
1479 {
1480         platform_driver_unregister(&bfin_spi_driver);
1481 }
1482 module_exit(bfin_spi_exit);