drivers/spi/spi-bcmbca-hsspi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Broadcom BCMBCA High Speed SPI Controller driver
   4  *
   5  * Copyright 2000-2010 Broadcom Corporation
   6  * Copyright 2012-2013 Jonas Gorski <jonas.gorski@gmail.com>
   7  * Copyright 2019-2022 Broadcom Ltd
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/init.h>
  12 #include <linux/io.h>
  13 #include <linux/clk.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/err.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/mutex.h>
  22 #include <linux/of.h>
  23 #include <linux/spi/spi-mem.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #define HSSPI_GLOBAL_CTRL_REG                   0x0
  27 #define GLOBAL_CTRL_CS_POLARITY_SHIFT           0
  28 #define GLOBAL_CTRL_CS_POLARITY_MASK            0x000000ff
  29 #define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT          8
  30 #define GLOBAL_CTRL_PLL_CLK_CTRL_MASK           0x0000ff00
  31 #define GLOBAL_CTRL_CLK_GATE_SSOFF              BIT(16)
  32 #define GLOBAL_CTRL_CLK_POLARITY                BIT(17)
  33 #define GLOBAL_CTRL_MOSI_IDLE                   BIT(18)
  34
  35 #define HSSPI_GLOBAL_EXT_TRIGGER_REG            0x4
  36
  37 #define HSSPI_INT_STATUS_REG                    0x8
  38 #define HSSPI_INT_STATUS_MASKED_REG             0xc
  39 #define HSSPI_INT_MASK_REG                      0x10
  40
  41 #define HSSPI_PINGx_CMD_DONE(i)                 BIT((i * 8) + 0)
  42 #define HSSPI_PINGx_RX_OVER(i)                  BIT((i * 8) + 1)
  43 #define HSSPI_PINGx_TX_UNDER(i)                 BIT((i * 8) + 2)
  44 #define HSSPI_PINGx_POLL_TIMEOUT(i)             BIT((i * 8) + 3)
  45 #define HSSPI_PINGx_CTRL_INVAL(i)               BIT((i * 8) + 4)
  46
  47 #define HSSPI_INT_CLEAR_ALL                     0xff001f1f
  48
  49 #define HSSPI_PINGPONG_COMMAND_REG(x)           (0x80 + (x) * 0x40)
  50 #define PINGPONG_CMD_COMMAND_MASK               0xf
  51 #define PINGPONG_COMMAND_NOOP                   0
  52 #define PINGPONG_COMMAND_START_NOW              1
  53 #define PINGPONG_COMMAND_START_TRIGGER          2
  54 #define PINGPONG_COMMAND_HALT                   3
  55 #define PINGPONG_COMMAND_FLUSH                  4
  56 #define PINGPONG_CMD_PROFILE_SHIFT              8
  57 #define PINGPONG_CMD_SS_SHIFT                   12
  58
  59 #define HSSPI_PINGPONG_STATUS_REG(x)            (0x84 + (x) * 0x40)
  60 #define HSSPI_PINGPONG_STATUS_SRC_BUSY          BIT(1)
  61
  62 #define HSSPI_PROFILE_CLK_CTRL_REG(x)           (0x100 + (x) * 0x20)
  63 #define CLK_CTRL_FREQ_CTRL_MASK                 0x0000ffff
  64 #define CLK_CTRL_SPI_CLK_2X_SEL                 BIT(14)
  65 #define CLK_CTRL_ACCUM_RST_ON_LOOP              BIT(15)
  66 #define CLK_CTRL_CLK_POLARITY                   BIT(16)
  67
  68 #define HSSPI_PROFILE_SIGNAL_CTRL_REG(x)        (0x104 + (x) * 0x20)
  69 #define SIGNAL_CTRL_LATCH_RISING                BIT(12)
  70 #define SIGNAL_CTRL_LAUNCH_RISING               BIT(13)
  71 #define SIGNAL_CTRL_ASYNC_INPUT_PATH            BIT(16)
  72
  73 #define HSSPI_PROFILE_MODE_CTRL_REG(x)          (0x108 + (x) * 0x20)
  74 #define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT       8
  75 #define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT       12
  76 #define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT       16
  77 #define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT       18
  78 #define MODE_CTRL_MODE_3WIRE                    BIT(20)
  79 #define MODE_CTRL_PREPENDBYTE_CNT_SHIFT         24
  80
  81 #define HSSPI_FIFO_REG(x)                       (0x200 + (x) * 0x200)
  82
  83 #define HSSPI_OP_MULTIBIT                       BIT(11)
  84 #define HSSPI_OP_CODE_SHIFT                     13
  85 #define HSSPI_OP_SLEEP                          (0 << HSSPI_OP_CODE_SHIFT)
  86 #define HSSPI_OP_READ_WRITE                     (1 << HSSPI_OP_CODE_SHIFT)
  87 #define HSSPI_OP_WRITE                          (2 << HSSPI_OP_CODE_SHIFT)
  88 #define HSSPI_OP_READ                           (3 << HSSPI_OP_CODE_SHIFT)
  89 #define HSSPI_OP_SETIRQ                         (4 << HSSPI_OP_CODE_SHIFT)
  90
  91 #define HSSPI_BUFFER_LEN                        512
  92 #define HSSPI_OPCODE_LEN                        2
  93
  94 #define HSSPI_MAX_PREPEND_LEN                   15
  95
  96 #define HSSPI_MAX_SYNC_CLOCK                    30000000
  97
  98 #define HSSPI_SPI_MAX_CS                        8
  99 #define HSSPI_BUS_NUM                           1       /* 0 is legacy SPI */
 100 #define HSSPI_POLL_STATUS_TIMEOUT_MS    100
 101
 102 #define HSSPI_WAIT_MODE_POLLING         0
 103 #define HSSPI_WAIT_MODE_INTR            1
 104 #define HSSPI_WAIT_MODE_MAX                     HSSPI_WAIT_MODE_INTR
 105
 106 #define SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT         0
 107 #define SPIM_CTRL_CS_OVERRIDE_SEL_MASK          0xff
 108 #define SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT         8
 109 #define SPIM_CTRL_CS_OVERRIDE_VAL_MASK          0xff
 110
 111 struct bcmbca_hsspi {
 112         struct completion done;
 113         struct mutex bus_mutex;
 114         struct mutex msg_mutex;
 115         struct platform_device *pdev;
 116         struct clk *clk;
 117         struct clk *pll_clk;
 118         void __iomem *regs;
 119         void __iomem *spim_ctrl;
 120         u8 __iomem *fifo;
 121         u32 speed_hz;
 122         u8 cs_polarity;
 123         u32 wait_mode;
 124 };
 125
 126 static ssize_t wait_mode_show(struct device *dev, struct device_attribute *attr,
 127                          char *buf)
 128 {
 129         struct spi_controller *ctrl = dev_get_drvdata(dev);
 130         struct bcmbca_hsspi *bs = spi_controller_get_devdata(ctrl);
 131
 132         return sprintf(buf, "%d\n", bs->wait_mode);
 133 }
 134
 135 static ssize_t wait_mode_store(struct device *dev, struct device_attribute *attr,
 136                           const char *buf, size_t count)
 137 {
 138         struct spi_controller *ctrl = dev_get_drvdata(dev);
 139         struct bcmbca_hsspi *bs = spi_controller_get_devdata(ctrl);
 140         u32 val;
 141
 142         if (kstrtou32(buf, 10, &val))
 143                 return -EINVAL;
 144
 145         if (val > HSSPI_WAIT_MODE_MAX) {
 146                 dev_warn(dev, "invalid wait mode %u\n", val);
 147                 return -EINVAL;
 148         }
 149
 150         mutex_lock(&bs->msg_mutex);
 151         bs->wait_mode = val;
 152         /* clear interrupt status to avoid spurious int on next transfer */
 153         if (val == HSSPI_WAIT_MODE_INTR)
 154                 __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
 155         mutex_unlock(&bs->msg_mutex);
 156
 157         return count;
 158 }
 159
 160 static DEVICE_ATTR_RW(wait_mode);
 161
 162 static struct attribute *bcmbca_hsspi_attrs[] = {
 163         &dev_attr_wait_mode.attr,
 164         NULL,
 165 };
 166
 167 static const struct attribute_group bcmbca_hsspi_group = {
 168         .attrs = bcmbca_hsspi_attrs,
 169 };
 170
 171 static void bcmbca_hsspi_set_cs(struct bcmbca_hsspi *bs, unsigned int cs,
 172                                  bool active)
 173 {
 174         u32 reg;
 175
 176         /* No cs orerriden needed for SS7 internal cs on pcm based voice dev */
 177         if (cs == 7)
 178                 return;
 179
 180         mutex_lock(&bs->bus_mutex);
 181
 182         reg = __raw_readl(bs->spim_ctrl);
 183         if (active)
 184                 reg |= BIT(cs + SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT);
 185         else
 186                 reg &= ~BIT(cs + SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT);
 187
 188         __raw_writel(reg, bs->spim_ctrl);
 189
 190         mutex_unlock(&bs->bus_mutex);
 191 }
 192
 193 static void bcmbca_hsspi_set_clk(struct bcmbca_hsspi *bs,
 194                                   struct spi_device *spi, int hz)
 195 {
 196         unsigned int profile = spi_get_chipselect(spi, 0);
 197         u32 reg;
 198
 199         reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
 200         __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
 201                      bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));
 202
 203         reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
 204         if (hz > HSSPI_MAX_SYNC_CLOCK)
 205                 reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
 206         else
 207                 reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
 208         __raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
 209
 210         mutex_lock(&bs->bus_mutex);
 211         /* setup clock polarity */
 212         reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
 213         reg &= ~GLOBAL_CTRL_CLK_POLARITY;
 214         if (spi->mode & SPI_CPOL)
 215                 reg |= GLOBAL_CTRL_CLK_POLARITY;
 216         __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
 217
 218         mutex_unlock(&bs->bus_mutex);
 219 }
 220
 221 static int bcmbca_hsspi_wait_cmd(struct bcmbca_hsspi *bs, unsigned int cs)
 222 {
 223         unsigned long limit;
 224         u32 reg = 0;
 225         int rc = 0;
 226
 227         if (bs->wait_mode == HSSPI_WAIT_MODE_INTR) {
 228                 if (wait_for_completion_timeout(&bs->done, HZ) == 0)
 229                         rc = 1;
 230         } else {
 231                 limit = jiffies + msecs_to_jiffies(HSSPI_POLL_STATUS_TIMEOUT_MS);
 232
 233                 while (!time_after(jiffies, limit)) {
 234                         reg = __raw_readl(bs->regs + HSSPI_PINGPONG_STATUS_REG(0));
 235                         if (reg & HSSPI_PINGPONG_STATUS_SRC_BUSY)
 236                                 cpu_relax();
 237                         else
 238                                 break;
 239                 }
 240                 if (reg & HSSPI_PINGPONG_STATUS_SRC_BUSY)
 241                         rc = 1;
 242         }
 243
 244         if (rc)
 245                 dev_err(&bs->pdev->dev, "transfer timed out!\n");
 246
 247         return rc;
 248 }
 249
 250 static int bcmbca_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t,
 251                                                                 struct spi_message *msg)
 252 {
 253         struct bcmbca_hsspi *bs = spi_controller_get_devdata(spi->controller);
 254         unsigned int chip_select = spi_get_chipselect(spi, 0);
 255         u16 opcode = 0, val;
 256         int pending = t->len;
 257         int step_size = HSSPI_BUFFER_LEN;
 258         const u8 *tx = t->tx_buf;
 259         u8 *rx = t->rx_buf;
 260         u32 reg = 0, cs_act = 0;
 261
 262         bcmbca_hsspi_set_clk(bs, spi, t->speed_hz);
 263
 264         if (tx && rx)
 265                 opcode = HSSPI_OP_READ_WRITE;
 266         else if (tx)
 267                 opcode = HSSPI_OP_WRITE;
 268         else if (rx)
 269                 opcode = HSSPI_OP_READ;
 270
 271         if (opcode != HSSPI_OP_READ)
 272                 step_size -= HSSPI_OPCODE_LEN;
 273
 274         if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) ||
 275             (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) {
 276                 opcode |= HSSPI_OP_MULTIBIT;
 277
 278                 if (t->rx_nbits == SPI_NBITS_DUAL)
 279                         reg |= 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT;
 280                 if (t->tx_nbits == SPI_NBITS_DUAL)
 281                         reg |= 1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT;
 282         }
 283
 284         __raw_writel(reg | 0xff,
 285                      bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
 286
 287         while (pending > 0) {
 288                 int curr_step = min_t(int, step_size, pending);
 289
 290                 reinit_completion(&bs->done);
 291                 if (tx) {
 292                         memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
 293                         tx += curr_step;
 294                 }
 295
 296                 *(__be16 *)(&val) = cpu_to_be16(opcode | curr_step);
 297                 __raw_writew(val, bs->fifo);
 298
 299                 /* enable interrupt */
 300                 if (bs->wait_mode == HSSPI_WAIT_MODE_INTR)
 301                         __raw_writel(HSSPI_PINGx_CMD_DONE(0),
 302                             bs->regs + HSSPI_INT_MASK_REG);
 303
 304                 if (!cs_act) {
 305                         /* must apply cs signal as close as the cmd starts */
 306                         bcmbca_hsspi_set_cs(bs, chip_select, true);
 307                         cs_act = 1;
 308                 }
 309
 310                 reg = chip_select << PINGPONG_CMD_SS_SHIFT |
 311                             chip_select << PINGPONG_CMD_PROFILE_SHIFT |
 312                             PINGPONG_COMMAND_START_NOW;
 313                 __raw_writel(reg, bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
 314
 315                 if (bcmbca_hsspi_wait_cmd(bs, spi_get_chipselect(spi, 0)))
 316                         return -ETIMEDOUT;
 317
 318                 pending -= curr_step;
 319
 320                 if (rx) {
 321                         memcpy_fromio(rx, bs->fifo, curr_step);
 322                         rx += curr_step;
 323                 }
 324         }
 325
 326         return 0;
 327 }
 328
 329 static int bcmbca_hsspi_setup(struct spi_device *spi)
 330 {
 331         struct bcmbca_hsspi *bs = spi_controller_get_devdata(spi->controller);
 332         u32 reg;
 333
 334         reg = __raw_readl(bs->regs +
 335                           HSSPI_PROFILE_SIGNAL_CTRL_REG(spi_get_chipselect(spi, 0)));
 336         reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
 337         if (spi->mode & SPI_CPHA)
 338                 reg |= SIGNAL_CTRL_LAUNCH_RISING;
 339         else
 340                 reg |= SIGNAL_CTRL_LATCH_RISING;
 341         __raw_writel(reg, bs->regs +
 342                      HSSPI_PROFILE_SIGNAL_CTRL_REG(spi_get_chipselect(spi, 0)));
 343
 344         mutex_lock(&bs->bus_mutex);
 345         reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
 346
 347         if (spi->mode & SPI_CS_HIGH)
 348                 reg |= BIT(spi_get_chipselect(spi, 0));
 349         else
 350                 reg &= ~BIT(spi_get_chipselect(spi, 0));
 351         __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
 352
 353         if (spi->mode & SPI_CS_HIGH)
 354                 bs->cs_polarity |= BIT(spi_get_chipselect(spi, 0));
 355         else
 356                 bs->cs_polarity &= ~BIT(spi_get_chipselect(spi, 0));
 357
 358         reg = __raw_readl(bs->spim_ctrl);
 359         reg &= ~BIT(spi_get_chipselect(spi, 0) + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT);
 360         if (spi->mode & SPI_CS_HIGH)
 361                 reg |= BIT(spi_get_chipselect(spi, 0) + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT);
 362         __raw_writel(reg, bs->spim_ctrl);
 363
 364         mutex_unlock(&bs->bus_mutex);
 365
 366         return 0;
 367 }
 368
 369 static int bcmbca_hsspi_transfer_one(struct spi_controller *host,
 370                                       struct spi_message *msg)
 371 {
 372         struct bcmbca_hsspi *bs = spi_controller_get_devdata(host);
 373         struct spi_transfer *t;
 374         struct spi_device *spi = msg->spi;
 375         int status = -EINVAL;
 376         bool keep_cs = false;
 377
 378         mutex_lock(&bs->msg_mutex);
 379         list_for_each_entry(t, &msg->transfers, transfer_list) {
 380                 status = bcmbca_hsspi_do_txrx(spi, t, msg);
 381                 if (status)
 382                         break;
 383
 384                 spi_transfer_delay_exec(t);
 385
 386                 if (t->cs_change) {
 387                         if (list_is_last(&t->transfer_list,     &msg->transfers)) {
 388                                 keep_cs = true;
 389                         } else {
 390                                 if (!t->cs_off)
 391                                         bcmbca_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), false);
 392
 393                                 spi_transfer_cs_change_delay_exec(msg, t);
 394
 395                                 if (!list_next_entry(t, transfer_list)->cs_off)
 396                                         bcmbca_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), true);
 397                         }
 398                 } else if (!list_is_last(&t->transfer_list, &msg->transfers) &&
 399                            t->cs_off != list_next_entry(t, transfer_list)->cs_off) {
 400                         bcmbca_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), t->cs_off);
 401                 }
 402
 403                 msg->actual_length += t->len;
 404         }
 405
 406         mutex_unlock(&bs->msg_mutex);
 407
 408         if (status || !keep_cs)
 409                 bcmbca_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), false);
 410
 411         msg->status = status;
 412         spi_finalize_current_message(host);
 413
 414         return 0;
 415 }
 416
 417 static irqreturn_t bcmbca_hsspi_interrupt(int irq, void *dev_id)
 418 {
 419         struct bcmbca_hsspi *bs = (struct bcmbca_hsspi *)dev_id;
 420
 421         if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
 422                 return IRQ_NONE;
 423
 424         __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
 425         __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
 426
 427         complete(&bs->done);
 428
 429         return IRQ_HANDLED;
 430 }
 431
 432 static int bcmbca_hsspi_probe(struct platform_device *pdev)
 433 {
 434         struct spi_controller *host;
 435         struct bcmbca_hsspi *bs;
 436         struct resource *res_mem;
 437         void __iomem *spim_ctrl;
 438         void __iomem *regs;
 439         struct device *dev = &pdev->dev;
 440         struct clk *clk, *pll_clk = NULL;
 441         int irq, ret;
 442         u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS;
 443
 444         irq = platform_get_irq(pdev, 0);
 445         if (irq < 0)
 446                 return irq;
 447
 448         res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsspi");
 449         if (!res_mem)
 450                 return -EINVAL;
 451         regs = devm_ioremap_resource(dev, res_mem);
 452         if (IS_ERR(regs))
 453                 return PTR_ERR(regs);
 454
 455         res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spim-ctrl");
 456         if (!res_mem)
 457                 return -EINVAL;
 458         spim_ctrl = devm_ioremap_resource(dev, res_mem);
 459         if (IS_ERR(spim_ctrl))
 460                 return PTR_ERR(spim_ctrl);
 461
 462         clk = devm_clk_get(dev, "hsspi");
 463         if (IS_ERR(clk))
 464                 return PTR_ERR(clk);
 465
 466         ret = clk_prepare_enable(clk);
 467         if (ret)
 468                 return ret;
 469
 470         rate = clk_get_rate(clk);
 471         if (!rate) {
 472                 pll_clk = devm_clk_get(dev, "pll");
 473
 474                 if (IS_ERR(pll_clk)) {
 475                         ret = PTR_ERR(pll_clk);
 476                         goto out_disable_clk;
 477                 }
 478
 479                 ret = clk_prepare_enable(pll_clk);
 480                 if (ret)
 481                         goto out_disable_clk;
 482
 483                 rate = clk_get_rate(pll_clk);
 484                 if (!rate) {
 485                         ret = -EINVAL;
 486                         goto out_disable_pll_clk;
 487                 }
 488         }
 489
 490         host = spi_alloc_host(&pdev->dev, sizeof(*bs));
 491         if (!host) {
 492                 ret = -ENOMEM;
 493                 goto out_disable_pll_clk;
 494         }
 495
 496         bs = spi_controller_get_devdata(host);
 497         bs->pdev = pdev;
 498         bs->clk = clk;
 499         bs->pll_clk = pll_clk;
 500         bs->regs = regs;
 501         bs->spim_ctrl = spim_ctrl;
 502         bs->speed_hz = rate;
 503         bs->fifo = (u8 __iomem *) (bs->regs + HSSPI_FIFO_REG(0));
 504         bs->wait_mode = HSSPI_WAIT_MODE_POLLING;
 505
 506         mutex_init(&bs->bus_mutex);
 507         mutex_init(&bs->msg_mutex);
 508         init_completion(&bs->done);
 509
 510         host->dev.of_node = dev->of_node;
 511         if (!dev->of_node)
 512                 host->bus_num = HSSPI_BUS_NUM;
 513
 514         of_property_read_u32(dev->of_node, "num-cs", &num_cs);
 515         if (num_cs > 8) {
 516                 dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
 517                          num_cs);
 518                 num_cs = HSSPI_SPI_MAX_CS;
 519         }
 520         host->num_chipselect = num_cs;
 521         host->setup = bcmbca_hsspi_setup;
 522         host->transfer_one_message = bcmbca_hsspi_transfer_one;
 523         host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
 524                           SPI_RX_DUAL | SPI_TX_DUAL;
 525         host->bits_per_word_mask = SPI_BPW_MASK(8);
 526         host->auto_runtime_pm = true;
 527
 528         platform_set_drvdata(pdev, host);
 529
 530         /* Initialize the hardware */
 531         __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
 532
 533         /* clean up any pending interrupts */
 534         __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
 535
 536         /* read out default CS polarities */
 537         reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
 538         bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
 539         __raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF,
 540                      bs->regs + HSSPI_GLOBAL_CTRL_REG);
 541
 542         if (irq > 0) {
 543                 ret = devm_request_irq(dev, irq, bcmbca_hsspi_interrupt, IRQF_SHARED,
 544                                pdev->name, bs);
 545                 if (ret)
 546                         goto out_put_host;
 547         }
 548
 549         pm_runtime_enable(&pdev->dev);
 550
 551         ret = sysfs_create_group(&pdev->dev.kobj, &bcmbca_hsspi_group);
 552         if (ret) {
 553                 dev_err(&pdev->dev, "couldn't register sysfs group\n");
 554                 goto out_pm_disable;
 555         }
 556
 557         /* register and we are done */
 558         ret = devm_spi_register_controller(dev, host);
 559         if (ret)
 560                 goto out_sysgroup_disable;
 561
 562         dev_info(dev, "Broadcom BCMBCA High Speed SPI Controller driver");
 563
 564         return 0;
 565
 566 out_sysgroup_disable:
 567         sysfs_remove_group(&pdev->dev.kobj, &bcmbca_hsspi_group);
 568 out_pm_disable:
 569         pm_runtime_disable(&pdev->dev);
 570 out_put_host:
 571         spi_controller_put(host);
 572 out_disable_pll_clk:
 573         clk_disable_unprepare(pll_clk);
 574 out_disable_clk:
 575         clk_disable_unprepare(clk);
 576         return ret;
 577 }
 578
 579 static void bcmbca_hsspi_remove(struct platform_device *pdev)
 580 {
 581         struct spi_controller *host = platform_get_drvdata(pdev);
 582         struct bcmbca_hsspi *bs = spi_controller_get_devdata(host);
 583
 584         /* reset the hardware and block queue progress */
 585         __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
 586         clk_disable_unprepare(bs->pll_clk);
 587         clk_disable_unprepare(bs->clk);
 588         sysfs_remove_group(&pdev->dev.kobj, &bcmbca_hsspi_group);
 589 }
 590
 591 #ifdef CONFIG_PM_SLEEP
 592 static int bcmbca_hsspi_suspend(struct device *dev)
 593 {
 594         struct spi_controller *host = dev_get_drvdata(dev);
 595         struct bcmbca_hsspi *bs = spi_controller_get_devdata(host);
 596
 597         spi_controller_suspend(host);
 598         clk_disable_unprepare(bs->pll_clk);
 599         clk_disable_unprepare(bs->clk);
 600
 601         return 0;
 602 }
 603
 604 static int bcmbca_hsspi_resume(struct device *dev)
 605 {
 606         struct spi_controller *host = dev_get_drvdata(dev);
 607         struct bcmbca_hsspi *bs = spi_controller_get_devdata(host);
 608         int ret;
 609
 610         ret = clk_prepare_enable(bs->clk);
 611         if (ret)
 612                 return ret;
 613
 614         if (bs->pll_clk) {
 615                 ret = clk_prepare_enable(bs->pll_clk);
 616                 if (ret) {
 617                         clk_disable_unprepare(bs->clk);
 618                         return ret;
 619                 }
 620         }
 621
 622         spi_controller_resume(host);
 623
 624         return 0;
 625 }
 626 #endif
 627
 628 static SIMPLE_DEV_PM_OPS(bcmbca_hsspi_pm_ops, bcmbca_hsspi_suspend,
 629                          bcmbca_hsspi_resume);
 630
 631 static const struct of_device_id bcmbca_hsspi_of_match[] = {
 632         { .compatible = "brcm,bcmbca-hsspi-v1.1", },
 633         {},
 634 };
 635
 636 MODULE_DEVICE_TABLE(of, bcmbca_hsspi_of_match);
 637
 638 static struct platform_driver bcmbca_hsspi_driver = {
 639         .driver = {
 640                    .name = "bcmbca-hsspi",
 641                    .pm = &bcmbca_hsspi_pm_ops,
 642                    .of_match_table = bcmbca_hsspi_of_match,
 643                    },
 644         .probe = bcmbca_hsspi_probe,
 645         .remove_new = bcmbca_hsspi_remove,
 646 };
 647
 648 module_platform_driver(bcmbca_hsspi_driver);
 649
 650 MODULE_ALIAS("platform:bcmbca_hsspi");
 651 MODULE_DESCRIPTION("Broadcom BCMBCA High Speed SPI Controller driver");
 652 MODULE_LICENSE("GPL");