drivers/spi/spi-bcm63xx.c

   1 /*
   2  * Broadcom BCM63xx SPI controller support
   3  *
   4  * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
   5  * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the
  19  * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/module.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/delay.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/spi/spi.h>
  30 #include <linux/completion.h>
  31 #include <linux/err.h>
  32 #include <linux/workqueue.h>
  33 #include <linux/pm_runtime.h>
  34
  35 #include <bcm63xx_dev_spi.h>
  36
  37 #define PFX             KBUILD_MODNAME
  38
  39 #define BCM63XX_SPI_MAX_PREPEND         15
  40
  41 struct bcm63xx_spi {
  42         struct completion       done;
  43
  44         void __iomem            *regs;
  45         int                     irq;
  46
  47         /* Platform data */
  48         unsigned                fifo_size;
  49         unsigned int            msg_type_shift;
  50         unsigned int            msg_ctl_width;
  51
  52         /* data iomem */
  53         u8 __iomem              *tx_io;
  54         const u8 __iomem        *rx_io;
  55
  56         struct clk              *clk;
  57         struct platform_device  *pdev;
  58 };
  59
  60 static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
  61                                 unsigned int offset)
  62 {
  63         return bcm_readb(bs->regs + bcm63xx_spireg(offset));
  64 }
  65
  66 static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
  67                                 unsigned int offset)
  68 {
  69         return bcm_readw(bs->regs + bcm63xx_spireg(offset));
  70 }
  71
  72 static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
  73                                   u8 value, unsigned int offset)
  74 {
  75         bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
  76 }
  77
  78 static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
  79                                   u16 value, unsigned int offset)
  80 {
  81         bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
  82 }
  83
  84 static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
  85         { 20000000, SPI_CLK_20MHZ },
  86         { 12500000, SPI_CLK_12_50MHZ },
  87         {  6250000, SPI_CLK_6_250MHZ },
  88         {  3125000, SPI_CLK_3_125MHZ },
  89         {  1563000, SPI_CLK_1_563MHZ },
  90         {   781000, SPI_CLK_0_781MHZ },
  91         {   391000, SPI_CLK_0_391MHZ }
  92 };
  93
  94 static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
  95                                       struct spi_transfer *t)
  96 {
  97         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
  98         u8 clk_cfg, reg;
  99         int i;
 100
 101         /* Find the closest clock configuration */
 102         for (i = 0; i < SPI_CLK_MASK; i++) {
 103                 if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
 104                         clk_cfg = bcm63xx_spi_freq_table[i][1];
 105                         break;
 106                 }
 107         }
 108
 109         /* No matching configuration found, default to lowest */
 110         if (i == SPI_CLK_MASK)
 111                 clk_cfg = SPI_CLK_0_391MHZ;
 112
 113         /* clear existing clock configuration bits of the register */
 114         reg = bcm_spi_readb(bs, SPI_CLK_CFG);
 115         reg &= ~SPI_CLK_MASK;
 116         reg |= clk_cfg;
 117
 118         bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
 119         dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
 120                 clk_cfg, t->speed_hz);
 121 }
 122
 123 /* the spi->mode bits understood by this driver: */
 124 #define MODEBITS (SPI_CPOL | SPI_CPHA)
 125
 126 static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
 127                                 unsigned int num_transfers)
 128 {
 129         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 130         u16 msg_ctl;
 131         u16 cmd;
 132         u8 rx_tail;
 133         unsigned int i, timeout = 0, prepend_len = 0, len = 0;
 134         struct spi_transfer *t = first;
 135         bool do_rx = false;
 136         bool do_tx = false;
 137
 138         /* Disable the CMD_DONE interrupt */
 139         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 140
 141         dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
 142                 t->tx_buf, t->rx_buf, t->len);
 143
 144         if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
 145                 prepend_len = t->len;
 146
 147         /* prepare the buffer */
 148         for (i = 0; i < num_transfers; i++) {
 149                 if (t->tx_buf) {
 150                         do_tx = true;
 151                         memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
 152
 153                         /* don't prepend more than one tx */
 154                         if (t != first)
 155                                 prepend_len = 0;
 156                 }
 157
 158                 if (t->rx_buf) {
 159                         do_rx = true;
 160                         /* prepend is half-duplex write only */
 161                         if (t == first)
 162                                 prepend_len = 0;
 163                 }
 164
 165                 len += t->len;
 166
 167                 t = list_entry(t->transfer_list.next, struct spi_transfer,
 168                                transfer_list);
 169         }
 170
 171         init_completion(&bs->done);
 172
 173         /* Fill in the Message control register */
 174         msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
 175
 176         if (do_rx && do_tx && prepend_len == 0)
 177                 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
 178         else if (do_rx)
 179                 msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
 180         else if (do_tx)
 181                 msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
 182
 183         switch (bs->msg_ctl_width) {
 184         case 8:
 185                 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
 186                 break;
 187         case 16:
 188                 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
 189                 break;
 190         }
 191
 192         /* Issue the transfer */
 193         cmd = SPI_CMD_START_IMMEDIATE;
 194         cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 195         cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
 196         bcm_spi_writew(bs, cmd, SPI_CMD);
 197
 198         /* Enable the CMD_DONE interrupt */
 199         bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
 200
 201         timeout = wait_for_completion_timeout(&bs->done, HZ);
 202         if (!timeout)
 203                 return -ETIMEDOUT;
 204
 205         if (!do_rx)
 206                 return 0;
 207
 208         len = 0;
 209         t = first;
 210         /* Read out all the data */
 211         for (i = 0; i < num_transfers; i++) {
 212                 if (t->rx_buf)
 213                         memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
 214
 215                 if (t != first || prepend_len == 0)
 216                         len += t->len;
 217
 218                 t = list_entry(t->transfer_list.next, struct spi_transfer,
 219                                transfer_list);
 220         }
 221
 222         return 0;
 223 }
 224
 225 static int bcm63xx_spi_transfer_one(struct spi_master *master,
 226                                         struct spi_message *m)
 227 {
 228         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 229         struct spi_transfer *t, *first = NULL;
 230         struct spi_device *spi = m->spi;
 231         int status = 0;
 232         unsigned int n_transfers = 0, total_len = 0;
 233         bool can_use_prepend = false;
 234
 235         /*
 236          * This SPI controller does not support keeping CS active after a
 237          * transfer.
 238          * Work around this by merging as many transfers we can into one big
 239          * full-duplex transfers.
 240          */
 241         list_for_each_entry(t, &m->transfers, transfer_list) {
 242                 if (!first)
 243                         first = t;
 244
 245                 n_transfers++;
 246                 total_len += t->len;
 247
 248                 if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
 249                     first->len <= BCM63XX_SPI_MAX_PREPEND)
 250                         can_use_prepend = true;
 251                 else if (can_use_prepend && t->tx_buf)
 252                         can_use_prepend = false;
 253
 254                 /* we can only transfer one fifo worth of data */
 255                 if ((can_use_prepend &&
 256                      total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
 257                     (!can_use_prepend && total_len > bs->fifo_size)) {
 258                         dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
 259                                 total_len, bs->fifo_size);
 260                         status = -EINVAL;
 261                         goto exit;
 262                 }
 263
 264                 /* all combined transfers have to have the same speed */
 265                 if (t->speed_hz != first->speed_hz) {
 266                         dev_err(&spi->dev, "unable to change speed between transfers\n");
 267                         status = -EINVAL;
 268                         goto exit;
 269                 }
 270
 271                 /* CS will be deasserted directly after transfer */
 272                 if (t->delay_usecs) {
 273                         dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
 274                         status = -EINVAL;
 275                         goto exit;
 276                 }
 277
 278                 if (t->cs_change ||
 279                     list_is_last(&t->transfer_list, &m->transfers)) {
 280                         /* configure adapter for a new transfer */
 281                         bcm63xx_spi_setup_transfer(spi, first);
 282
 283                         /* send the data */
 284                         status = bcm63xx_txrx_bufs(spi, first, n_transfers);
 285                         if (status)
 286                                 goto exit;
 287
 288                         m->actual_length += total_len;
 289
 290                         first = NULL;
 291                         n_transfers = 0;
 292                         total_len = 0;
 293                         can_use_prepend = false;
 294                 }
 295         }
 296 exit:
 297         m->status = status;
 298         spi_finalize_current_message(master);
 299
 300         return 0;
 301 }
 302
 303 /* This driver supports single master mode only. Hence
 304  * CMD_DONE is the only interrupt we care about
 305  */
 306 static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
 307 {
 308         struct spi_master *master = (struct spi_master *)dev_id;
 309         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 310         u8 intr;
 311
 312         /* Read interupts and clear them immediately */
 313         intr = bcm_spi_readb(bs, SPI_INT_STATUS);
 314         bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 315         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 316
 317         /* A transfer completed */
 318         if (intr & SPI_INTR_CMD_DONE)
 319                 complete(&bs->done);
 320
 321         return IRQ_HANDLED;
 322 }
 323
 324
 325 static int bcm63xx_spi_probe(struct platform_device *pdev)
 326 {
 327         struct resource *r;
 328         struct device *dev = &pdev->dev;
 329         struct bcm63xx_spi_pdata *pdata = dev_get_platdata(&pdev->dev);
 330         int irq;
 331         struct spi_master *master;
 332         struct clk *clk;
 333         struct bcm63xx_spi *bs;
 334         int ret;
 335
 336         irq = platform_get_irq(pdev, 0);
 337         if (irq < 0) {
 338                 dev_err(dev, "no irq\n");
 339                 return -ENXIO;
 340         }
 341
 342         clk = devm_clk_get(dev, "spi");
 343         if (IS_ERR(clk)) {
 344                 dev_err(dev, "no clock for device\n");
 345                 return PTR_ERR(clk);
 346         }
 347
 348         master = spi_alloc_master(dev, sizeof(*bs));
 349         if (!master) {
 350                 dev_err(dev, "out of memory\n");
 351                 return -ENOMEM;
 352         }
 353
 354         bs = spi_master_get_devdata(master);
 355
 356         platform_set_drvdata(pdev, master);
 357         bs->pdev = pdev;
 358
 359         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 360         bs->regs = devm_ioremap_resource(&pdev->dev, r);
 361         if (IS_ERR(bs->regs)) {
 362                 ret = PTR_ERR(bs->regs);
 363                 goto out_err;
 364         }
 365
 366         bs->irq = irq;
 367         bs->clk = clk;
 368         bs->fifo_size = pdata->fifo_size;
 369
 370         ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
 371                                                         pdev->name, master);
 372         if (ret) {
 373                 dev_err(dev, "unable to request irq\n");
 374                 goto out_err;
 375         }
 376
 377         master->bus_num = pdata->bus_num;
 378         master->num_chipselect = pdata->num_chipselect;
 379         master->transfer_one_message = bcm63xx_spi_transfer_one;
 380         master->mode_bits = MODEBITS;
 381         master->bits_per_word_mask = SPI_BPW_MASK(8);
 382         master->auto_runtime_pm = true;
 383         bs->msg_type_shift = pdata->msg_type_shift;
 384         bs->msg_ctl_width = pdata->msg_ctl_width;
 385         bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
 386         bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
 387
 388         switch (bs->msg_ctl_width) {
 389         case 8:
 390         case 16:
 391                 break;
 392         default:
 393                 dev_err(dev, "unsupported MSG_CTL width: %d\n",
 394                          bs->msg_ctl_width);
 395                 goto out_err;
 396         }
 397
 398         /* Initialize hardware */
 399         ret = clk_prepare_enable(bs->clk);
 400         if (ret)
 401                 goto out_err;
 402
 403         bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 404
 405         /* register and we are done */
 406         ret = devm_spi_register_master(dev, master);
 407         if (ret) {
 408                 dev_err(dev, "spi register failed\n");
 409                 goto out_clk_disable;
 410         }
 411
 412         dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
 413                  r->start, irq, bs->fifo_size);
 414
 415         return 0;
 416
 417 out_clk_disable:
 418         clk_disable_unprepare(clk);
 419 out_err:
 420         spi_master_put(master);
 421         return ret;
 422 }
 423
 424 static int bcm63xx_spi_remove(struct platform_device *pdev)
 425 {
 426         struct spi_master *master = platform_get_drvdata(pdev);
 427         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 428
 429         /* reset spi block */
 430         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 431
 432         /* HW shutdown */
 433         clk_disable_unprepare(bs->clk);
 434
 435         return 0;
 436 }
 437
 438 #ifdef CONFIG_PM_SLEEP
 439 static int bcm63xx_spi_suspend(struct device *dev)
 440 {
 441         struct spi_master *master = dev_get_drvdata(dev);
 442         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 443
 444         spi_master_suspend(master);
 445
 446         clk_disable_unprepare(bs->clk);
 447
 448         return 0;
 449 }
 450
 451 static int bcm63xx_spi_resume(struct device *dev)
 452 {
 453         struct spi_master *master = dev_get_drvdata(dev);
 454         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 455         int ret;
 456
 457         ret = clk_prepare_enable(bs->clk);
 458         if (ret)
 459                 return ret;
 460
 461         spi_master_resume(master);
 462
 463         return 0;
 464 }
 465 #endif
 466
 467 static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
 468         SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
 469 };
 470
 471 static struct platform_driver bcm63xx_spi_driver = {
 472         .driver = {
 473                 .name   = "bcm63xx-spi",
 474                 .owner  = THIS_MODULE,
 475                 .pm     = &bcm63xx_spi_pm_ops,
 476         },
 477         .probe          = bcm63xx_spi_probe,
 478         .remove         = bcm63xx_spi_remove,
 479 };
 480
 481 module_platform_driver(bcm63xx_spi_driver);
 482
 483 MODULE_ALIAS("platform:bcm63xx_spi");
 484 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
 485 MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
 486 MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
 487 MODULE_LICENSE("GPL");