drivers/spi/spi-bcm63xx-hsspi.c

   1 /*
   2  * Broadcom BCM63XX High Speed SPI Controller driver
   3  *
   4  * Copyright 2000-2010 Broadcom Corporation
   5  * Copyright 2012-2013 Jonas Gorski <jonas.gorski@gmail.com>
   6  *
   7  * Licensed under the GNU/GPL. See COPYING for details.
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/init.h>
  12 #include <linux/io.h>
  13 #include <linux/clk.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/err.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/mutex.h>
  22 #include <linux/of.h>
  23 #include <linux/spi/spi-mem.h>
  24 #include <linux/mtd/spi-nor.h>
  25 #include <linux/reset.h>
  26 #include <linux/pm_runtime.h>
  27
  28 #define HSSPI_GLOBAL_CTRL_REG                   0x0
  29 #define GLOBAL_CTRL_CS_POLARITY_SHIFT           0
  30 #define GLOBAL_CTRL_CS_POLARITY_MASK            0x000000ff
  31 #define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT          8
  32 #define GLOBAL_CTRL_PLL_CLK_CTRL_MASK           0x0000ff00
  33 #define GLOBAL_CTRL_CLK_GATE_SSOFF              BIT(16)
  34 #define GLOBAL_CTRL_CLK_POLARITY                BIT(17)
  35 #define GLOBAL_CTRL_MOSI_IDLE                   BIT(18)
  36
  37 #define HSSPI_GLOBAL_EXT_TRIGGER_REG            0x4
  38
  39 #define HSSPI_INT_STATUS_REG                    0x8
  40 #define HSSPI_INT_STATUS_MASKED_REG             0xc
  41 #define HSSPI_INT_MASK_REG                      0x10
  42
  43 #define HSSPI_PINGx_CMD_DONE(i)                 BIT((i * 8) + 0)
  44 #define HSSPI_PINGx_RX_OVER(i)                  BIT((i * 8) + 1)
  45 #define HSSPI_PINGx_TX_UNDER(i)                 BIT((i * 8) + 2)
  46 #define HSSPI_PINGx_POLL_TIMEOUT(i)             BIT((i * 8) + 3)
  47 #define HSSPI_PINGx_CTRL_INVAL(i)               BIT((i * 8) + 4)
  48
  49 #define HSSPI_INT_CLEAR_ALL                     0xff001f1f
  50
  51 #define HSSPI_PINGPONG_COMMAND_REG(x)           (0x80 + (x) * 0x40)
  52 #define PINGPONG_CMD_COMMAND_MASK               0xf
  53 #define PINGPONG_COMMAND_NOOP                   0
  54 #define PINGPONG_COMMAND_START_NOW              1
  55 #define PINGPONG_COMMAND_START_TRIGGER          2
  56 #define PINGPONG_COMMAND_HALT                   3
  57 #define PINGPONG_COMMAND_FLUSH                  4
  58 #define PINGPONG_CMD_PROFILE_SHIFT              8
  59 #define PINGPONG_CMD_SS_SHIFT                   12
  60
  61 #define HSSPI_PINGPONG_STATUS_REG(x)            (0x84 + (x) * 0x40)
  62 #define HSSPI_PINGPONG_STATUS_SRC_BUSY          BIT(1)
  63
  64 #define HSSPI_PROFILE_CLK_CTRL_REG(x)           (0x100 + (x) * 0x20)
  65 #define CLK_CTRL_FREQ_CTRL_MASK                 0x0000ffff
  66 #define CLK_CTRL_SPI_CLK_2X_SEL                 BIT(14)
  67 #define CLK_CTRL_ACCUM_RST_ON_LOOP              BIT(15)
  68
  69 #define HSSPI_PROFILE_SIGNAL_CTRL_REG(x)        (0x104 + (x) * 0x20)
  70 #define SIGNAL_CTRL_LATCH_RISING                BIT(12)
  71 #define SIGNAL_CTRL_LAUNCH_RISING               BIT(13)
  72 #define SIGNAL_CTRL_ASYNC_INPUT_PATH            BIT(16)
  73
  74 #define HSSPI_PROFILE_MODE_CTRL_REG(x)          (0x108 + (x) * 0x20)
  75 #define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT       8
  76 #define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT       12
  77 #define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT       16
  78 #define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT       18
  79 #define MODE_CTRL_MODE_3WIRE                    BIT(20)
  80 #define MODE_CTRL_PREPENDBYTE_CNT_SHIFT         24
  81
  82 #define HSSPI_FIFO_REG(x)                       (0x200 + (x) * 0x200)
  83
  84
  85 #define HSSPI_OP_MULTIBIT                       BIT(11)
  86 #define HSSPI_OP_CODE_SHIFT                     13
  87 #define HSSPI_OP_SLEEP                          (0 << HSSPI_OP_CODE_SHIFT)
  88 #define HSSPI_OP_READ_WRITE                     (1 << HSSPI_OP_CODE_SHIFT)
  89 #define HSSPI_OP_WRITE                          (2 << HSSPI_OP_CODE_SHIFT)
  90 #define HSSPI_OP_READ                           (3 << HSSPI_OP_CODE_SHIFT)
  91 #define HSSPI_OP_SETIRQ                         (4 << HSSPI_OP_CODE_SHIFT)
  92
  93 #define HSSPI_BUFFER_LEN                        512
  94 #define HSSPI_OPCODE_LEN                        2
  95
  96 #define HSSPI_MAX_PREPEND_LEN                   15
  97
  98 /*
  99  * Some chip require 30MHz but other require 25MHz. Use smaller value to cover
 100  * both cases.
 101  */
 102 #define HSSPI_MAX_SYNC_CLOCK                    25000000
 103
 104 #define HSSPI_SPI_MAX_CS                        8
 105 #define HSSPI_BUS_NUM                           1 /* 0 is legacy SPI */
 106 #define HSSPI_POLL_STATUS_TIMEOUT_MS    100
 107
 108 #define HSSPI_WAIT_MODE_POLLING         0
 109 #define HSSPI_WAIT_MODE_INTR            1
 110 #define HSSPI_WAIT_MODE_MAX                     HSSPI_WAIT_MODE_INTR
 111
 112 /*
 113  * Default transfer mode is auto. If the msg is prependable, use the prepend
 114  * mode.  If not, falls back to use the dummy cs workaround mode but limit the
 115  * clock to 25MHz to make sure it works in all board design.
 116  */
 117 #define HSSPI_XFER_MODE_AUTO            0
 118 #define HSSPI_XFER_MODE_PREPEND         1
 119 #define HSSPI_XFER_MODE_DUMMYCS         2
 120 #define HSSPI_XFER_MODE_MAX                     HSSPI_XFER_MODE_DUMMYCS
 121
 122 #define bcm63xx_prepend_printk_on_checkfail(bs, fmt, ...)       \
 123 do {                                                                            \
 124         if (bs->xfer_mode == HSSPI_XFER_MODE_AUTO)                              \
 125                 dev_dbg(&bs->pdev->dev, fmt, ##__VA_ARGS__);            \
 126         else if (bs->xfer_mode == HSSPI_XFER_MODE_PREPEND)              \
 127                 dev_err(&bs->pdev->dev, fmt, ##__VA_ARGS__);            \
 128 } while (0)
 129
 130 struct bcm63xx_hsspi {
 131         struct completion done;
 132         struct mutex bus_mutex;
 133         struct mutex msg_mutex;
 134         struct platform_device *pdev;
 135         struct clk *clk;
 136         struct clk *pll_clk;
 137         void __iomem *regs;
 138         u8 __iomem *fifo;
 139
 140         u32 speed_hz;
 141         u8 cs_polarity;
 142         u32 wait_mode;
 143         u32 xfer_mode;
 144         u32 prepend_cnt;
 145         u8 *prepend_buf;
 146 };
 147
 148 static ssize_t wait_mode_show(struct device *dev, struct device_attribute *attr,
 149                          char *buf)
 150 {
 151         struct spi_controller *ctrl = dev_get_drvdata(dev);
 152         struct bcm63xx_hsspi *bs = spi_controller_get_devdata(ctrl);
 153
 154         return sprintf(buf, "%d\n", bs->wait_mode);
 155 }
 156
 157 static ssize_t wait_mode_store(struct device *dev, struct device_attribute *attr,
 158                           const char *buf, size_t count)
 159 {
 160         struct spi_controller *ctrl = dev_get_drvdata(dev);
 161         struct bcm63xx_hsspi *bs = spi_controller_get_devdata(ctrl);
 162         u32 val;
 163
 164         if (kstrtou32(buf, 10, &val))
 165                 return -EINVAL;
 166
 167         if (val > HSSPI_WAIT_MODE_MAX) {
 168                 dev_warn(dev, "invalid wait mode %u\n", val);
 169                 return -EINVAL;
 170         }
 171
 172         mutex_lock(&bs->msg_mutex);
 173         bs->wait_mode = val;
 174         /* clear interrupt status to avoid spurious int on next transfer */
 175         if (val == HSSPI_WAIT_MODE_INTR)
 176                 __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
 177         mutex_unlock(&bs->msg_mutex);
 178
 179         return count;
 180 }
 181
 182 static DEVICE_ATTR_RW(wait_mode);
 183
 184 static ssize_t xfer_mode_show(struct device *dev, struct device_attribute *attr,
 185                          char *buf)
 186 {
 187         struct spi_controller *ctrl = dev_get_drvdata(dev);
 188         struct bcm63xx_hsspi *bs = spi_controller_get_devdata(ctrl);
 189
 190         return sprintf(buf, "%d\n", bs->xfer_mode);
 191 }
 192
 193 static ssize_t xfer_mode_store(struct device *dev, struct device_attribute *attr,
 194                           const char *buf, size_t count)
 195 {
 196         struct spi_controller *ctrl = dev_get_drvdata(dev);
 197         struct bcm63xx_hsspi *bs = spi_controller_get_devdata(ctrl);
 198         u32 val;
 199
 200         if (kstrtou32(buf, 10, &val))
 201                 return -EINVAL;
 202
 203         if (val > HSSPI_XFER_MODE_MAX) {
 204                 dev_warn(dev, "invalid xfer mode %u\n", val);
 205                 return -EINVAL;
 206         }
 207
 208         mutex_lock(&bs->msg_mutex);
 209         bs->xfer_mode = val;
 210         mutex_unlock(&bs->msg_mutex);
 211
 212         return count;
 213 }
 214
 215 static DEVICE_ATTR_RW(xfer_mode);
 216
 217 static struct attribute *bcm63xx_hsspi_attrs[] = {
 218         &dev_attr_wait_mode.attr,
 219         &dev_attr_xfer_mode.attr,
 220         NULL,
 221 };
 222
 223 static const struct attribute_group bcm63xx_hsspi_group = {
 224         .attrs = bcm63xx_hsspi_attrs,
 225 };
 226
 227 static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
 228                                   struct spi_device *spi, int hz);
 229
 230 static size_t bcm63xx_hsspi_max_message_size(struct spi_device *spi)
 231 {
 232         return HSSPI_BUFFER_LEN - HSSPI_OPCODE_LEN;
 233 }
 234
 235 static int bcm63xx_hsspi_wait_cmd(struct bcm63xx_hsspi *bs)
 236 {
 237         unsigned long limit;
 238         u32 reg = 0;
 239         int rc = 0;
 240
 241         if (bs->wait_mode == HSSPI_WAIT_MODE_INTR) {
 242                 if (wait_for_completion_timeout(&bs->done, HZ) == 0)
 243                         rc = 1;
 244         } else {
 245                 /* polling mode checks for status busy bit */
 246                 limit = jiffies + msecs_to_jiffies(HSSPI_POLL_STATUS_TIMEOUT_MS);
 247
 248                 while (!time_after(jiffies, limit)) {
 249                         reg = __raw_readl(bs->regs + HSSPI_PINGPONG_STATUS_REG(0));
 250                         if (reg & HSSPI_PINGPONG_STATUS_SRC_BUSY)
 251                                 cpu_relax();
 252                         else
 253                                 break;
 254                 }
 255                 if (reg & HSSPI_PINGPONG_STATUS_SRC_BUSY)
 256                         rc = 1;
 257         }
 258
 259         if (rc)
 260                 dev_err(&bs->pdev->dev, "transfer timed out!\n");
 261
 262         return rc;
 263 }
 264
 265 static bool bcm63xx_prepare_prepend_transfer(struct spi_controller *host,
 266                                           struct spi_message *msg,
 267                                           struct spi_transfer *t_prepend)
 268 {
 269
 270         struct bcm63xx_hsspi *bs = spi_controller_get_devdata(host);
 271         bool tx_only = false;
 272         struct spi_transfer *t;
 273
 274         /*
 275          * Multiple transfers within a message may be combined into one transfer
 276          * to the controller using its prepend feature. A SPI message is prependable
 277          * only if the following are all true:
 278          *   1. One or more half duplex write transfer in single bit mode
 279          *   2. Optional full duplex read/write at the end
 280          *   3. No delay and cs_change between transfers
 281          */
 282         bs->prepend_cnt = 0;
 283         list_for_each_entry(t, &msg->transfers, transfer_list) {
 284                 if ((spi_delay_to_ns(&t->delay, t) > 0) || t->cs_change) {
 285                         bcm63xx_prepend_printk_on_checkfail(bs,
 286                                  "Delay or cs change not supported in prepend mode!\n");
 287                         return false;
 288                 }
 289
 290                 tx_only = false;
 291                 if (t->tx_buf && !t->rx_buf) {
 292                         tx_only = true;
 293                         if (bs->prepend_cnt + t->len >
 294                                 (HSSPI_BUFFER_LEN - HSSPI_OPCODE_LEN)) {
 295                                 bcm63xx_prepend_printk_on_checkfail(bs,
 296                                          "exceed max buf len, abort prepending transfers!\n");
 297                                 return false;
 298                         }
 299
 300                         if (t->tx_nbits > SPI_NBITS_SINGLE &&
 301                                 !list_is_last(&t->transfer_list, &msg->transfers)) {
 302                                 bcm63xx_prepend_printk_on_checkfail(bs,
 303                                          "multi-bit prepend buf not supported!\n");
 304                                 return false;
 305                         }
 306
 307                         if (t->tx_nbits == SPI_NBITS_SINGLE) {
 308                                 memcpy(bs->prepend_buf + bs->prepend_cnt, t->tx_buf, t->len);
 309                                 bs->prepend_cnt += t->len;
 310                         }
 311                 } else {
 312                         if (!list_is_last(&t->transfer_list, &msg->transfers)) {
 313                                 bcm63xx_prepend_printk_on_checkfail(bs,
 314                                          "rx/tx_rx transfer not supported when it is not last one!\n");
 315                                 return false;
 316                         }
 317                 }
 318
 319                 if (list_is_last(&t->transfer_list, &msg->transfers)) {
 320                         memcpy(t_prepend, t, sizeof(struct spi_transfer));
 321
 322                         if (tx_only && t->tx_nbits == SPI_NBITS_SINGLE) {
 323                                 /*
 324                                  * if the last one is also a single bit tx only transfer, merge
 325                                  * all of them into one single tx transfer
 326                                  */
 327                                 t_prepend->len = bs->prepend_cnt;
 328                                 t_prepend->tx_buf = bs->prepend_buf;
 329                                 bs->prepend_cnt = 0;
 330                         } else {
 331                                 /*
 332                                  * if the last one is not a tx only transfer or dual tx xfer, all
 333                                  * the previous transfers are sent through prepend bytes and
 334                                  * make sure it does not exceed the max prepend len
 335                                  */
 336                                 if (bs->prepend_cnt > HSSPI_MAX_PREPEND_LEN) {
 337                                         bcm63xx_prepend_printk_on_checkfail(bs,
 338                                                 "exceed max prepend len, abort prepending transfers!\n");
 339                                         return false;
 340                                 }
 341                         }
 342                 }
 343         }
 344
 345         return true;
 346 }
 347
 348 static int bcm63xx_hsspi_do_prepend_txrx(struct spi_device *spi,
 349                                          struct spi_transfer *t)
 350 {
 351         struct bcm63xx_hsspi *bs = spi_controller_get_devdata(spi->controller);
 352         unsigned int chip_select = spi_get_chipselect(spi, 0);
 353         u16 opcode = 0, val;
 354         const u8 *tx = t->tx_buf;
 355         u8 *rx = t->rx_buf;
 356         u32 reg = 0;
 357
 358         /*
 359          * shouldn't happen as we set the max_message_size in the probe.
 360          * but check it again in case some driver does not honor the max size
 361          */
 362         if (t->len + bs->prepend_cnt > (HSSPI_BUFFER_LEN - HSSPI_OPCODE_LEN)) {
 363                 dev_warn(&bs->pdev->dev,
 364                          "Prepend message large than fifo size len %d prepend %d\n",
 365                          t->len, bs->prepend_cnt);
 366                 return -EINVAL;
 367         }
 368
 369         bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
 370
 371         if (tx && rx)
 372                 opcode = HSSPI_OP_READ_WRITE;
 373         else if (tx)
 374                 opcode = HSSPI_OP_WRITE;
 375         else if (rx)
 376                 opcode = HSSPI_OP_READ;
 377
 378         if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) ||
 379             (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) {
 380                 opcode |= HSSPI_OP_MULTIBIT;
 381
 382                 if (t->rx_nbits == SPI_NBITS_DUAL) {
 383                         reg |= 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT;
 384                         reg |= bs->prepend_cnt << MODE_CTRL_MULTIDATA_RD_STRT_SHIFT;
 385                 }
 386                 if (t->tx_nbits == SPI_NBITS_DUAL) {
 387                         reg |= 1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT;
 388                         reg |= bs->prepend_cnt << MODE_CTRL_MULTIDATA_WR_STRT_SHIFT;
 389                 }
 390         }
 391
 392         reg |= bs->prepend_cnt << MODE_CTRL_PREPENDBYTE_CNT_SHIFT;
 393         __raw_writel(reg | 0xff,
 394                      bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
 395
 396         reinit_completion(&bs->done);
 397         if (bs->prepend_cnt)
 398                 memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, bs->prepend_buf,
 399                             bs->prepend_cnt);
 400         if (tx)
 401                 memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN + bs->prepend_cnt, tx,
 402                             t->len);
 403
 404         *(__be16 *)(&val) = cpu_to_be16(opcode | t->len);
 405         __raw_writew(val, bs->fifo);
 406         /* enable interrupt */
 407         if (bs->wait_mode == HSSPI_WAIT_MODE_INTR)
 408                 __raw_writel(HSSPI_PINGx_CMD_DONE(0), bs->regs + HSSPI_INT_MASK_REG);
 409
 410         /* start the transfer */
 411         reg = chip_select << PINGPONG_CMD_SS_SHIFT |
 412             chip_select << PINGPONG_CMD_PROFILE_SHIFT |
 413             PINGPONG_COMMAND_START_NOW;
 414         __raw_writel(reg, bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
 415
 416         if (bcm63xx_hsspi_wait_cmd(bs))
 417                 return -ETIMEDOUT;
 418
 419         if (rx)
 420                 memcpy_fromio(rx, bs->fifo, t->len);
 421
 422         return 0;
 423 }
 424
 425 static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs,
 426                                  bool active)
 427 {
 428         u32 reg;
 429
 430         mutex_lock(&bs->bus_mutex);
 431         reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
 432
 433         reg &= ~BIT(cs);
 434         if (active == !(bs->cs_polarity & BIT(cs)))
 435                 reg |= BIT(cs);
 436
 437         __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
 438         mutex_unlock(&bs->bus_mutex);
 439 }
 440
 441 static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
 442                                   struct spi_device *spi, int hz)
 443 {
 444         unsigned int profile = spi_get_chipselect(spi, 0);
 445         u32 reg;
 446
 447         reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
 448         __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
 449                      bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));
 450
 451         reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
 452         if (hz > HSSPI_MAX_SYNC_CLOCK)
 453                 reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
 454         else
 455                 reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
 456         __raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
 457
 458         mutex_lock(&bs->bus_mutex);
 459         /* setup clock polarity */
 460         reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
 461         reg &= ~GLOBAL_CTRL_CLK_POLARITY;
 462         if (spi->mode & SPI_CPOL)
 463                 reg |= GLOBAL_CTRL_CLK_POLARITY;
 464         __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
 465         mutex_unlock(&bs->bus_mutex);
 466 }
 467
 468 static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
 469 {
 470         struct bcm63xx_hsspi *bs = spi_controller_get_devdata(spi->controller);
 471         unsigned int chip_select = spi_get_chipselect(spi, 0);
 472         u16 opcode = 0, val;
 473         int pending = t->len;
 474         int step_size = HSSPI_BUFFER_LEN;
 475         const u8 *tx = t->tx_buf;
 476         u8 *rx = t->rx_buf;
 477         u32 reg = 0;
 478
 479         bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
 480         if (!t->cs_off)
 481                 bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), true);
 482
 483         if (tx && rx)
 484                 opcode = HSSPI_OP_READ_WRITE;
 485         else if (tx)
 486                 opcode = HSSPI_OP_WRITE;
 487         else if (rx)
 488                 opcode = HSSPI_OP_READ;
 489
 490         if (opcode != HSSPI_OP_READ)
 491                 step_size -= HSSPI_OPCODE_LEN;
 492
 493         if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) ||
 494             (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) {
 495                 opcode |= HSSPI_OP_MULTIBIT;
 496
 497                 if (t->rx_nbits == SPI_NBITS_DUAL)
 498                         reg |= 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT;
 499                 if (t->tx_nbits == SPI_NBITS_DUAL)
 500                         reg |= 1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT;
 501         }
 502
 503         __raw_writel(reg | 0xff,
 504                      bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
 505
 506         while (pending > 0) {
 507                 int curr_step = min_t(int, step_size, pending);
 508
 509                 reinit_completion(&bs->done);
 510                 if (tx) {
 511                         memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
 512                         tx += curr_step;
 513                 }
 514
 515                 *(__be16 *)(&val) = cpu_to_be16(opcode | curr_step);
 516                 __raw_writew(val, bs->fifo);
 517
 518                 /* enable interrupt */
 519                 if (bs->wait_mode == HSSPI_WAIT_MODE_INTR)
 520                         __raw_writel(HSSPI_PINGx_CMD_DONE(0),
 521                                      bs->regs + HSSPI_INT_MASK_REG);
 522
 523                 reg =  !chip_select << PINGPONG_CMD_SS_SHIFT |
 524                             chip_select << PINGPONG_CMD_PROFILE_SHIFT |
 525                             PINGPONG_COMMAND_START_NOW;
 526                 __raw_writel(reg, bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
 527
 528                 if (bcm63xx_hsspi_wait_cmd(bs))
 529                         return -ETIMEDOUT;
 530
 531                 if (rx) {
 532                         memcpy_fromio(rx, bs->fifo, curr_step);
 533                         rx += curr_step;
 534                 }
 535
 536                 pending -= curr_step;
 537         }
 538
 539         return 0;
 540 }
 541
 542 static int bcm63xx_hsspi_setup(struct spi_device *spi)
 543 {
 544         struct bcm63xx_hsspi *bs = spi_controller_get_devdata(spi->controller);
 545         u32 reg;
 546
 547         reg = __raw_readl(bs->regs +
 548                           HSSPI_PROFILE_SIGNAL_CTRL_REG(spi_get_chipselect(spi, 0)));
 549         reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
 550         if (spi->mode & SPI_CPHA)
 551                 reg |= SIGNAL_CTRL_LAUNCH_RISING;
 552         else
 553                 reg |= SIGNAL_CTRL_LATCH_RISING;
 554         __raw_writel(reg, bs->regs +
 555                      HSSPI_PROFILE_SIGNAL_CTRL_REG(spi_get_chipselect(spi, 0)));
 556
 557         mutex_lock(&bs->bus_mutex);
 558         reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
 559
 560         /* only change actual polarities if there is no transfer */
 561         if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
 562                 if (spi->mode & SPI_CS_HIGH)
 563                         reg |= BIT(spi_get_chipselect(spi, 0));
 564                 else
 565                         reg &= ~BIT(spi_get_chipselect(spi, 0));
 566                 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
 567         }
 568
 569         if (spi->mode & SPI_CS_HIGH)
 570                 bs->cs_polarity |= BIT(spi_get_chipselect(spi, 0));
 571         else
 572                 bs->cs_polarity &= ~BIT(spi_get_chipselect(spi, 0));
 573
 574         mutex_unlock(&bs->bus_mutex);
 575
 576         return 0;
 577 }
 578
 579 static int bcm63xx_hsspi_do_dummy_cs_txrx(struct spi_device *spi,
 580                                       struct spi_message *msg)
 581 {
 582         struct bcm63xx_hsspi *bs = spi_controller_get_devdata(spi->controller);
 583         int status = -EINVAL;
 584         int dummy_cs;
 585         bool keep_cs = false;
 586         struct spi_transfer *t;
 587
 588         /*
 589          * This controller does not support keeping CS active during idle.
 590          * To work around this, we use the following ugly hack:
 591          *
 592          * a. Invert the target chip select's polarity so it will be active.
 593          * b. Select a "dummy" chip select to use as the hardware target.
 594          * c. Invert the dummy chip select's polarity so it will be inactive
 595          *    during the actual transfers.
 596          * d. Tell the hardware to send to the dummy chip select. Thanks to
 597          *    the multiplexed nature of SPI the actual target will receive
 598          *    the transfer and we see its response.
 599          *
 600          * e. At the end restore the polarities again to their default values.
 601          */
 602
 603         dummy_cs = !spi_get_chipselect(spi, 0);
 604         bcm63xx_hsspi_set_cs(bs, dummy_cs, true);
 605
 606         list_for_each_entry(t, &msg->transfers, transfer_list) {
 607                 /*
 608                  * We are here because one of reasons below:
 609                  * a. Message is not prependable and in default auto xfer mode. This mean
 610                  *    we fallback to dummy cs mode at maximum 25MHz safe clock rate.
 611                  * b. User set to use the dummy cs mode.
 612                  */
 613                 if (bs->xfer_mode == HSSPI_XFER_MODE_AUTO) {
 614                         if (t->speed_hz > HSSPI_MAX_SYNC_CLOCK) {
 615                                 t->speed_hz = HSSPI_MAX_SYNC_CLOCK;
 616                                 dev_warn_once(&bs->pdev->dev,
 617                                         "Force to dummy cs mode. Reduce the speed to %dHz",
 618                                         t->speed_hz);
 619                         }
 620                 }
 621
 622                 status = bcm63xx_hsspi_do_txrx(spi, t);
 623                 if (status)
 624                         break;
 625
 626                 msg->actual_length += t->len;
 627
 628                 spi_transfer_delay_exec(t);
 629
 630                 /* use existing cs change logic from spi_transfer_one_message */
 631                 if (t->cs_change) {
 632                         if (list_is_last(&t->transfer_list, &msg->transfers)) {
 633                                 keep_cs = true;
 634                         } else {
 635                                 if (!t->cs_off)
 636                                         bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), false);
 637
 638                                 spi_transfer_cs_change_delay_exec(msg, t);
 639
 640                                 if (!list_next_entry(t, transfer_list)->cs_off)
 641                                         bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), true);
 642                         }
 643                 } else if (!list_is_last(&t->transfer_list, &msg->transfers) &&
 644                            t->cs_off != list_next_entry(t, transfer_list)->cs_off) {
 645                         bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), t->cs_off);
 646                 }
 647         }
 648
 649         bcm63xx_hsspi_set_cs(bs, dummy_cs, false);
 650         if (status || !keep_cs)
 651                 bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), false);
 652
 653         return status;
 654 }
 655
 656 static int bcm63xx_hsspi_transfer_one(struct spi_controller *host,
 657                                       struct spi_message *msg)
 658 {
 659         struct bcm63xx_hsspi *bs = spi_controller_get_devdata(host);
 660         struct spi_device *spi = msg->spi;
 661         int status = -EINVAL;
 662         bool prependable = false;
 663         struct spi_transfer t_prepend;
 664
 665         mutex_lock(&bs->msg_mutex);
 666
 667         if (bs->xfer_mode != HSSPI_XFER_MODE_DUMMYCS)
 668                 prependable = bcm63xx_prepare_prepend_transfer(host, msg, &t_prepend);
 669
 670         if (prependable) {
 671                 status = bcm63xx_hsspi_do_prepend_txrx(spi, &t_prepend);
 672                 msg->actual_length = (t_prepend.len + bs->prepend_cnt);
 673         } else {
 674                 if (bs->xfer_mode == HSSPI_XFER_MODE_PREPEND) {
 675                         dev_err(&bs->pdev->dev,
 676                                 "User sets prepend mode but msg not prependable! Abort transfer\n");
 677                         status = -EINVAL;
 678                 } else
 679                         status = bcm63xx_hsspi_do_dummy_cs_txrx(spi, msg);
 680         }
 681
 682         mutex_unlock(&bs->msg_mutex);
 683         msg->status = status;
 684         spi_finalize_current_message(host);
 685
 686         return 0;
 687 }
 688
 689 static bool bcm63xx_hsspi_mem_supports_op(struct spi_mem *mem,
 690                             const struct spi_mem_op *op)
 691 {
 692         if (!spi_mem_default_supports_op(mem, op))
 693                 return false;
 694
 695         /* Controller doesn't support spi mem dual io mode */
 696         if ((op->cmd.opcode == SPINOR_OP_READ_1_2_2) ||
 697                 (op->cmd.opcode == SPINOR_OP_READ_1_2_2_4B) ||
 698                 (op->cmd.opcode == SPINOR_OP_READ_1_2_2_DTR) ||
 699                 (op->cmd.opcode == SPINOR_OP_READ_1_2_2_DTR_4B))
 700                 return false;
 701
 702         return true;
 703 }
 704
 705 static const struct spi_controller_mem_ops bcm63xx_hsspi_mem_ops = {
 706         .supports_op = bcm63xx_hsspi_mem_supports_op,
 707 };
 708
 709 static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
 710 {
 711         struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id;
 712
 713         if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
 714                 return IRQ_NONE;
 715
 716         __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
 717         __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
 718
 719         complete(&bs->done);
 720
 721         return IRQ_HANDLED;
 722 }
 723
 724 static int bcm63xx_hsspi_probe(struct platform_device *pdev)
 725 {
 726         struct spi_controller *host;
 727         struct bcm63xx_hsspi *bs;
 728         void __iomem *regs;
 729         struct device *dev = &pdev->dev;
 730         struct clk *clk, *pll_clk = NULL;
 731         int irq, ret;
 732         u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS;
 733         struct reset_control *reset;
 734
 735         irq = platform_get_irq(pdev, 0);
 736         if (irq < 0)
 737                 return irq;
 738
 739         regs = devm_platform_ioremap_resource(pdev, 0);
 740         if (IS_ERR(regs))
 741                 return PTR_ERR(regs);
 742
 743         clk = devm_clk_get(dev, "hsspi");
 744
 745         if (IS_ERR(clk))
 746                 return PTR_ERR(clk);
 747
 748         reset = devm_reset_control_get_optional_exclusive(dev, NULL);
 749         if (IS_ERR(reset))
 750                 return PTR_ERR(reset);
 751
 752         ret = clk_prepare_enable(clk);
 753         if (ret)
 754                 return ret;
 755
 756         ret = reset_control_reset(reset);
 757         if (ret) {
 758                 dev_err(dev, "unable to reset device: %d\n", ret);
 759                 goto out_disable_clk;
 760         }
 761
 762         rate = clk_get_rate(clk);
 763         if (!rate) {
 764                 pll_clk = devm_clk_get(dev, "pll");
 765
 766                 if (IS_ERR(pll_clk)) {
 767                         ret = PTR_ERR(pll_clk);
 768                         goto out_disable_clk;
 769                 }
 770
 771                 ret = clk_prepare_enable(pll_clk);
 772                 if (ret)
 773                         goto out_disable_clk;
 774
 775                 rate = clk_get_rate(pll_clk);
 776                 if (!rate) {
 777                         ret = -EINVAL;
 778                         goto out_disable_pll_clk;
 779                 }
 780         }
 781
 782         host = spi_alloc_host(&pdev->dev, sizeof(*bs));
 783         if (!host) {
 784                 ret = -ENOMEM;
 785                 goto out_disable_pll_clk;
 786         }
 787
 788         bs = spi_controller_get_devdata(host);
 789         bs->pdev = pdev;
 790         bs->clk = clk;
 791         bs->pll_clk = pll_clk;
 792         bs->regs = regs;
 793         bs->speed_hz = rate;
 794         bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
 795         bs->wait_mode = HSSPI_WAIT_MODE_POLLING;
 796         bs->prepend_buf = devm_kzalloc(dev, HSSPI_BUFFER_LEN, GFP_KERNEL);
 797         if (!bs->prepend_buf) {
 798                 ret = -ENOMEM;
 799                 goto out_put_host;
 800         }
 801
 802         mutex_init(&bs->bus_mutex);
 803         mutex_init(&bs->msg_mutex);
 804         init_completion(&bs->done);
 805
 806         host->mem_ops = &bcm63xx_hsspi_mem_ops;
 807         host->dev.of_node = dev->of_node;
 808         if (!dev->of_node)
 809                 host->bus_num = HSSPI_BUS_NUM;
 810
 811         of_property_read_u32(dev->of_node, "num-cs", &num_cs);
 812         if (num_cs > 8) {
 813                 dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
 814                          num_cs);
 815                 num_cs = HSSPI_SPI_MAX_CS;
 816         }
 817         host->num_chipselect = num_cs;
 818         host->setup = bcm63xx_hsspi_setup;
 819         host->transfer_one_message = bcm63xx_hsspi_transfer_one;
 820         host->max_transfer_size = bcm63xx_hsspi_max_message_size;
 821         host->max_message_size = bcm63xx_hsspi_max_message_size;
 822
 823         host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
 824                             SPI_RX_DUAL | SPI_TX_DUAL;
 825         host->bits_per_word_mask = SPI_BPW_MASK(8);
 826         host->auto_runtime_pm = true;
 827
 828         platform_set_drvdata(pdev, host);
 829
 830         /* Initialize the hardware */
 831         __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
 832
 833         /* clean up any pending interrupts */
 834         __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
 835
 836         /* read out default CS polarities */
 837         reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
 838         bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
 839         __raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF,
 840                      bs->regs + HSSPI_GLOBAL_CTRL_REG);
 841
 842         if (irq > 0) {
 843                 ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
 844                                        pdev->name, bs);
 845
 846                 if (ret)
 847                         goto out_put_host;
 848         }
 849
 850         pm_runtime_enable(&pdev->dev);
 851
 852         ret = sysfs_create_group(&pdev->dev.kobj, &bcm63xx_hsspi_group);
 853         if (ret) {
 854                 dev_err(&pdev->dev, "couldn't register sysfs group\n");
 855                 goto out_pm_disable;
 856         }
 857
 858         /* register and we are done */
 859         ret = devm_spi_register_controller(dev, host);
 860         if (ret)
 861                 goto out_sysgroup_disable;
 862
 863         dev_info(dev, "Broadcom 63XX High Speed SPI Controller driver");
 864
 865         return 0;
 866
 867 out_sysgroup_disable:
 868         sysfs_remove_group(&pdev->dev.kobj, &bcm63xx_hsspi_group);
 869 out_pm_disable:
 870         pm_runtime_disable(&pdev->dev);
 871 out_put_host:
 872         spi_controller_put(host);
 873 out_disable_pll_clk:
 874         clk_disable_unprepare(pll_clk);
 875 out_disable_clk:
 876         clk_disable_unprepare(clk);
 877         return ret;
 878 }
 879
 880
 881 static void bcm63xx_hsspi_remove(struct platform_device *pdev)
 882 {
 883         struct spi_controller *host = platform_get_drvdata(pdev);
 884         struct bcm63xx_hsspi *bs = spi_controller_get_devdata(host);
 885
 886         /* reset the hardware and block queue progress */
 887         __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
 888         clk_disable_unprepare(bs->pll_clk);
 889         clk_disable_unprepare(bs->clk);
 890         sysfs_remove_group(&pdev->dev.kobj, &bcm63xx_hsspi_group);
 891 }
 892
 893 #ifdef CONFIG_PM_SLEEP
 894 static int bcm63xx_hsspi_suspend(struct device *dev)
 895 {
 896         struct spi_controller *host = dev_get_drvdata(dev);
 897         struct bcm63xx_hsspi *bs = spi_controller_get_devdata(host);
 898
 899         spi_controller_suspend(host);
 900         clk_disable_unprepare(bs->pll_clk);
 901         clk_disable_unprepare(bs->clk);
 902
 903         return 0;
 904 }
 905
 906 static int bcm63xx_hsspi_resume(struct device *dev)
 907 {
 908         struct spi_controller *host = dev_get_drvdata(dev);
 909         struct bcm63xx_hsspi *bs = spi_controller_get_devdata(host);
 910         int ret;
 911
 912         ret = clk_prepare_enable(bs->clk);
 913         if (ret)
 914                 return ret;
 915
 916         if (bs->pll_clk) {
 917                 ret = clk_prepare_enable(bs->pll_clk);
 918                 if (ret) {
 919                         clk_disable_unprepare(bs->clk);
 920                         return ret;
 921                 }
 922         }
 923
 924         spi_controller_resume(host);
 925
 926         return 0;
 927 }
 928 #endif
 929
 930 static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend,
 931                          bcm63xx_hsspi_resume);
 932
 933 static const struct of_device_id bcm63xx_hsspi_of_match[] = {
 934         { .compatible = "brcm,bcm6328-hsspi", },
 935         { .compatible = "brcm,bcmbca-hsspi-v1.0", },
 936         { },
 937 };
 938 MODULE_DEVICE_TABLE(of, bcm63xx_hsspi_of_match);
 939
 940 static struct platform_driver bcm63xx_hsspi_driver = {
 941         .driver = {
 942                 .name   = "bcm63xx-hsspi",
 943                 .pm     = &bcm63xx_hsspi_pm_ops,
 944                 .of_match_table = bcm63xx_hsspi_of_match,
 945         },
 946         .probe          = bcm63xx_hsspi_probe,
 947         .remove_new     = bcm63xx_hsspi_remove,
 948 };
 949
 950 module_platform_driver(bcm63xx_hsspi_driver);
 951
 952 MODULE_ALIAS("platform:bcm63xx_hsspi");
 953 MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver");
 954 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
 955 MODULE_LICENSE("GPL");