drivers/spi/spi-bcm-qspi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for Broadcom BRCMSTB, NSP,  NS2, Cygnus SPI Controllers
   4  *
   5  * Copyright 2016 Broadcom
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/device.h>
  11 #include <linux/init.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/ioport.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/slab.h>
  21 #include <linux/spi/spi.h>
  22 #include <linux/spi/spi-mem.h>
  23 #include <linux/sysfs.h>
  24 #include <linux/types.h>
  25 #include "spi-bcm-qspi.h"
  26
  27 #define DRIVER_NAME "bcm_qspi"
  28
  29
  30 /* BSPI register offsets */
  31 #define BSPI_REVISION_ID                        0x000
  32 #define BSPI_SCRATCH                            0x004
  33 #define BSPI_MAST_N_BOOT_CTRL                   0x008
  34 #define BSPI_BUSY_STATUS                        0x00c
  35 #define BSPI_INTR_STATUS                        0x010
  36 #define BSPI_B0_STATUS                          0x014
  37 #define BSPI_B0_CTRL                            0x018
  38 #define BSPI_B1_STATUS                          0x01c
  39 #define BSPI_B1_CTRL                            0x020
  40 #define BSPI_STRAP_OVERRIDE_CTRL                0x024
  41 #define BSPI_FLEX_MODE_ENABLE                   0x028
  42 #define BSPI_BITS_PER_CYCLE                     0x02c
  43 #define BSPI_BITS_PER_PHASE                     0x030
  44 #define BSPI_CMD_AND_MODE_BYTE                  0x034
  45 #define BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038
  46 #define BSPI_BSPI_XOR_VALUE                     0x03c
  47 #define BSPI_BSPI_XOR_ENABLE                    0x040
  48 #define BSPI_BSPI_PIO_MODE_ENABLE               0x044
  49 #define BSPI_BSPI_PIO_IODIR                     0x048
  50 #define BSPI_BSPI_PIO_DATA                      0x04c
  51
  52 /* RAF register offsets */
  53 #define BSPI_RAF_START_ADDR                     0x100
  54 #define BSPI_RAF_NUM_WORDS                      0x104
  55 #define BSPI_RAF_CTRL                           0x108
  56 #define BSPI_RAF_FULLNESS                       0x10c
  57 #define BSPI_RAF_WATERMARK                      0x110
  58 #define BSPI_RAF_STATUS                 0x114
  59 #define BSPI_RAF_READ_DATA                      0x118
  60 #define BSPI_RAF_WORD_CNT                       0x11c
  61 #define BSPI_RAF_CURR_ADDR                      0x120
  62
  63 /* Override mode masks */
  64 #define BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE       BIT(0)
  65 #define BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL      BIT(1)
  66 #define BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE     BIT(2)
  67 #define BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD      BIT(3)
  68 #define BSPI_STRAP_OVERRIDE_CTRL_ENDAIN_MODE    BIT(4)
  69
  70 #define BSPI_ADDRLEN_3BYTES                     3
  71 #define BSPI_ADDRLEN_4BYTES                     4
  72
  73 #define BSPI_RAF_STATUS_FIFO_EMPTY_MASK BIT(1)
  74
  75 #define BSPI_RAF_CTRL_START_MASK                BIT(0)
  76 #define BSPI_RAF_CTRL_CLEAR_MASK                BIT(1)
  77
  78 #define BSPI_BPP_MODE_SELECT_MASK               BIT(8)
  79 #define BSPI_BPP_ADDR_SELECT_MASK               BIT(16)
  80
  81 #define BSPI_READ_LENGTH                        256
  82
  83 /* MSPI register offsets */
  84 #define MSPI_SPCR0_LSB                          0x000
  85 #define MSPI_SPCR0_MSB                          0x004
  86 #define MSPI_SPCR1_LSB                          0x008
  87 #define MSPI_SPCR1_MSB                          0x00c
  88 #define MSPI_NEWQP                              0x010
  89 #define MSPI_ENDQP                              0x014
  90 #define MSPI_SPCR2                              0x018
  91 #define MSPI_MSPI_STATUS                        0x020
  92 #define MSPI_CPTQP                              0x024
  93 #define MSPI_SPCR3                              0x028
  94 #define MSPI_REV                                0x02c
  95 #define MSPI_TXRAM                              0x040
  96 #define MSPI_RXRAM                              0x0c0
  97 #define MSPI_CDRAM                              0x140
  98 #define MSPI_WRITE_LOCK                 0x180
  99
 100 #define MSPI_MASTER_BIT                 BIT(7)
 101
 102 #define MSPI_NUM_CDRAM                          16
 103 #define MSPI_CDRAM_CONT_BIT                     BIT(7)
 104 #define MSPI_CDRAM_BITSE_BIT                    BIT(6)
 105 #define MSPI_CDRAM_PCS                          0xf
 106
 107 #define MSPI_SPCR2_SPE                          BIT(6)
 108 #define MSPI_SPCR2_CONT_AFTER_CMD               BIT(7)
 109
 110 #define MSPI_SPCR3_FASTBR                       BIT(0)
 111 #define MSPI_SPCR3_FASTDT                       BIT(1)
 112 #define MSPI_SPCR3_SYSCLKSEL_MASK               GENMASK(11, 10)
 113 #define MSPI_SPCR3_SYSCLKSEL_27                 (MSPI_SPCR3_SYSCLKSEL_MASK & \
 114                                                  ~(BIT(10) | BIT(11)))
 115 #define MSPI_SPCR3_SYSCLKSEL_108                (MSPI_SPCR3_SYSCLKSEL_MASK & \
 116                                                  BIT(11))
 117
 118 #define MSPI_MSPI_STATUS_SPIF                   BIT(0)
 119
 120 #define INTR_BASE_BIT_SHIFT                     0x02
 121 #define INTR_COUNT                              0x07
 122
 123 #define NUM_CHIPSELECT                          4
 124 #define QSPI_SPBR_MAX                           255U
 125 #define MSPI_BASE_FREQ                          27000000UL
 126
 127 #define OPCODE_DIOR                             0xBB
 128 #define OPCODE_QIOR                             0xEB
 129 #define OPCODE_DIOR_4B                          0xBC
 130 #define OPCODE_QIOR_4B                          0xEC
 131
 132 #define MAX_CMD_SIZE                            6
 133
 134 #define ADDR_4MB_MASK                           GENMASK(22, 0)
 135
 136 /* stop at end of transfer, no other reason */
 137 #define TRANS_STATUS_BREAK_NONE         0
 138 /* stop at end of spi_message */
 139 #define TRANS_STATUS_BREAK_EOM                  1
 140 /* stop at end of spi_transfer if delay */
 141 #define TRANS_STATUS_BREAK_DELAY                2
 142 /* stop at end of spi_transfer if cs_change */
 143 #define TRANS_STATUS_BREAK_CS_CHANGE            4
 144 /* stop if we run out of bytes */
 145 #define TRANS_STATUS_BREAK_NO_BYTES             8
 146
 147 /* events that make us stop filling TX slots */
 148 #define TRANS_STATUS_BREAK_TX (TRANS_STATUS_BREAK_EOM |         \
 149                                TRANS_STATUS_BREAK_DELAY |               \
 150                                TRANS_STATUS_BREAK_CS_CHANGE)
 151
 152 /* events that make us deassert CS */
 153 #define TRANS_STATUS_BREAK_DESELECT (TRANS_STATUS_BREAK_EOM |           \
 154                                      TRANS_STATUS_BREAK_CS_CHANGE)
 155
 156 struct bcm_qspi_parms {
 157         u32 speed_hz;
 158         u8 mode;
 159         u8 bits_per_word;
 160 };
 161
 162 struct bcm_xfer_mode {
 163         bool flex_mode;
 164         unsigned int width;
 165         unsigned int addrlen;
 166         unsigned int hp;
 167 };
 168
 169 enum base_type {
 170         MSPI,
 171         BSPI,
 172         CHIP_SELECT,
 173         BASEMAX,
 174 };
 175
 176 enum irq_source {
 177         SINGLE_L2,
 178         MUXED_L1,
 179 };
 180
 181 struct bcm_qspi_irq {
 182         const char *irq_name;
 183         const irq_handler_t irq_handler;
 184         int irq_source;
 185         u32 mask;
 186 };
 187
 188 struct bcm_qspi_dev_id {
 189         const struct bcm_qspi_irq *irqp;
 190         void *dev;
 191 };
 192
 193
 194 struct qspi_trans {
 195         struct spi_transfer *trans;
 196         int byte;
 197         bool mspi_last_trans;
 198 };
 199
 200 struct bcm_qspi {
 201         struct platform_device *pdev;
 202         struct spi_master *master;
 203         struct clk *clk;
 204         u32 base_clk;
 205         u32 max_speed_hz;
 206         void __iomem *base[BASEMAX];
 207
 208         /* Some SoCs provide custom interrupt status register(s) */
 209         struct bcm_qspi_soc_intc        *soc_intc;
 210
 211         struct bcm_qspi_parms last_parms;
 212         struct qspi_trans  trans_pos;
 213         int curr_cs;
 214         int bspi_maj_rev;
 215         int bspi_min_rev;
 216         int bspi_enabled;
 217         const struct spi_mem_op *bspi_rf_op;
 218         u32 bspi_rf_op_idx;
 219         u32 bspi_rf_op_len;
 220         u32 bspi_rf_op_status;
 221         struct bcm_xfer_mode xfer_mode;
 222         u32 s3_strap_override_ctrl;
 223         bool bspi_mode;
 224         bool big_endian;
 225         int num_irqs;
 226         struct bcm_qspi_dev_id *dev_ids;
 227         struct completion mspi_done;
 228         struct completion bspi_done;
 229         u8 mspi_maj_rev;
 230         u8 mspi_min_rev;
 231         bool mspi_spcr3_sysclk;
 232 };
 233
 234 static inline bool has_bspi(struct bcm_qspi *qspi)
 235 {
 236         return qspi->bspi_mode;
 237 }
 238
 239 /* hardware supports spcr3 and fast baud-rate  */
 240 static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi)
 241 {
 242         if (!has_bspi(qspi) &&
 243             ((qspi->mspi_maj_rev >= 1) &&
 244              (qspi->mspi_min_rev >= 5)))
 245                 return true;
 246
 247         return false;
 248 }
 249
 250 /* hardware supports sys clk 108Mhz  */
 251 static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi)
 252 {
 253         if (!has_bspi(qspi) && (qspi->mspi_spcr3_sysclk ||
 254             ((qspi->mspi_maj_rev >= 1) &&
 255              (qspi->mspi_min_rev >= 6))))
 256                 return true;
 257
 258         return false;
 259 }
 260
 261 static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi)
 262 {
 263         if (bcm_qspi_has_fastbr(qspi))
 264                 return 1;
 265         else
 266                 return 8;
 267 }
 268
 269 /* Read qspi controller register*/
 270 static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,
 271                                 unsigned int offset)
 272 {
 273         return bcm_qspi_readl(qspi->big_endian, qspi->base[type] + offset);
 274 }
 275
 276 /* Write qspi controller register*/
 277 static inline void bcm_qspi_write(struct bcm_qspi *qspi, enum base_type type,
 278                                   unsigned int offset, unsigned int data)
 279 {
 280         bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset);
 281 }
 282
 283 /* BSPI helpers */
 284 static int bcm_qspi_bspi_busy_poll(struct bcm_qspi *qspi)
 285 {
 286         int i;
 287
 288         /* this should normally finish within 10us */
 289         for (i = 0; i < 1000; i++) {
 290                 if (!(bcm_qspi_read(qspi, BSPI, BSPI_BUSY_STATUS) & 1))
 291                         return 0;
 292                 udelay(1);
 293         }
 294         dev_warn(&qspi->pdev->dev, "timeout waiting for !busy_status\n");
 295         return -EIO;
 296 }
 297
 298 static inline bool bcm_qspi_bspi_ver_three(struct bcm_qspi *qspi)
 299 {
 300         if (qspi->bspi_maj_rev < 4)
 301                 return true;
 302         return false;
 303 }
 304
 305 static void bcm_qspi_bspi_flush_prefetch_buffers(struct bcm_qspi *qspi)
 306 {
 307         bcm_qspi_bspi_busy_poll(qspi);
 308         /* Force rising edge for the b0/b1 'flush' field */
 309         bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 1);
 310         bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 1);
 311         bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
 312         bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
 313 }
 314
 315 static int bcm_qspi_bspi_lr_is_fifo_empty(struct bcm_qspi *qspi)
 316 {
 317         return (bcm_qspi_read(qspi, BSPI, BSPI_RAF_STATUS) &
 318                                 BSPI_RAF_STATUS_FIFO_EMPTY_MASK);
 319 }
 320
 321 static inline u32 bcm_qspi_bspi_lr_read_fifo(struct bcm_qspi *qspi)
 322 {
 323         u32 data = bcm_qspi_read(qspi, BSPI, BSPI_RAF_READ_DATA);
 324
 325         /* BSPI v3 LR is LE only, convert data to host endianness */
 326         if (bcm_qspi_bspi_ver_three(qspi))
 327                 data = le32_to_cpu(data);
 328
 329         return data;
 330 }
 331
 332 static inline void bcm_qspi_bspi_lr_start(struct bcm_qspi *qspi)
 333 {
 334         bcm_qspi_bspi_busy_poll(qspi);
 335         bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
 336                        BSPI_RAF_CTRL_START_MASK);
 337 }
 338
 339 static inline void bcm_qspi_bspi_lr_clear(struct bcm_qspi *qspi)
 340 {
 341         bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
 342                        BSPI_RAF_CTRL_CLEAR_MASK);
 343         bcm_qspi_bspi_flush_prefetch_buffers(qspi);
 344 }
 345
 346 static void bcm_qspi_bspi_lr_data_read(struct bcm_qspi *qspi)
 347 {
 348         u32 *buf = (u32 *)qspi->bspi_rf_op->data.buf.in;
 349         u32 data = 0;
 350
 351         dev_dbg(&qspi->pdev->dev, "xfer %p rx %p rxlen %d\n", qspi->bspi_rf_op,
 352                 qspi->bspi_rf_op->data.buf.in, qspi->bspi_rf_op_len);
 353         while (!bcm_qspi_bspi_lr_is_fifo_empty(qspi)) {
 354                 data = bcm_qspi_bspi_lr_read_fifo(qspi);
 355                 if (likely(qspi->bspi_rf_op_len >= 4) &&
 356                     IS_ALIGNED((uintptr_t)buf, 4)) {
 357                         buf[qspi->bspi_rf_op_idx++] = data;
 358                         qspi->bspi_rf_op_len -= 4;
 359                 } else {
 360                         /* Read out remaining bytes, make sure*/
 361                         u8 *cbuf = (u8 *)&buf[qspi->bspi_rf_op_idx];
 362
 363                         data = cpu_to_le32(data);
 364                         while (qspi->bspi_rf_op_len) {
 365                                 *cbuf++ = (u8)data;
 366                                 data >>= 8;
 367                                 qspi->bspi_rf_op_len--;
 368                         }
 369                 }
 370         }
 371 }
 372
 373 static void bcm_qspi_bspi_set_xfer_params(struct bcm_qspi *qspi, u8 cmd_byte,
 374                                           int bpp, int bpc, int flex_mode)
 375 {
 376         bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
 377         bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_CYCLE, bpc);
 378         bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_PHASE, bpp);
 379         bcm_qspi_write(qspi, BSPI, BSPI_CMD_AND_MODE_BYTE, cmd_byte);
 380         bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, flex_mode);
 381 }
 382
 383 static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi,
 384                                        const struct spi_mem_op *op, int hp)
 385 {
 386         int bpc = 0, bpp = 0;
 387         u8 command = op->cmd.opcode;
 388         int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE;
 389         int addrlen = op->addr.nbytes;
 390         int flex_mode = 1;
 391
 392         dev_dbg(&qspi->pdev->dev, "set flex mode w %x addrlen %x hp %d\n",
 393                 width, addrlen, hp);
 394
 395         if (addrlen == BSPI_ADDRLEN_4BYTES)
 396                 bpp = BSPI_BPP_ADDR_SELECT_MASK;
 397
 398         if (op->dummy.nbytes)
 399                 bpp |= (op->dummy.nbytes * 8) / op->dummy.buswidth;
 400
 401         switch (width) {
 402         case SPI_NBITS_SINGLE:
 403                 if (addrlen == BSPI_ADDRLEN_3BYTES)
 404                         /* default mode, does not need flex_cmd */
 405                         flex_mode = 0;
 406                 break;
 407         case SPI_NBITS_DUAL:
 408                 bpc = 0x00000001;
 409                 if (hp) {
 410                         bpc |= 0x00010100; /* address and mode are 2-bit */
 411                         bpp = BSPI_BPP_MODE_SELECT_MASK;
 412                 }
 413                 break;
 414         case SPI_NBITS_QUAD:
 415                 bpc = 0x00000002;
 416                 if (hp) {
 417                         bpc |= 0x00020200; /* address and mode are 4-bit */
 418                         bpp |= BSPI_BPP_MODE_SELECT_MASK;
 419                 }
 420                 break;
 421         default:
 422                 return -EINVAL;
 423         }
 424
 425         bcm_qspi_bspi_set_xfer_params(qspi, command, bpp, bpc, flex_mode);
 426
 427         return 0;
 428 }
 429
 430 static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi,
 431                                       const struct spi_mem_op *op, int hp)
 432 {
 433         int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE;
 434         int addrlen = op->addr.nbytes;
 435         u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
 436
 437         dev_dbg(&qspi->pdev->dev, "set override mode w %x addrlen %x hp %d\n",
 438                 width, addrlen, hp);
 439
 440         switch (width) {
 441         case SPI_NBITS_SINGLE:
 442                 /* clear quad/dual mode */
 443                 data &= ~(BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD |
 444                           BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL);
 445                 break;
 446         case SPI_NBITS_QUAD:
 447                 /* clear dual mode and set quad mode */
 448                 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
 449                 data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
 450                 break;
 451         case SPI_NBITS_DUAL:
 452                 /* clear quad mode set dual mode */
 453                 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
 454                 data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
 455                 break;
 456         default:
 457                 return -EINVAL;
 458         }
 459
 460         if (addrlen == BSPI_ADDRLEN_4BYTES)
 461                 /* set 4byte mode*/
 462                 data |= BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
 463         else
 464                 /* clear 4 byte mode */
 465                 data &= ~BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
 466
 467         /* set the override mode */
 468         data |= BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
 469         bcm_qspi_write(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL, data);
 470         bcm_qspi_bspi_set_xfer_params(qspi, op->cmd.opcode, 0, 0, 0);
 471
 472         return 0;
 473 }
 474
 475 static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi,
 476                                   const struct spi_mem_op *op, int hp)
 477 {
 478         int error = 0;
 479         int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE;
 480         int addrlen = op->addr.nbytes;
 481
 482         /* default mode */
 483         qspi->xfer_mode.flex_mode = true;
 484
 485         if (!bcm_qspi_bspi_ver_three(qspi)) {
 486                 u32 val, mask;
 487
 488                 val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
 489                 mask = BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
 490                 if (val & mask || qspi->s3_strap_override_ctrl & mask) {
 491                         qspi->xfer_mode.flex_mode = false;
 492                         bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
 493                         error = bcm_qspi_bspi_set_override(qspi, op, hp);
 494                 }
 495         }
 496
 497         if (qspi->xfer_mode.flex_mode)
 498                 error = bcm_qspi_bspi_set_flex_mode(qspi, op, hp);
 499
 500         if (error) {
 501                 dev_warn(&qspi->pdev->dev,
 502                          "INVALID COMBINATION: width=%d addrlen=%d hp=%d\n",
 503                          width, addrlen, hp);
 504         } else if (qspi->xfer_mode.width != width ||
 505                    qspi->xfer_mode.addrlen != addrlen ||
 506                    qspi->xfer_mode.hp != hp) {
 507                 qspi->xfer_mode.width = width;
 508                 qspi->xfer_mode.addrlen = addrlen;
 509                 qspi->xfer_mode.hp = hp;
 510                 dev_dbg(&qspi->pdev->dev,
 511                         "cs:%d %d-lane output, %d-byte address%s\n",
 512                         qspi->curr_cs,
 513                         qspi->xfer_mode.width,
 514                         qspi->xfer_mode.addrlen,
 515                         qspi->xfer_mode.hp != -1 ? ", hp mode" : "");
 516         }
 517
 518         return error;
 519 }
 520
 521 static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
 522 {
 523         if (!has_bspi(qspi))
 524                 return;
 525
 526         qspi->bspi_enabled = 1;
 527         if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1) == 0)
 528                 return;
 529
 530         bcm_qspi_bspi_flush_prefetch_buffers(qspi);
 531         udelay(1);
 532         bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 0);
 533         udelay(1);
 534 }
 535
 536 static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
 537 {
 538         if (!has_bspi(qspi))
 539                 return;
 540
 541         qspi->bspi_enabled = 0;
 542         if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1))
 543                 return;
 544
 545         bcm_qspi_bspi_busy_poll(qspi);
 546         bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 1);
 547         udelay(1);
 548 }
 549
 550 static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
 551 {
 552         u32 rd = 0;
 553         u32 wr = 0;
 554
 555         if (cs >= 0 && qspi->base[CHIP_SELECT]) {
 556                 rd = bcm_qspi_read(qspi, CHIP_SELECT, 0);
 557                 wr = (rd & ~0xff) | (1 << cs);
 558                 if (rd == wr)
 559                         return;
 560                 bcm_qspi_write(qspi, CHIP_SELECT, 0, wr);
 561                 usleep_range(10, 20);
 562         }
 563
 564         dev_dbg(&qspi->pdev->dev, "using cs:%d\n", cs);
 565         qspi->curr_cs = cs;
 566 }
 567
 568 /* MSPI helpers */
 569 static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
 570                                   const struct bcm_qspi_parms *xp)
 571 {
 572         u32 spcr, spbr = 0;
 573
 574         if (xp->speed_hz)
 575                 spbr = qspi->base_clk / (2 * xp->speed_hz);
 576
 577         spcr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX);
 578         bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
 579
 580         if (!qspi->mspi_maj_rev)
 581                 /* legacy controller */
 582                 spcr = MSPI_MASTER_BIT;
 583         else
 584                 spcr = 0;
 585
 586         /* for 16 bit the data should be zero */
 587         if (xp->bits_per_word != 16)
 588                 spcr |= xp->bits_per_word << 2;
 589         spcr |= xp->mode & 3;
 590
 591         bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
 592
 593         if (bcm_qspi_has_fastbr(qspi)) {
 594                 spcr = 0;
 595
 596                 /* enable fastbr */
 597                 spcr |= MSPI_SPCR3_FASTBR;
 598
 599                 if (bcm_qspi_has_sysclk_108(qspi)) {
 600                         /* SYSCLK_108 */
 601                         spcr |= MSPI_SPCR3_SYSCLKSEL_108;
 602                         qspi->base_clk = MSPI_BASE_FREQ * 4;
 603                         /* Change spbr as we changed sysclk */
 604                         bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, 4);
 605                 }
 606
 607                 bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr);
 608         }
 609
 610         qspi->last_parms = *xp;
 611 }
 612
 613 static void bcm_qspi_update_parms(struct bcm_qspi *qspi,
 614                                   struct spi_device *spi,
 615                                   struct spi_transfer *trans)
 616 {
 617         struct bcm_qspi_parms xp;
 618
 619         xp.speed_hz = trans->speed_hz;
 620         xp.bits_per_word = trans->bits_per_word;
 621         xp.mode = spi->mode;
 622
 623         bcm_qspi_hw_set_parms(qspi, &xp);
 624 }
 625
 626 static int bcm_qspi_setup(struct spi_device *spi)
 627 {
 628         struct bcm_qspi_parms *xp;
 629
 630         if (spi->bits_per_word > 16)
 631                 return -EINVAL;
 632
 633         xp = spi_get_ctldata(spi);
 634         if (!xp) {
 635                 xp = kzalloc(sizeof(*xp), GFP_KERNEL);
 636                 if (!xp)
 637                         return -ENOMEM;
 638                 spi_set_ctldata(spi, xp);
 639         }
 640         xp->speed_hz = spi->max_speed_hz;
 641         xp->mode = spi->mode;
 642
 643         if (spi->bits_per_word)
 644                 xp->bits_per_word = spi->bits_per_word;
 645         else
 646                 xp->bits_per_word = 8;
 647
 648         return 0;
 649 }
 650
 651 static bool bcm_qspi_mspi_transfer_is_last(struct bcm_qspi *qspi,
 652                                            struct qspi_trans *qt)
 653 {
 654         if (qt->mspi_last_trans &&
 655             spi_transfer_is_last(qspi->master, qt->trans))
 656                 return true;
 657         else
 658                 return false;
 659 }
 660
 661 static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
 662                                         struct qspi_trans *qt, int flags)
 663 {
 664         int ret = TRANS_STATUS_BREAK_NONE;
 665
 666         /* count the last transferred bytes */
 667         if (qt->trans->bits_per_word <= 8)
 668                 qt->byte++;
 669         else
 670                 qt->byte += 2;
 671
 672         if (qt->byte >= qt->trans->len) {
 673                 /* we're at the end of the spi_transfer */
 674                 /* in TX mode, need to pause for a delay or CS change */
 675                 if (qt->trans->delay.value &&
 676                     (flags & TRANS_STATUS_BREAK_DELAY))
 677                         ret |= TRANS_STATUS_BREAK_DELAY;
 678                 if (qt->trans->cs_change &&
 679                     (flags & TRANS_STATUS_BREAK_CS_CHANGE))
 680                         ret |= TRANS_STATUS_BREAK_CS_CHANGE;
 681
 682                 if (bcm_qspi_mspi_transfer_is_last(qspi, qt))
 683                         ret |= TRANS_STATUS_BREAK_EOM;
 684                 else
 685                         ret |= TRANS_STATUS_BREAK_NO_BYTES;
 686
 687                 qt->trans = NULL;
 688         }
 689
 690         dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n",
 691                 qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret);
 692         return ret;
 693 }
 694
 695 static inline u8 read_rxram_slot_u8(struct bcm_qspi *qspi, int slot)
 696 {
 697         u32 slot_offset = MSPI_RXRAM + (slot << 3) + 0x4;
 698
 699         /* mask out reserved bits */
 700         return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;
 701 }
 702
 703 static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot)
 704 {
 705         u32 reg_offset = MSPI_RXRAM;
 706         u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
 707         u32 msb_offset = reg_offset + (slot << 3);
 708
 709         return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |
 710                 ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);
 711 }
 712
 713 static void read_from_hw(struct bcm_qspi *qspi, int slots)
 714 {
 715         struct qspi_trans tp;
 716         int slot;
 717
 718         bcm_qspi_disable_bspi(qspi);
 719
 720         if (slots > MSPI_NUM_CDRAM) {
 721                 /* should never happen */
 722                 dev_err(&qspi->pdev->dev, "%s: too many slots!\n", __func__);
 723                 return;
 724         }
 725
 726         tp = qspi->trans_pos;
 727
 728         for (slot = 0; slot < slots; slot++) {
 729                 if (tp.trans->bits_per_word <= 8) {
 730                         u8 *buf = tp.trans->rx_buf;
 731
 732                         if (buf)
 733                                 buf[tp.byte] = read_rxram_slot_u8(qspi, slot);
 734                         dev_dbg(&qspi->pdev->dev, "RD %02x\n",
 735                                 buf ? buf[tp.byte] : 0x0);
 736                 } else {
 737                         u16 *buf = tp.trans->rx_buf;
 738
 739                         if (buf)
 740                                 buf[tp.byte / 2] = read_rxram_slot_u16(qspi,
 741                                                                       slot);
 742                         dev_dbg(&qspi->pdev->dev, "RD %04x\n",
 743                                 buf ? buf[tp.byte / 2] : 0x0);
 744                 }
 745
 746                 update_qspi_trans_byte_count(qspi, &tp,
 747                                              TRANS_STATUS_BREAK_NONE);
 748         }
 749
 750         qspi->trans_pos = tp;
 751 }
 752
 753 static inline void write_txram_slot_u8(struct bcm_qspi *qspi, int slot,
 754                                        u8 val)
 755 {
 756         u32 reg_offset = MSPI_TXRAM + (slot << 3);
 757
 758         /* mask out reserved bits */
 759         bcm_qspi_write(qspi, MSPI, reg_offset, val);
 760 }
 761
 762 static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot,
 763                                         u16 val)
 764 {
 765         u32 reg_offset = MSPI_TXRAM;
 766         u32 msb_offset = reg_offset + (slot << 3);
 767         u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
 768
 769         bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8));
 770         bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff));
 771 }
 772
 773 static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot)
 774 {
 775         return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));
 776 }
 777
 778 static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val)
 779 {
 780         bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val);
 781 }
 782
 783 /* Return number of slots written */
 784 static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
 785 {
 786         struct qspi_trans tp;
 787         int slot = 0, tstatus = 0;
 788         u32 mspi_cdram = 0;
 789
 790         bcm_qspi_disable_bspi(qspi);
 791         tp = qspi->trans_pos;
 792         bcm_qspi_update_parms(qspi, spi, tp.trans);
 793
 794         /* Run until end of transfer or reached the max data */
 795         while (!tstatus && slot < MSPI_NUM_CDRAM) {
 796                 if (tp.trans->bits_per_word <= 8) {
 797                         const u8 *buf = tp.trans->tx_buf;
 798                         u8 val = buf ? buf[tp.byte] : 0x00;
 799
 800                         write_txram_slot_u8(qspi, slot, val);
 801                         dev_dbg(&qspi->pdev->dev, "WR %02x\n", val);
 802                 } else {
 803                         const u16 *buf = tp.trans->tx_buf;
 804                         u16 val = buf ? buf[tp.byte / 2] : 0x0000;
 805
 806                         write_txram_slot_u16(qspi, slot, val);
 807                         dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
 808                 }
 809                 mspi_cdram = MSPI_CDRAM_CONT_BIT;
 810
 811                 if (has_bspi(qspi))
 812                         mspi_cdram &= ~1;
 813                 else
 814                         mspi_cdram |= (~(1 << spi->chip_select) &
 815                                        MSPI_CDRAM_PCS);
 816
 817                 mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
 818                                 MSPI_CDRAM_BITSE_BIT);
 819
 820                 write_cdram_slot(qspi, slot, mspi_cdram);
 821
 822                 tstatus = update_qspi_trans_byte_count(qspi, &tp,
 823                                                        TRANS_STATUS_BREAK_TX);
 824                 slot++;
 825         }
 826
 827         if (!slot) {
 828                 dev_err(&qspi->pdev->dev, "%s: no data to send?", __func__);
 829                 goto done;
 830         }
 831
 832         dev_dbg(&qspi->pdev->dev, "submitting %d slots\n", slot);
 833         bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
 834         bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
 835
 836         /*
 837          *  case 1) EOM =1, cs_change =0: SSb inactive
 838          *  case 2) EOM =1, cs_change =1: SSb stay active
 839          *  case 3) EOM =0, cs_change =0: SSb stay active
 840          *  case 4) EOM =0, cs_change =1: SSb inactive
 841          */
 842         if (((tstatus & TRANS_STATUS_BREAK_DESELECT)
 843              == TRANS_STATUS_BREAK_CS_CHANGE) ||
 844             ((tstatus & TRANS_STATUS_BREAK_DESELECT)
 845              == TRANS_STATUS_BREAK_EOM)) {
 846                 mspi_cdram = read_cdram_slot(qspi, slot - 1) &
 847                         ~MSPI_CDRAM_CONT_BIT;
 848                 write_cdram_slot(qspi, slot - 1, mspi_cdram);
 849         }
 850
 851         if (has_bspi(qspi))
 852                 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1);
 853
 854         /* Must flush previous writes before starting MSPI operation */
 855         mb();
 856         /* Set cont | spe | spifie */
 857         bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0);
 858
 859 done:
 860         return slot;
 861 }
 862
 863 static int bcm_qspi_bspi_exec_mem_op(struct spi_device *spi,
 864                                      const struct spi_mem_op *op)
 865 {
 866         struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
 867         u32 addr = 0, len, rdlen, len_words, from = 0;
 868         int ret = 0;
 869         unsigned long timeo = msecs_to_jiffies(100);
 870         struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
 871
 872         if (bcm_qspi_bspi_ver_three(qspi))
 873                 if (op->addr.nbytes == BSPI_ADDRLEN_4BYTES)
 874                         return -EIO;
 875
 876         from = op->addr.val;
 877         if (!spi->cs_gpiod)
 878                 bcm_qspi_chip_select(qspi, spi->chip_select);
 879         bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
 880
 881         /*
 882          * when using flex mode we need to send
 883          * the upper address byte to bspi
 884          */
 885         if (!bcm_qspi_bspi_ver_three(qspi)) {
 886                 addr = from & 0xff000000;
 887                 bcm_qspi_write(qspi, BSPI,
 888                                BSPI_BSPI_FLASH_UPPER_ADDR_BYTE, addr);
 889         }
 890
 891         if (!qspi->xfer_mode.flex_mode)
 892                 addr = from;
 893         else
 894                 addr = from & 0x00ffffff;
 895
 896         if (bcm_qspi_bspi_ver_three(qspi) == true)
 897                 addr = (addr + 0xc00000) & 0xffffff;
 898
 899         /*
 900          * read into the entire buffer by breaking the reads
 901          * into RAF buffer read lengths
 902          */
 903         len = op->data.nbytes;
 904         qspi->bspi_rf_op_idx = 0;
 905
 906         do {
 907                 if (len > BSPI_READ_LENGTH)
 908                         rdlen = BSPI_READ_LENGTH;
 909                 else
 910                         rdlen = len;
 911
 912                 reinit_completion(&qspi->bspi_done);
 913                 bcm_qspi_enable_bspi(qspi);
 914                 len_words = (rdlen + 3) >> 2;
 915                 qspi->bspi_rf_op = op;
 916                 qspi->bspi_rf_op_status = 0;
 917                 qspi->bspi_rf_op_len = rdlen;
 918                 dev_dbg(&qspi->pdev->dev,
 919                         "bspi xfr addr 0x%x len 0x%x", addr, rdlen);
 920                 bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr);
 921                 bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words);
 922                 bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0);
 923                 if (qspi->soc_intc) {
 924                         /*
 925                          * clear soc MSPI and BSPI interrupts and enable
 926                          * BSPI interrupts.
 927                          */
 928                         soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE);
 929                         soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true);
 930                 }
 931
 932                 /* Must flush previous writes before starting BSPI operation */
 933                 mb();
 934                 bcm_qspi_bspi_lr_start(qspi);
 935                 if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) {
 936                         dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n");
 937                         ret = -ETIMEDOUT;
 938                         break;
 939                 }
 940
 941                 /* set msg return length */
 942                 addr += rdlen;
 943                 len -= rdlen;
 944         } while (len);
 945
 946         return ret;
 947 }
 948
 949 static int bcm_qspi_transfer_one(struct spi_master *master,
 950                                  struct spi_device *spi,
 951                                  struct spi_transfer *trans)
 952 {
 953         struct bcm_qspi *qspi = spi_master_get_devdata(master);
 954         int slots;
 955         unsigned long timeo = msecs_to_jiffies(100);
 956
 957         if (!spi->cs_gpiod)
 958                 bcm_qspi_chip_select(qspi, spi->chip_select);
 959         qspi->trans_pos.trans = trans;
 960         qspi->trans_pos.byte = 0;
 961
 962         while (qspi->trans_pos.byte < trans->len) {
 963                 reinit_completion(&qspi->mspi_done);
 964
 965                 slots = write_to_hw(qspi, spi);
 966                 if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) {
 967                         dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n");
 968                         return -ETIMEDOUT;
 969                 }
 970
 971                 read_from_hw(qspi, slots);
 972         }
 973         bcm_qspi_enable_bspi(qspi);
 974
 975         return 0;
 976 }
 977
 978 static int bcm_qspi_mspi_exec_mem_op(struct spi_device *spi,
 979                                      const struct spi_mem_op *op)
 980 {
 981         struct spi_master *master = spi->master;
 982         struct bcm_qspi *qspi = spi_master_get_devdata(master);
 983         struct spi_transfer t[2];
 984         u8 cmd[6] = { };
 985         int ret, i;
 986
 987         memset(cmd, 0, sizeof(cmd));
 988         memset(t, 0, sizeof(t));
 989
 990         /* tx */
 991         /* opcode is in cmd[0] */
 992         cmd[0] = op->cmd.opcode;
 993         for (i = 0; i < op->addr.nbytes; i++)
 994                 cmd[1 + i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
 995
 996         t[0].tx_buf = cmd;
 997         t[0].len = op->addr.nbytes + op->dummy.nbytes + 1;
 998         t[0].bits_per_word = spi->bits_per_word;
 999         t[0].tx_nbits = op->cmd.buswidth;
1000         /* lets mspi know that this is not last transfer */
1001         qspi->trans_pos.mspi_last_trans = false;
1002         ret = bcm_qspi_transfer_one(master, spi, &t[0]);
1003
1004         /* rx */
1005         qspi->trans_pos.mspi_last_trans = true;
1006         if (!ret) {
1007                 /* rx */
1008                 t[1].rx_buf = op->data.buf.in;
1009                 t[1].len = op->data.nbytes;
1010                 t[1].rx_nbits =  op->data.buswidth;
1011                 t[1].bits_per_word = spi->bits_per_word;
1012                 ret = bcm_qspi_transfer_one(master, spi, &t[1]);
1013         }
1014
1015         return ret;
1016 }
1017
1018 static int bcm_qspi_exec_mem_op(struct spi_mem *mem,
1019                                 const struct spi_mem_op *op)
1020 {
1021         struct spi_device *spi = mem->spi;
1022         struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
1023         int ret = 0;
1024         bool mspi_read = false;
1025         u32 addr = 0, len;
1026         u_char *buf;
1027
1028         if (!op->data.nbytes || !op->addr.nbytes || op->addr.nbytes > 4 ||
1029             op->data.dir != SPI_MEM_DATA_IN)
1030                 return -ENOTSUPP;
1031
1032         buf = op->data.buf.in;
1033         addr = op->addr.val;
1034         len = op->data.nbytes;
1035
1036         if (has_bspi(qspi) && bcm_qspi_bspi_ver_three(qspi) == true) {
1037                 /*
1038                  * The address coming into this function is a raw flash offset.
1039                  * But for BSPI <= V3, we need to convert it to a remapped BSPI
1040                  * address. If it crosses a 4MB boundary, just revert back to
1041                  * using MSPI.
1042                  */
1043                 addr = (addr + 0xc00000) & 0xffffff;
1044
1045                 if ((~ADDR_4MB_MASK & addr) ^
1046                     (~ADDR_4MB_MASK & (addr + len - 1)))
1047                         mspi_read = true;
1048         }
1049
1050         /* non-aligned and very short transfers are handled by MSPI */
1051         if (!IS_ALIGNED((uintptr_t)addr, 4) || !IS_ALIGNED((uintptr_t)buf, 4) ||
1052             len < 4)
1053                 mspi_read = true;
1054
1055         if (!has_bspi(qspi) || mspi_read)
1056                 return bcm_qspi_mspi_exec_mem_op(spi, op);
1057
1058         ret = bcm_qspi_bspi_set_mode(qspi, op, 0);
1059
1060         if (!ret)
1061                 ret = bcm_qspi_bspi_exec_mem_op(spi, op);
1062
1063         return ret;
1064 }
1065
1066 static void bcm_qspi_cleanup(struct spi_device *spi)
1067 {
1068         struct bcm_qspi_parms *xp = spi_get_ctldata(spi);
1069
1070         kfree(xp);
1071 }
1072
1073 static irqreturn_t bcm_qspi_mspi_l2_isr(int irq, void *dev_id)
1074 {
1075         struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1076         struct bcm_qspi *qspi = qspi_dev_id->dev;
1077         u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
1078
1079         if (status & MSPI_MSPI_STATUS_SPIF) {
1080                 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1081                 /* clear interrupt */
1082                 status &= ~MSPI_MSPI_STATUS_SPIF;
1083                 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);
1084                 if (qspi->soc_intc)
1085                         soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_DONE);
1086                 complete(&qspi->mspi_done);
1087                 return IRQ_HANDLED;
1088         }
1089
1090         return IRQ_NONE;
1091 }
1092
1093 static irqreturn_t bcm_qspi_bspi_lr_l2_isr(int irq, void *dev_id)
1094 {
1095         struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1096         struct bcm_qspi *qspi = qspi_dev_id->dev;
1097         struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1098         u32 status = qspi_dev_id->irqp->mask;
1099
1100         if (qspi->bspi_enabled && qspi->bspi_rf_op) {
1101                 bcm_qspi_bspi_lr_data_read(qspi);
1102                 if (qspi->bspi_rf_op_len == 0) {
1103                         qspi->bspi_rf_op = NULL;
1104                         if (qspi->soc_intc) {
1105                                 /* disable soc BSPI interrupt */
1106                                 soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE,
1107                                                            false);
1108                                 /* indicate done */
1109                                 status = INTR_BSPI_LR_SESSION_DONE_MASK;
1110                         }
1111
1112                         if (qspi->bspi_rf_op_status)
1113                                 bcm_qspi_bspi_lr_clear(qspi);
1114                         else
1115                                 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
1116                 }
1117
1118                 if (qspi->soc_intc)
1119                         /* clear soc BSPI interrupt */
1120                         soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_DONE);
1121         }
1122
1123         status &= INTR_BSPI_LR_SESSION_DONE_MASK;
1124         if (qspi->bspi_enabled && status && qspi->bspi_rf_op_len == 0)
1125                 complete(&qspi->bspi_done);
1126
1127         return IRQ_HANDLED;
1128 }
1129
1130 static irqreturn_t bcm_qspi_bspi_lr_err_l2_isr(int irq, void *dev_id)
1131 {
1132         struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1133         struct bcm_qspi *qspi = qspi_dev_id->dev;
1134         struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1135
1136         dev_err(&qspi->pdev->dev, "BSPI INT error\n");
1137         qspi->bspi_rf_op_status = -EIO;
1138         if (qspi->soc_intc)
1139                 /* clear soc interrupt */
1140                 soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_ERR);
1141
1142         complete(&qspi->bspi_done);
1143         return IRQ_HANDLED;
1144 }
1145
1146 static irqreturn_t bcm_qspi_l1_isr(int irq, void *dev_id)
1147 {
1148         struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1149         struct bcm_qspi *qspi = qspi_dev_id->dev;
1150         struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1151         irqreturn_t ret = IRQ_NONE;
1152
1153         if (soc_intc) {
1154                 u32 status = soc_intc->bcm_qspi_get_int_status(soc_intc);
1155
1156                 if (status & MSPI_DONE)
1157                         ret = bcm_qspi_mspi_l2_isr(irq, dev_id);
1158                 else if (status & BSPI_DONE)
1159                         ret = bcm_qspi_bspi_lr_l2_isr(irq, dev_id);
1160                 else if (status & BSPI_ERR)
1161                         ret = bcm_qspi_bspi_lr_err_l2_isr(irq, dev_id);
1162         }
1163
1164         return ret;
1165 }
1166
1167 static const struct bcm_qspi_irq qspi_irq_tab[] = {
1168         {
1169                 .irq_name = "spi_lr_fullness_reached",
1170                 .irq_handler = bcm_qspi_bspi_lr_l2_isr,
1171                 .mask = INTR_BSPI_LR_FULLNESS_REACHED_MASK,
1172         },
1173         {
1174                 .irq_name = "spi_lr_session_aborted",
1175                 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1176                 .mask = INTR_BSPI_LR_SESSION_ABORTED_MASK,
1177         },
1178         {
1179                 .irq_name = "spi_lr_impatient",
1180                 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1181                 .mask = INTR_BSPI_LR_IMPATIENT_MASK,
1182         },
1183         {
1184                 .irq_name = "spi_lr_session_done",
1185                 .irq_handler = bcm_qspi_bspi_lr_l2_isr,
1186                 .mask = INTR_BSPI_LR_SESSION_DONE_MASK,
1187         },
1188 #ifdef QSPI_INT_DEBUG
1189         /* this interrupt is for debug purposes only, dont request irq */
1190         {
1191                 .irq_name = "spi_lr_overread",
1192                 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1193                 .mask = INTR_BSPI_LR_OVERREAD_MASK,
1194         },
1195 #endif
1196         {
1197                 .irq_name = "mspi_done",
1198                 .irq_handler = bcm_qspi_mspi_l2_isr,
1199                 .mask = INTR_MSPI_DONE_MASK,
1200         },
1201         {
1202                 .irq_name = "mspi_halted",
1203                 .irq_handler = bcm_qspi_mspi_l2_isr,
1204                 .mask = INTR_MSPI_HALTED_MASK,
1205         },
1206         {
1207                 /* single muxed L1 interrupt source */
1208                 .irq_name = "spi_l1_intr",
1209                 .irq_handler = bcm_qspi_l1_isr,
1210                 .irq_source = MUXED_L1,
1211                 .mask = QSPI_INTERRUPTS_ALL,
1212         },
1213 };
1214
1215 static void bcm_qspi_bspi_init(struct bcm_qspi *qspi)
1216 {
1217         u32 val = 0;
1218
1219         val = bcm_qspi_read(qspi, BSPI, BSPI_REVISION_ID);
1220         qspi->bspi_maj_rev = (val >> 8) & 0xff;
1221         qspi->bspi_min_rev = val & 0xff;
1222         if (!(bcm_qspi_bspi_ver_three(qspi))) {
1223                 /* Force mapping of BSPI address -> flash offset */
1224                 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_VALUE, 0);
1225                 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_ENABLE, 1);
1226         }
1227         qspi->bspi_enabled = 1;
1228         bcm_qspi_disable_bspi(qspi);
1229         bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
1230         bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
1231 }
1232
1233 static void bcm_qspi_hw_init(struct bcm_qspi *qspi)
1234 {
1235         struct bcm_qspi_parms parms;
1236
1237         bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0);
1238         bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0);
1239         bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
1240         bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0);
1241         bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20);
1242
1243         parms.mode = SPI_MODE_3;
1244         parms.bits_per_word = 8;
1245         parms.speed_hz = qspi->max_speed_hz;
1246         bcm_qspi_hw_set_parms(qspi, &parms);
1247
1248         if (has_bspi(qspi))
1249                 bcm_qspi_bspi_init(qspi);
1250 }
1251
1252 static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi)
1253 {
1254         u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
1255
1256         bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);
1257         if (has_bspi(qspi))
1258                 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
1259
1260         /* clear interrupt */
1261         bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status & ~1);
1262 }
1263
1264 static const struct spi_controller_mem_ops bcm_qspi_mem_ops = {
1265         .exec_op = bcm_qspi_exec_mem_op,
1266 };
1267
1268 struct bcm_qspi_data {
1269         bool    has_mspi_rev;
1270         bool    has_spcr3_sysclk;
1271 };
1272
1273 static const struct bcm_qspi_data bcm_qspi_no_rev_data = {
1274         .has_mspi_rev   = false,
1275         .has_spcr3_sysclk = false,
1276 };
1277
1278 static const struct bcm_qspi_data bcm_qspi_rev_data = {
1279         .has_mspi_rev   = true,
1280         .has_spcr3_sysclk = false,
1281 };
1282
1283 static const struct bcm_qspi_data bcm_qspi_spcr3_data = {
1284         .has_mspi_rev   = true,
1285         .has_spcr3_sysclk = true,
1286 };
1287
1288 static const struct of_device_id bcm_qspi_of_match[] = {
1289         {
1290                 .compatible = "brcm,spi-bcm7445-qspi",
1291                 .data = &bcm_qspi_rev_data,
1292
1293         },
1294         {
1295                 .compatible = "brcm,spi-bcm-qspi",
1296                 .data = &bcm_qspi_no_rev_data,
1297         },
1298         {
1299                 .compatible = "brcm,spi-bcm7216-qspi",
1300                 .data = &bcm_qspi_spcr3_data,
1301         },
1302         {
1303                 .compatible = "brcm,spi-bcm7278-qspi",
1304                 .data = &bcm_qspi_spcr3_data,
1305         },
1306         {},
1307 };
1308 MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);
1309
1310 int bcm_qspi_probe(struct platform_device *pdev,
1311                    struct bcm_qspi_soc_intc *soc_intc)
1312 {
1313         const struct of_device_id *of_id = NULL;
1314         const struct bcm_qspi_data *data;
1315         struct device *dev = &pdev->dev;
1316         struct bcm_qspi *qspi;
1317         struct spi_master *master;
1318         struct resource *res;
1319         int irq, ret = 0, num_ints = 0;
1320         u32 val;
1321         u32 rev = 0;
1322         const char *name = NULL;
1323         int num_irqs = ARRAY_SIZE(qspi_irq_tab);
1324
1325         /* We only support device-tree instantiation */
1326         if (!dev->of_node)
1327                 return -ENODEV;
1328
1329         of_id = of_match_node(bcm_qspi_of_match, dev->of_node);
1330         if (!of_id)
1331                 return -ENODEV;
1332
1333         data = of_id->data;
1334
1335         master = devm_spi_alloc_master(dev, sizeof(struct bcm_qspi));
1336         if (!master) {
1337                 dev_err(dev, "error allocating spi_master\n");
1338                 return -ENOMEM;
1339         }
1340
1341         qspi = spi_master_get_devdata(master);
1342
1343         qspi->clk = devm_clk_get_optional(&pdev->dev, NULL);
1344         if (IS_ERR(qspi->clk))
1345                 return PTR_ERR(qspi->clk);
1346
1347         qspi->pdev = pdev;
1348         qspi->trans_pos.trans = NULL;
1349         qspi->trans_pos.byte = 0;
1350         qspi->trans_pos.mspi_last_trans = true;
1351         qspi->master = master;
1352
1353         master->bus_num = -1;
1354         master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD;
1355         master->setup = bcm_qspi_setup;
1356         master->transfer_one = bcm_qspi_transfer_one;
1357         master->mem_ops = &bcm_qspi_mem_ops;
1358         master->cleanup = bcm_qspi_cleanup;
1359         master->dev.of_node = dev->of_node;
1360         master->num_chipselect = NUM_CHIPSELECT;
1361         master->use_gpio_descriptors = true;
1362
1363         qspi->big_endian = of_device_is_big_endian(dev->of_node);
1364
1365         if (!of_property_read_u32(dev->of_node, "num-cs", &val))
1366                 master->num_chipselect = val;
1367
1368         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hif_mspi");
1369         if (!res)
1370                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1371                                                    "mspi");
1372
1373         if (res) {
1374                 qspi->base[MSPI]  = devm_ioremap_resource(dev, res);
1375                 if (IS_ERR(qspi->base[MSPI]))
1376                         return PTR_ERR(qspi->base[MSPI]);
1377         } else {
1378                 return 0;
1379         }
1380
1381         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bspi");
1382         if (res) {
1383                 qspi->base[BSPI]  = devm_ioremap_resource(dev, res);
1384                 if (IS_ERR(qspi->base[BSPI]))
1385                         return PTR_ERR(qspi->base[BSPI]);
1386                 qspi->bspi_mode = true;
1387         } else {
1388                 qspi->bspi_mode = false;
1389         }
1390
1391         dev_info(dev, "using %smspi mode\n", qspi->bspi_mode ? "bspi-" : "");
1392
1393         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs_reg");
1394         if (res) {
1395                 qspi->base[CHIP_SELECT]  = devm_ioremap_resource(dev, res);
1396                 if (IS_ERR(qspi->base[CHIP_SELECT]))
1397                         return PTR_ERR(qspi->base[CHIP_SELECT]);
1398         }
1399
1400         qspi->dev_ids = kcalloc(num_irqs, sizeof(struct bcm_qspi_dev_id),
1401                                 GFP_KERNEL);
1402         if (!qspi->dev_ids)
1403                 return -ENOMEM;
1404
1405         /*
1406          * Some SoCs integrate spi controller (e.g., its interrupt bits)
1407          * in specific ways
1408          */
1409         if (soc_intc) {
1410                 qspi->soc_intc = soc_intc;
1411                 soc_intc->bcm_qspi_int_set(soc_intc, MSPI_DONE, true);
1412         } else {
1413                 qspi->soc_intc = NULL;
1414         }
1415
1416         if (qspi->clk) {
1417                 ret = clk_prepare_enable(qspi->clk);
1418                 if (ret) {
1419                         dev_err(dev, "failed to prepare clock\n");
1420                         goto qspi_probe_err;
1421                 }
1422                 qspi->base_clk = clk_get_rate(qspi->clk);
1423         } else {
1424                 qspi->base_clk = MSPI_BASE_FREQ;
1425         }
1426
1427         if (data->has_mspi_rev) {
1428                 rev = bcm_qspi_read(qspi, MSPI, MSPI_REV);
1429                 /* some older revs do not have a MSPI_REV register */
1430                 if ((rev & 0xff) == 0xff)
1431                         rev = 0;
1432         }
1433
1434         qspi->mspi_maj_rev = (rev >> 4) & 0xf;
1435         qspi->mspi_min_rev = rev & 0xf;
1436         qspi->mspi_spcr3_sysclk = data->has_spcr3_sysclk;
1437
1438         qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2);
1439
1440         /*
1441          * On SW resets it is possible to have the mask still enabled
1442          * Need to disable the mask and clear the status while we init
1443          */
1444         bcm_qspi_hw_uninit(qspi);
1445
1446         for (val = 0; val < num_irqs; val++) {
1447                 irq = -1;
1448                 name = qspi_irq_tab[val].irq_name;
1449                 if (qspi_irq_tab[val].irq_source == SINGLE_L2) {
1450                         /* get the l2 interrupts */
1451                         irq = platform_get_irq_byname_optional(pdev, name);
1452                 } else if (!num_ints && soc_intc) {
1453                         /* all mspi, bspi intrs muxed to one L1 intr */
1454                         irq = platform_get_irq(pdev, 0);
1455                 }
1456
1457                 if (irq  >= 0) {
1458                         ret = devm_request_irq(&pdev->dev, irq,
1459                                                qspi_irq_tab[val].irq_handler, 0,
1460                                                name,
1461                                                &qspi->dev_ids[val]);
1462                         if (ret < 0) {
1463                                 dev_err(&pdev->dev, "IRQ %s not found\n", name);
1464                                 goto qspi_unprepare_err;
1465                         }
1466
1467                         qspi->dev_ids[val].dev = qspi;
1468                         qspi->dev_ids[val].irqp = &qspi_irq_tab[val];
1469                         num_ints++;
1470                         dev_dbg(&pdev->dev, "registered IRQ %s %d\n",
1471                                 qspi_irq_tab[val].irq_name,
1472                                 irq);
1473                 }
1474         }
1475
1476         if (!num_ints) {
1477                 dev_err(&pdev->dev, "no IRQs registered, cannot init driver\n");
1478                 ret = -EINVAL;
1479                 goto qspi_unprepare_err;
1480         }
1481
1482         bcm_qspi_hw_init(qspi);
1483         init_completion(&qspi->mspi_done);
1484         init_completion(&qspi->bspi_done);
1485         qspi->curr_cs = -1;
1486
1487         platform_set_drvdata(pdev, qspi);
1488
1489         qspi->xfer_mode.width = -1;
1490         qspi->xfer_mode.addrlen = -1;
1491         qspi->xfer_mode.hp = -1;
1492
1493         ret = spi_register_master(master);
1494         if (ret < 0) {
1495                 dev_err(dev, "can't register master\n");
1496                 goto qspi_reg_err;
1497         }
1498
1499         return 0;
1500
1501 qspi_reg_err:
1502         bcm_qspi_hw_uninit(qspi);
1503 qspi_unprepare_err:
1504         clk_disable_unprepare(qspi->clk);
1505 qspi_probe_err:
1506         kfree(qspi->dev_ids);
1507         return ret;
1508 }
1509 /* probe function to be called by SoC specific platform driver probe */
1510 EXPORT_SYMBOL_GPL(bcm_qspi_probe);
1511
1512 int bcm_qspi_remove(struct platform_device *pdev)
1513 {
1514         struct bcm_qspi *qspi = platform_get_drvdata(pdev);
1515
1516         spi_unregister_master(qspi->master);
1517         bcm_qspi_hw_uninit(qspi);
1518         clk_disable_unprepare(qspi->clk);
1519         kfree(qspi->dev_ids);
1520
1521         return 0;
1522 }
1523 /* function to be called by SoC specific platform driver remove() */
1524 EXPORT_SYMBOL_GPL(bcm_qspi_remove);
1525
1526 static int __maybe_unused bcm_qspi_suspend(struct device *dev)
1527 {
1528         struct bcm_qspi *qspi = dev_get_drvdata(dev);
1529
1530         /* store the override strap value */
1531         if (!bcm_qspi_bspi_ver_three(qspi))
1532                 qspi->s3_strap_override_ctrl =
1533                         bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
1534
1535         spi_master_suspend(qspi->master);
1536         clk_disable_unprepare(qspi->clk);
1537         bcm_qspi_hw_uninit(qspi);
1538
1539         return 0;
1540 };
1541
1542 static int __maybe_unused bcm_qspi_resume(struct device *dev)
1543 {
1544         struct bcm_qspi *qspi = dev_get_drvdata(dev);
1545         int ret = 0;
1546
1547         bcm_qspi_hw_init(qspi);
1548         bcm_qspi_chip_select(qspi, qspi->curr_cs);
1549         if (qspi->soc_intc)
1550                 /* enable MSPI interrupt */
1551                 qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE,
1552                                                  true);
1553
1554         ret = clk_prepare_enable(qspi->clk);
1555         if (!ret)
1556                 spi_master_resume(qspi->master);
1557
1558         return ret;
1559 }
1560
1561 SIMPLE_DEV_PM_OPS(bcm_qspi_pm_ops, bcm_qspi_suspend, bcm_qspi_resume);
1562
1563 /* pm_ops to be called by SoC specific platform driver */
1564 EXPORT_SYMBOL_GPL(bcm_qspi_pm_ops);
1565
1566 MODULE_AUTHOR("Kamal Dasu");
1567 MODULE_DESCRIPTION("Broadcom QSPI driver");
1568 MODULE_LICENSE("GPL v2");
1569 MODULE_ALIAS("platform:" DRIVER_NAME);