drivers/spi/spi-au1550.c

   1 /*
   2  * au1550 psc spi controller driver
   3  * may work also with au1200, au1210, au1250
   4  * will not work on au1000, au1100 and au1500 (no full spi controller there)
   5  *
   6  * Copyright (c) 2006 ATRON electronic GmbH
   7  * Author: Jan Nikitenko <jan.nikitenko@gmail.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/slab.h>
  27 #include <linux/errno.h>
  28 #include <linux/module.h>
  29 #include <linux/device.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/resource.h>
  32 #include <linux/spi/spi.h>
  33 #include <linux/spi/spi_bitbang.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/completion.h>
  36 #include <asm/mach-au1x00/au1000.h>
  37 #include <asm/mach-au1x00/au1xxx_psc.h>
  38 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  39
  40 #include <asm/mach-au1x00/au1550_spi.h>
  41
  42 static unsigned usedma = 1;
  43 module_param(usedma, uint, 0644);
  44
  45 /*
  46 #define AU1550_SPI_DEBUG_LOOPBACK
  47 */
  48
  49
  50 #define AU1550_SPI_DBDMA_DESCRIPTORS 1
  51 #define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U
  52
  53 struct au1550_spi {
  54         struct spi_bitbang bitbang;
  55
  56         volatile psc_spi_t __iomem *regs;
  57         int irq;
  58         unsigned freq_max;
  59         unsigned freq_min;
  60
  61         unsigned len;
  62         unsigned tx_count;
  63         unsigned rx_count;
  64         const u8 *tx;
  65         u8 *rx;
  66
  67         void (*rx_word)(struct au1550_spi *hw);
  68         void (*tx_word)(struct au1550_spi *hw);
  69         int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
  70         irqreturn_t (*irq_callback)(struct au1550_spi *hw);
  71
  72         struct completion master_done;
  73
  74         unsigned usedma;
  75         u32 dma_tx_id;
  76         u32 dma_rx_id;
  77         u32 dma_tx_ch;
  78         u32 dma_rx_ch;
  79
  80         u8 *dma_rx_tmpbuf;
  81         unsigned dma_rx_tmpbuf_size;
  82         u32 dma_rx_tmpbuf_addr;
  83
  84         struct spi_master *master;
  85         struct device *dev;
  86         struct au1550_spi_info *pdata;
  87         struct resource *ioarea;
  88 };
  89
  90
  91 /* we use an 8-bit memory device for dma transfers to/from spi fifo */
  92 static dbdev_tab_t au1550_spi_mem_dbdev =
  93 {
  94         .dev_id                 = DBDMA_MEM_CHAN,
  95         .dev_flags              = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
  96         .dev_tsize              = 0,
  97         .dev_devwidth           = 8,
  98         .dev_physaddr           = 0x00000000,
  99         .dev_intlevel           = 0,
 100         .dev_intpolarity        = 0
 101 };
 102
 103 static int ddma_memid;  /* id to above mem dma device */
 104
 105 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
 106
 107
 108 /*
 109  *  compute BRG and DIV bits to setup spi clock based on main input clock rate
 110  *  that was specified in platform data structure
 111  *  according to au1550 datasheet:
 112  *    psc_tempclk = psc_mainclk / (2 << DIV)
 113  *    spiclk = psc_tempclk / (2 * (BRG + 1))
 114  *    BRG valid range is 4..63
 115  *    DIV valid range is 0..3
 116  */
 117 static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
 118 {
 119         u32 mainclk_hz = hw->pdata->mainclk_hz;
 120         u32 div, brg;
 121
 122         for (div = 0; div < 4; div++) {
 123                 brg = mainclk_hz / speed_hz / (4 << div);
 124                 /* now we have BRG+1 in brg, so count with that */
 125                 if (brg < (4 + 1)) {
 126                         brg = (4 + 1);  /* speed_hz too big */
 127                         break;          /* set lowest brg (div is == 0) */
 128                 }
 129                 if (brg <= (63 + 1))
 130                         break;          /* we have valid brg and div */
 131         }
 132         if (div == 4) {
 133                 div = 3;                /* speed_hz too small */
 134                 brg = (63 + 1);         /* set highest brg and div */
 135         }
 136         brg--;
 137         return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
 138 }
 139
 140 static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
 141 {
 142         hw->regs->psc_spimsk =
 143                   PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
 144                 | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
 145                 | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
 146         au_sync();
 147
 148         hw->regs->psc_spievent =
 149                   PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
 150                 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
 151                 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
 152         au_sync();
 153 }
 154
 155 static void au1550_spi_reset_fifos(struct au1550_spi *hw)
 156 {
 157         u32 pcr;
 158
 159         hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
 160         au_sync();
 161         do {
 162                 pcr = hw->regs->psc_spipcr;
 163                 au_sync();
 164         } while (pcr != 0);
 165 }
 166
 167 /*
 168  * dma transfers are used for the most common spi word size of 8-bits
 169  * we cannot easily change already set up dma channels' width, so if we wanted
 170  * dma support for more than 8-bit words (up to 24 bits), we would need to
 171  * setup dma channels from scratch on each spi transfer, based on bits_per_word
 172  * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits
 173  * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode
 174  * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set()
 175  */
 176 static void au1550_spi_chipsel(struct spi_device *spi, int value)
 177 {
 178         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
 179         unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
 180         u32 cfg, stat;
 181
 182         switch (value) {
 183         case BITBANG_CS_INACTIVE:
 184                 if (hw->pdata->deactivate_cs)
 185                         hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
 186                                         cspol);
 187                 break;
 188
 189         case BITBANG_CS_ACTIVE:
 190                 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
 191
 192                 cfg = hw->regs->psc_spicfg;
 193                 au_sync();
 194                 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
 195                 au_sync();
 196
 197                 if (spi->mode & SPI_CPOL)
 198                         cfg |= PSC_SPICFG_BI;
 199                 else
 200                         cfg &= ~PSC_SPICFG_BI;
 201                 if (spi->mode & SPI_CPHA)
 202                         cfg &= ~PSC_SPICFG_CDE;
 203                 else
 204                         cfg |= PSC_SPICFG_CDE;
 205
 206                 if (spi->mode & SPI_LSB_FIRST)
 207                         cfg |= PSC_SPICFG_MLF;
 208                 else
 209                         cfg &= ~PSC_SPICFG_MLF;
 210
 211                 if (hw->usedma && spi->bits_per_word <= 8)
 212                         cfg &= ~PSC_SPICFG_DD_DISABLE;
 213                 else
 214                         cfg |= PSC_SPICFG_DD_DISABLE;
 215                 cfg = PSC_SPICFG_CLR_LEN(cfg);
 216                 cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word);
 217
 218                 cfg = PSC_SPICFG_CLR_BAUD(cfg);
 219                 cfg &= ~PSC_SPICFG_SET_DIV(3);
 220                 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
 221
 222                 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
 223                 au_sync();
 224                 do {
 225                         stat = hw->regs->psc_spistat;
 226                         au_sync();
 227                 } while ((stat & PSC_SPISTAT_DR) == 0);
 228
 229                 if (hw->pdata->activate_cs)
 230                         hw->pdata->activate_cs(hw->pdata, spi->chip_select,
 231                                         cspol);
 232                 break;
 233         }
 234 }
 235
 236 static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
 237 {
 238         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
 239         unsigned bpw, hz;
 240         u32 cfg, stat;
 241
 242         bpw = spi->bits_per_word;
 243         hz = spi->max_speed_hz;
 244         if (t) {
 245                 if (t->bits_per_word)
 246                         bpw = t->bits_per_word;
 247                 if (t->speed_hz)
 248                         hz = t->speed_hz;
 249         }
 250
 251         if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) {
 252                 dev_err(&spi->dev, "setupxfer: clock rate=%d out of range\n",
 253                         hz);
 254                 return -EINVAL;
 255         }
 256
 257         au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
 258
 259         cfg = hw->regs->psc_spicfg;
 260         au_sync();
 261         hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
 262         au_sync();
 263
 264         if (hw->usedma && bpw <= 8)
 265                 cfg &= ~PSC_SPICFG_DD_DISABLE;
 266         else
 267                 cfg |= PSC_SPICFG_DD_DISABLE;
 268         cfg = PSC_SPICFG_CLR_LEN(cfg);
 269         cfg |= PSC_SPICFG_SET_LEN(bpw);
 270
 271         cfg = PSC_SPICFG_CLR_BAUD(cfg);
 272         cfg &= ~PSC_SPICFG_SET_DIV(3);
 273         cfg |= au1550_spi_baudcfg(hw, hz);
 274
 275         hw->regs->psc_spicfg = cfg;
 276         au_sync();
 277
 278         if (cfg & PSC_SPICFG_DE_ENABLE) {
 279                 do {
 280                         stat = hw->regs->psc_spistat;
 281                         au_sync();
 282                 } while ((stat & PSC_SPISTAT_DR) == 0);
 283         }
 284
 285         au1550_spi_reset_fifos(hw);
 286         au1550_spi_mask_ack_all(hw);
 287         return 0;
 288 }
 289
 290 static int au1550_spi_setup(struct spi_device *spi)
 291 {
 292         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
 293
 294         if (spi->max_speed_hz == 0)
 295                 spi->max_speed_hz = hw->freq_max;
 296         if (spi->max_speed_hz > hw->freq_max
 297                         || spi->max_speed_hz < hw->freq_min)
 298                 return -EINVAL;
 299         /*
 300          * NOTE: cannot change speed and other hw settings immediately,
 301          *       otherwise sharing of spi bus is not possible,
 302          *       so do not call setupxfer(spi, NULL) here
 303          */
 304         return 0;
 305 }
 306
 307 /*
 308  * for dma spi transfers, we have to setup rx channel, otherwise there is
 309  * no reliable way how to recognize that spi transfer is done
 310  * dma complete callbacks are called before real spi transfer is finished
 311  * and if only tx dma channel is set up (and rx fifo overflow event masked)
 312  * spi master done event irq is not generated unless rx fifo is empty (emptied)
 313  * so we need rx tmp buffer to use for rx dma if user does not provide one
 314  */
 315 static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size)
 316 {
 317         hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
 318         if (!hw->dma_rx_tmpbuf)
 319                 return -ENOMEM;
 320         hw->dma_rx_tmpbuf_size = size;
 321         hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
 322                         size, DMA_FROM_DEVICE);
 323         if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) {
 324                 kfree(hw->dma_rx_tmpbuf);
 325                 hw->dma_rx_tmpbuf = 0;
 326                 hw->dma_rx_tmpbuf_size = 0;
 327                 return -EFAULT;
 328         }
 329         return 0;
 330 }
 331
 332 static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
 333 {
 334         dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
 335                         hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
 336         kfree(hw->dma_rx_tmpbuf);
 337         hw->dma_rx_tmpbuf = 0;
 338         hw->dma_rx_tmpbuf_size = 0;
 339 }
 340
 341 static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
 342 {
 343         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
 344         dma_addr_t dma_tx_addr;
 345         dma_addr_t dma_rx_addr;
 346         u32 res;
 347
 348         hw->len = t->len;
 349         hw->tx_count = 0;
 350         hw->rx_count = 0;
 351
 352         hw->tx = t->tx_buf;
 353         hw->rx = t->rx_buf;
 354         dma_tx_addr = t->tx_dma;
 355         dma_rx_addr = t->rx_dma;
 356
 357         /*
 358          * check if buffers are already dma mapped, map them otherwise:
 359          * - first map the TX buffer, so cache data gets written to memory
 360          * - then map the RX buffer, so that cache entries (with
 361          *   soon-to-be-stale data) get removed
 362          * use rx buffer in place of tx if tx buffer was not provided
 363          * use temp rx buffer (preallocated or realloc to fit) for rx dma
 364          */
 365         if (t->tx_buf) {
 366                 if (t->tx_dma == 0) {   /* if DMA_ADDR_INVALID, map it */
 367                         dma_tx_addr = dma_map_single(hw->dev,
 368                                         (void *)t->tx_buf,
 369                                         t->len, DMA_TO_DEVICE);
 370                         if (dma_mapping_error(hw->dev, dma_tx_addr))
 371                                 dev_err(hw->dev, "tx dma map error\n");
 372                 }
 373         }
 374
 375         if (t->rx_buf) {
 376                 if (t->rx_dma == 0) {   /* if DMA_ADDR_INVALID, map it */
 377                         dma_rx_addr = dma_map_single(hw->dev,
 378                                         (void *)t->rx_buf,
 379                                         t->len, DMA_FROM_DEVICE);
 380                         if (dma_mapping_error(hw->dev, dma_rx_addr))
 381                                 dev_err(hw->dev, "rx dma map error\n");
 382                 }
 383         } else {
 384                 if (t->len > hw->dma_rx_tmpbuf_size) {
 385                         int ret;
 386
 387                         au1550_spi_dma_rxtmp_free(hw);
 388                         ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
 389                                         AU1550_SPI_DMA_RXTMP_MINSIZE));
 390                         if (ret < 0)
 391                                 return ret;
 392                 }
 393                 hw->rx = hw->dma_rx_tmpbuf;
 394                 dma_rx_addr = hw->dma_rx_tmpbuf_addr;
 395                 dma_sync_single_for_device(hw->dev, dma_rx_addr,
 396                         t->len, DMA_FROM_DEVICE);
 397         }
 398
 399         if (!t->tx_buf) {
 400                 dma_sync_single_for_device(hw->dev, dma_rx_addr,
 401                                 t->len, DMA_BIDIRECTIONAL);
 402                 hw->tx = hw->rx;
 403         }
 404
 405         /* put buffers on the ring */
 406         res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, virt_to_phys(hw->rx),
 407                                     t->len, DDMA_FLAGS_IE);
 408         if (!res)
 409                 dev_err(hw->dev, "rx dma put dest error\n");
 410
 411         res = au1xxx_dbdma_put_source(hw->dma_tx_ch, virt_to_phys(hw->tx),
 412                                       t->len, DDMA_FLAGS_IE);
 413         if (!res)
 414                 dev_err(hw->dev, "tx dma put source error\n");
 415
 416         au1xxx_dbdma_start(hw->dma_rx_ch);
 417         au1xxx_dbdma_start(hw->dma_tx_ch);
 418
 419         /* by default enable nearly all events interrupt */
 420         hw->regs->psc_spimsk = PSC_SPIMSK_SD;
 421         au_sync();
 422
 423         /* start the transfer */
 424         hw->regs->psc_spipcr = PSC_SPIPCR_MS;
 425         au_sync();
 426
 427         wait_for_completion(&hw->master_done);
 428
 429         au1xxx_dbdma_stop(hw->dma_tx_ch);
 430         au1xxx_dbdma_stop(hw->dma_rx_ch);
 431
 432         if (!t->rx_buf) {
 433                 /* using the temporal preallocated and premapped buffer */
 434                 dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
 435                         DMA_FROM_DEVICE);
 436         }
 437         /* unmap buffers if mapped above */
 438         if (t->rx_buf && t->rx_dma == 0 )
 439                 dma_unmap_single(hw->dev, dma_rx_addr, t->len,
 440                         DMA_FROM_DEVICE);
 441         if (t->tx_buf && t->tx_dma == 0 )
 442                 dma_unmap_single(hw->dev, dma_tx_addr, t->len,
 443                         DMA_TO_DEVICE);
 444
 445         return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
 446 }
 447
 448 static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
 449 {
 450         u32 stat, evnt;
 451
 452         stat = hw->regs->psc_spistat;
 453         evnt = hw->regs->psc_spievent;
 454         au_sync();
 455         if ((stat & PSC_SPISTAT_DI) == 0) {
 456                 dev_err(hw->dev, "Unexpected IRQ!\n");
 457                 return IRQ_NONE;
 458         }
 459
 460         if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
 461                                 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
 462                                 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
 463                         != 0) {
 464                 /*
 465                  * due to an spi error we consider transfer as done,
 466                  * so mask all events until before next transfer start
 467                  * and stop the possibly running dma immediately
 468                  */
 469                 au1550_spi_mask_ack_all(hw);
 470                 au1xxx_dbdma_stop(hw->dma_rx_ch);
 471                 au1xxx_dbdma_stop(hw->dma_tx_ch);
 472
 473                 /* get number of transferred bytes */
 474                 hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
 475                 hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
 476
 477                 au1xxx_dbdma_reset(hw->dma_rx_ch);
 478                 au1xxx_dbdma_reset(hw->dma_tx_ch);
 479                 au1550_spi_reset_fifos(hw);
 480
 481                 if (evnt == PSC_SPIEVNT_RO)
 482                         dev_err(hw->dev,
 483                                 "dma transfer: receive FIFO overflow!\n");
 484                 else
 485                         dev_err(hw->dev,
 486                                 "dma transfer: unexpected SPI error "
 487                                 "(event=0x%x stat=0x%x)!\n", evnt, stat);
 488
 489                 complete(&hw->master_done);
 490                 return IRQ_HANDLED;
 491         }
 492
 493         if ((evnt & PSC_SPIEVNT_MD) != 0) {
 494                 /* transfer completed successfully */
 495                 au1550_spi_mask_ack_all(hw);
 496                 hw->rx_count = hw->len;
 497                 hw->tx_count = hw->len;
 498                 complete(&hw->master_done);
 499         }
 500         return IRQ_HANDLED;
 501 }
 502
 503
 504 /* routines to handle different word sizes in pio mode */
 505 #define AU1550_SPI_RX_WORD(size, mask)                                  \
 506 static void au1550_spi_rx_word_##size(struct au1550_spi *hw)            \
 507 {                                                                       \
 508         u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask);             \
 509         au_sync();                                                      \
 510         if (hw->rx) {                                                   \
 511                 *(u##size *)hw->rx = (u##size)fifoword;                 \
 512                 hw->rx += (size) / 8;                                   \
 513         }                                                               \
 514         hw->rx_count += (size) / 8;                                     \
 515 }
 516
 517 #define AU1550_SPI_TX_WORD(size, mask)                                  \
 518 static void au1550_spi_tx_word_##size(struct au1550_spi *hw)            \
 519 {                                                                       \
 520         u32 fifoword = 0;                                               \
 521         if (hw->tx) {                                                   \
 522                 fifoword = *(u##size *)hw->tx & (u32)(mask);            \
 523                 hw->tx += (size) / 8;                                   \
 524         }                                                               \
 525         hw->tx_count += (size) / 8;                                     \
 526         if (hw->tx_count >= hw->len)                                    \
 527                 fifoword |= PSC_SPITXRX_LC;                             \
 528         hw->regs->psc_spitxrx = fifoword;                               \
 529         au_sync();                                                      \
 530 }
 531
 532 AU1550_SPI_RX_WORD(8,0xff)
 533 AU1550_SPI_RX_WORD(16,0xffff)
 534 AU1550_SPI_RX_WORD(32,0xffffff)
 535 AU1550_SPI_TX_WORD(8,0xff)
 536 AU1550_SPI_TX_WORD(16,0xffff)
 537 AU1550_SPI_TX_WORD(32,0xffffff)
 538
 539 static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
 540 {
 541         u32 stat, mask;
 542         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
 543
 544         hw->tx = t->tx_buf;
 545         hw->rx = t->rx_buf;
 546         hw->len = t->len;
 547         hw->tx_count = 0;
 548         hw->rx_count = 0;
 549
 550         /* by default enable nearly all events after filling tx fifo */
 551         mask = PSC_SPIMSK_SD;
 552
 553         /* fill the transmit FIFO */
 554         while (hw->tx_count < hw->len) {
 555
 556                 hw->tx_word(hw);
 557
 558                 if (hw->tx_count >= hw->len) {
 559                         /* mask tx fifo request interrupt as we are done */
 560                         mask |= PSC_SPIMSK_TR;
 561                 }
 562
 563                 stat = hw->regs->psc_spistat;
 564                 au_sync();
 565                 if (stat & PSC_SPISTAT_TF)
 566                         break;
 567         }
 568
 569         /* enable event interrupts */
 570         hw->regs->psc_spimsk = mask;
 571         au_sync();
 572
 573         /* start the transfer */
 574         hw->regs->psc_spipcr = PSC_SPIPCR_MS;
 575         au_sync();
 576
 577         wait_for_completion(&hw->master_done);
 578
 579         return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
 580 }
 581
 582 static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
 583 {
 584         int busy;
 585         u32 stat, evnt;
 586
 587         stat = hw->regs->psc_spistat;
 588         evnt = hw->regs->psc_spievent;
 589         au_sync();
 590         if ((stat & PSC_SPISTAT_DI) == 0) {
 591                 dev_err(hw->dev, "Unexpected IRQ!\n");
 592                 return IRQ_NONE;
 593         }
 594
 595         if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
 596                                 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
 597                                 | PSC_SPIEVNT_SD))
 598                         != 0) {
 599                 /*
 600                  * due to an error we consider transfer as done,
 601                  * so mask all events until before next transfer start
 602                  */
 603                 au1550_spi_mask_ack_all(hw);
 604                 au1550_spi_reset_fifos(hw);
 605                 dev_err(hw->dev,
 606                         "pio transfer: unexpected SPI error "
 607                         "(event=0x%x stat=0x%x)!\n", evnt, stat);
 608                 complete(&hw->master_done);
 609                 return IRQ_HANDLED;
 610         }
 611
 612         /*
 613          * while there is something to read from rx fifo
 614          * or there is a space to write to tx fifo:
 615          */
 616         do {
 617                 busy = 0;
 618                 stat = hw->regs->psc_spistat;
 619                 au_sync();
 620
 621                 /*
 622                  * Take care to not let the Rx FIFO overflow.
 623                  *
 624                  * We only write a byte if we have read one at least. Initially,
 625                  * the write fifo is full, so we should read from the read fifo
 626                  * first.
 627                  * In case we miss a word from the read fifo, we should get a
 628                  * RO event and should back out.
 629                  */
 630                 if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) {
 631                         hw->rx_word(hw);
 632                         busy = 1;
 633
 634                         if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len)
 635                                 hw->tx_word(hw);
 636                 }
 637         } while (busy);
 638
 639         hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
 640         au_sync();
 641
 642         /*
 643          * Restart the SPI transmission in case of a transmit underflow.
 644          * This seems to work despite the notes in the Au1550 data book
 645          * of Figure 8-4 with flowchart for SPI master operation:
 646          *
 647          * """Note 1: An XFR Error Interrupt occurs, unless masked,
 648          * for any of the following events: Tx FIFO Underflow,
 649          * Rx FIFO Overflow, or Multiple-master Error
 650          *    Note 2: In case of a Tx Underflow Error, all zeroes are
 651          * transmitted."""
 652          *
 653          * By simply restarting the spi transfer on Tx Underflow Error,
 654          * we assume that spi transfer was paused instead of zeroes
 655          * transmittion mentioned in the Note 2 of Au1550 data book.
 656          */
 657         if (evnt & PSC_SPIEVNT_TU) {
 658                 hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
 659                 au_sync();
 660                 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
 661                 au_sync();
 662         }
 663
 664         if (hw->rx_count >= hw->len) {
 665                 /* transfer completed successfully */
 666                 au1550_spi_mask_ack_all(hw);
 667                 complete(&hw->master_done);
 668         }
 669         return IRQ_HANDLED;
 670 }
 671
 672 static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
 673 {
 674         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
 675         return hw->txrx_bufs(spi, t);
 676 }
 677
 678 static irqreturn_t au1550_spi_irq(int irq, void *dev)
 679 {
 680         struct au1550_spi *hw = dev;
 681         return hw->irq_callback(hw);
 682 }
 683
 684 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
 685 {
 686         if (bpw <= 8) {
 687                 if (hw->usedma) {
 688                         hw->txrx_bufs = &au1550_spi_dma_txrxb;
 689                         hw->irq_callback = &au1550_spi_dma_irq_callback;
 690                 } else {
 691                         hw->rx_word = &au1550_spi_rx_word_8;
 692                         hw->tx_word = &au1550_spi_tx_word_8;
 693                         hw->txrx_bufs = &au1550_spi_pio_txrxb;
 694                         hw->irq_callback = &au1550_spi_pio_irq_callback;
 695                 }
 696         } else if (bpw <= 16) {
 697                 hw->rx_word = &au1550_spi_rx_word_16;
 698                 hw->tx_word = &au1550_spi_tx_word_16;
 699                 hw->txrx_bufs = &au1550_spi_pio_txrxb;
 700                 hw->irq_callback = &au1550_spi_pio_irq_callback;
 701         } else {
 702                 hw->rx_word = &au1550_spi_rx_word_32;
 703                 hw->tx_word = &au1550_spi_tx_word_32;
 704                 hw->txrx_bufs = &au1550_spi_pio_txrxb;
 705                 hw->irq_callback = &au1550_spi_pio_irq_callback;
 706         }
 707 }
 708
 709 static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
 710 {
 711         u32 stat, cfg;
 712
 713         /* set up the PSC for SPI mode */
 714         hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
 715         au_sync();
 716         hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
 717         au_sync();
 718
 719         hw->regs->psc_spicfg = 0;
 720         au_sync();
 721
 722         hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
 723         au_sync();
 724
 725         do {
 726                 stat = hw->regs->psc_spistat;
 727                 au_sync();
 728         } while ((stat & PSC_SPISTAT_SR) == 0);
 729
 730
 731         cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
 732         cfg |= PSC_SPICFG_SET_LEN(8);
 733         cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8;
 734         /* use minimal allowed brg and div values as initial setting: */
 735         cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0);
 736
 737 #ifdef AU1550_SPI_DEBUG_LOOPBACK
 738         cfg |= PSC_SPICFG_LB;
 739 #endif
 740
 741         hw->regs->psc_spicfg = cfg;
 742         au_sync();
 743
 744         au1550_spi_mask_ack_all(hw);
 745
 746         hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
 747         au_sync();
 748
 749         do {
 750                 stat = hw->regs->psc_spistat;
 751                 au_sync();
 752         } while ((stat & PSC_SPISTAT_DR) == 0);
 753
 754         au1550_spi_reset_fifos(hw);
 755 }
 756
 757
 758 static int au1550_spi_probe(struct platform_device *pdev)
 759 {
 760         struct au1550_spi *hw;
 761         struct spi_master *master;
 762         struct resource *r;
 763         int err = 0;
 764
 765         master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi));
 766         if (master == NULL) {
 767                 dev_err(&pdev->dev, "No memory for spi_master\n");
 768                 err = -ENOMEM;
 769                 goto err_nomem;
 770         }
 771
 772         /* the spi->mode bits understood by this driver: */
 773         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
 774         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 24);
 775
 776         hw = spi_master_get_devdata(master);
 777
 778         hw->master = master;
 779         hw->pdata = dev_get_platdata(&pdev->dev);
 780         hw->dev = &pdev->dev;
 781
 782         if (hw->pdata == NULL) {
 783                 dev_err(&pdev->dev, "No platform data supplied\n");
 784                 err = -ENOENT;
 785                 goto err_no_pdata;
 786         }
 787
 788         r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 789         if (!r) {
 790                 dev_err(&pdev->dev, "no IRQ\n");
 791                 err = -ENODEV;
 792                 goto err_no_iores;
 793         }
 794         hw->irq = r->start;
 795
 796         hw->usedma = 0;
 797         r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 798         if (r) {
 799                 hw->dma_tx_id = r->start;
 800                 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
 801                 if (r) {
 802                         hw->dma_rx_id = r->start;
 803                         if (usedma && ddma_memid) {
 804                                 if (pdev->dev.dma_mask == NULL)
 805                                         dev_warn(&pdev->dev, "no dma mask\n");
 806                                 else
 807                                         hw->usedma = 1;
 808                         }
 809                 }
 810         }
 811
 812         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 813         if (!r) {
 814                 dev_err(&pdev->dev, "no mmio resource\n");
 815                 err = -ENODEV;
 816                 goto err_no_iores;
 817         }
 818
 819         hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
 820                                         pdev->name);
 821         if (!hw->ioarea) {
 822                 dev_err(&pdev->dev, "Cannot reserve iomem region\n");
 823                 err = -ENXIO;
 824                 goto err_no_iores;
 825         }
 826
 827         hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
 828         if (!hw->regs) {
 829                 dev_err(&pdev->dev, "cannot ioremap\n");
 830                 err = -ENXIO;
 831                 goto err_ioremap;
 832         }
 833
 834         platform_set_drvdata(pdev, hw);
 835
 836         init_completion(&hw->master_done);
 837
 838         hw->bitbang.master = hw->master;
 839         hw->bitbang.setup_transfer = au1550_spi_setupxfer;
 840         hw->bitbang.chipselect = au1550_spi_chipsel;
 841         hw->bitbang.master->setup = au1550_spi_setup;
 842         hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
 843
 844         if (hw->usedma) {
 845                 hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
 846                         hw->dma_tx_id, NULL, (void *)hw);
 847                 if (hw->dma_tx_ch == 0) {
 848                         dev_err(&pdev->dev,
 849                                 "Cannot allocate tx dma channel\n");
 850                         err = -ENXIO;
 851                         goto err_no_txdma;
 852                 }
 853                 au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
 854                 if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
 855                         AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
 856                         dev_err(&pdev->dev,
 857                                 "Cannot allocate tx dma descriptors\n");
 858                         err = -ENXIO;
 859                         goto err_no_txdma_descr;
 860                 }
 861
 862
 863                 hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
 864                         ddma_memid, NULL, (void *)hw);
 865                 if (hw->dma_rx_ch == 0) {
 866                         dev_err(&pdev->dev,
 867                                 "Cannot allocate rx dma channel\n");
 868                         err = -ENXIO;
 869                         goto err_no_rxdma;
 870                 }
 871                 au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
 872                 if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
 873                         AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
 874                         dev_err(&pdev->dev,
 875                                 "Cannot allocate rx dma descriptors\n");
 876                         err = -ENXIO;
 877                         goto err_no_rxdma_descr;
 878                 }
 879
 880                 err = au1550_spi_dma_rxtmp_alloc(hw,
 881                         AU1550_SPI_DMA_RXTMP_MINSIZE);
 882                 if (err < 0) {
 883                         dev_err(&pdev->dev,
 884                                 "Cannot allocate initial rx dma tmp buffer\n");
 885                         goto err_dma_rxtmp_alloc;
 886                 }
 887         }
 888
 889         au1550_spi_bits_handlers_set(hw, 8);
 890
 891         err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
 892         if (err) {
 893                 dev_err(&pdev->dev, "Cannot claim IRQ\n");
 894                 goto err_no_irq;
 895         }
 896
 897         master->bus_num = pdev->id;
 898         master->num_chipselect = hw->pdata->num_chipselect;
 899
 900         /*
 901          *  precompute valid range for spi freq - from au1550 datasheet:
 902          *    psc_tempclk = psc_mainclk / (2 << DIV)
 903          *    spiclk = psc_tempclk / (2 * (BRG + 1))
 904          *    BRG valid range is 4..63
 905          *    DIV valid range is 0..3
 906          *  round the min and max frequencies to values that would still
 907          *  produce valid brg and div
 908          */
 909         {
 910                 int min_div = (2 << 0) * (2 * (4 + 1));
 911                 int max_div = (2 << 3) * (2 * (63 + 1));
 912                 hw->freq_max = hw->pdata->mainclk_hz / min_div;
 913                 hw->freq_min = hw->pdata->mainclk_hz / (max_div + 1) + 1;
 914         }
 915
 916         au1550_spi_setup_psc_as_spi(hw);
 917
 918         err = spi_bitbang_start(&hw->bitbang);
 919         if (err) {
 920                 dev_err(&pdev->dev, "Failed to register SPI master\n");
 921                 goto err_register;
 922         }
 923
 924         dev_info(&pdev->dev,
 925                 "spi master registered: bus_num=%d num_chipselect=%d\n",
 926                 master->bus_num, master->num_chipselect);
 927
 928         return 0;
 929
 930 err_register:
 931         free_irq(hw->irq, hw);
 932
 933 err_no_irq:
 934         au1550_spi_dma_rxtmp_free(hw);
 935
 936 err_dma_rxtmp_alloc:
 937 err_no_rxdma_descr:
 938         if (hw->usedma)
 939                 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
 940
 941 err_no_rxdma:
 942 err_no_txdma_descr:
 943         if (hw->usedma)
 944                 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
 945
 946 err_no_txdma:
 947         iounmap((void __iomem *)hw->regs);
 948
 949 err_ioremap:
 950         release_resource(hw->ioarea);
 951         kfree(hw->ioarea);
 952
 953 err_no_iores:
 954 err_no_pdata:
 955         spi_master_put(hw->master);
 956
 957 err_nomem:
 958         return err;
 959 }
 960
 961 static int au1550_spi_remove(struct platform_device *pdev)
 962 {
 963         struct au1550_spi *hw = platform_get_drvdata(pdev);
 964
 965         dev_info(&pdev->dev, "spi master remove: bus_num=%d\n",
 966                 hw->master->bus_num);
 967
 968         spi_bitbang_stop(&hw->bitbang);
 969         free_irq(hw->irq, hw);
 970         iounmap((void __iomem *)hw->regs);
 971         release_resource(hw->ioarea);
 972         kfree(hw->ioarea);
 973
 974         if (hw->usedma) {
 975                 au1550_spi_dma_rxtmp_free(hw);
 976                 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
 977                 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
 978         }
 979
 980         spi_master_put(hw->master);
 981         return 0;
 982 }
 983
 984 /* work with hotplug and coldplug */
 985 MODULE_ALIAS("platform:au1550-spi");
 986
 987 static struct platform_driver au1550_spi_drv = {
 988         .probe = au1550_spi_probe,
 989         .remove = au1550_spi_remove,
 990         .driver = {
 991                 .name = "au1550-spi",
 992                 .owner = THIS_MODULE,
 993         },
 994 };
 995
 996 static int __init au1550_spi_init(void)
 997 {
 998         /*
 999          * create memory device with 8 bits dev_devwidth
1000          * needed for proper byte ordering to spi fifo
1001          */
1002         if (usedma) {
1003                 ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
1004                 if (!ddma_memid)
1005                         printk(KERN_ERR "au1550-spi: cannot add memory"
1006                                         "dbdma device\n");
1007         }
1008         return platform_driver_register(&au1550_spi_drv);
1009 }
1010 module_init(au1550_spi_init);
1011
1012 static void __exit au1550_spi_exit(void)
1013 {
1014         if (usedma && ddma_memid)
1015                 au1xxx_ddma_del_device(ddma_memid);
1016         platform_driver_unregister(&au1550_spi_drv);
1017 }
1018 module_exit(au1550_spi_exit);
1019
1020 MODULE_DESCRIPTION("Au1550 PSC SPI Driver");
1021 MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>");
1022 MODULE_LICENSE("GPL");