drivers/spi/spi-atmel.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for Atmel AT32 and AT91 SPI Controllers
   4  *
   5  * Copyright (C) 2006 Atmel Corporation
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/clk.h>
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/delay.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/err.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/spi/spi.h>
  18 #include <linux/slab.h>
  19 #include <linux/platform_data/dma-atmel.h>
  20 #include <linux/of.h>
  21
  22 #include <linux/io.h>
  23 #include <linux/gpio/consumer.h>
  24 #include <linux/pinctrl/consumer.h>
  25 #include <linux/pm_runtime.h>
  26
  27 /* SPI register offsets */
  28 #define SPI_CR                                  0x0000
  29 #define SPI_MR                                  0x0004
  30 #define SPI_RDR                                 0x0008
  31 #define SPI_TDR                                 0x000c
  32 #define SPI_SR                                  0x0010
  33 #define SPI_IER                                 0x0014
  34 #define SPI_IDR                                 0x0018
  35 #define SPI_IMR                                 0x001c
  36 #define SPI_CSR0                                0x0030
  37 #define SPI_CSR1                                0x0034
  38 #define SPI_CSR2                                0x0038
  39 #define SPI_CSR3                                0x003c
  40 #define SPI_FMR                                 0x0040
  41 #define SPI_FLR                                 0x0044
  42 #define SPI_VERSION                             0x00fc
  43 #define SPI_RPR                                 0x0100
  44 #define SPI_RCR                                 0x0104
  45 #define SPI_TPR                                 0x0108
  46 #define SPI_TCR                                 0x010c
  47 #define SPI_RNPR                                0x0110
  48 #define SPI_RNCR                                0x0114
  49 #define SPI_TNPR                                0x0118
  50 #define SPI_TNCR                                0x011c
  51 #define SPI_PTCR                                0x0120
  52 #define SPI_PTSR                                0x0124
  53
  54 /* Bitfields in CR */
  55 #define SPI_SPIEN_OFFSET                        0
  56 #define SPI_SPIEN_SIZE                          1
  57 #define SPI_SPIDIS_OFFSET                       1
  58 #define SPI_SPIDIS_SIZE                         1
  59 #define SPI_SWRST_OFFSET                        7
  60 #define SPI_SWRST_SIZE                          1
  61 #define SPI_LASTXFER_OFFSET                     24
  62 #define SPI_LASTXFER_SIZE                       1
  63 #define SPI_TXFCLR_OFFSET                       16
  64 #define SPI_TXFCLR_SIZE                         1
  65 #define SPI_RXFCLR_OFFSET                       17
  66 #define SPI_RXFCLR_SIZE                         1
  67 #define SPI_FIFOEN_OFFSET                       30
  68 #define SPI_FIFOEN_SIZE                         1
  69 #define SPI_FIFODIS_OFFSET                      31
  70 #define SPI_FIFODIS_SIZE                        1
  71
  72 /* Bitfields in MR */
  73 #define SPI_MSTR_OFFSET                         0
  74 #define SPI_MSTR_SIZE                           1
  75 #define SPI_PS_OFFSET                           1
  76 #define SPI_PS_SIZE                             1
  77 #define SPI_PCSDEC_OFFSET                       2
  78 #define SPI_PCSDEC_SIZE                         1
  79 #define SPI_FDIV_OFFSET                         3
  80 #define SPI_FDIV_SIZE                           1
  81 #define SPI_MODFDIS_OFFSET                      4
  82 #define SPI_MODFDIS_SIZE                        1
  83 #define SPI_WDRBT_OFFSET                        5
  84 #define SPI_WDRBT_SIZE                          1
  85 #define SPI_LLB_OFFSET                          7
  86 #define SPI_LLB_SIZE                            1
  87 #define SPI_PCS_OFFSET                          16
  88 #define SPI_PCS_SIZE                            4
  89 #define SPI_DLYBCS_OFFSET                       24
  90 #define SPI_DLYBCS_SIZE                         8
  91
  92 /* Bitfields in RDR */
  93 #define SPI_RD_OFFSET                           0
  94 #define SPI_RD_SIZE                             16
  95
  96 /* Bitfields in TDR */
  97 #define SPI_TD_OFFSET                           0
  98 #define SPI_TD_SIZE                             16
  99
 100 /* Bitfields in SR */
 101 #define SPI_RDRF_OFFSET                         0
 102 #define SPI_RDRF_SIZE                           1
 103 #define SPI_TDRE_OFFSET                         1
 104 #define SPI_TDRE_SIZE                           1
 105 #define SPI_MODF_OFFSET                         2
 106 #define SPI_MODF_SIZE                           1
 107 #define SPI_OVRES_OFFSET                        3
 108 #define SPI_OVRES_SIZE                          1
 109 #define SPI_ENDRX_OFFSET                        4
 110 #define SPI_ENDRX_SIZE                          1
 111 #define SPI_ENDTX_OFFSET                        5
 112 #define SPI_ENDTX_SIZE                          1
 113 #define SPI_RXBUFF_OFFSET                       6
 114 #define SPI_RXBUFF_SIZE                         1
 115 #define SPI_TXBUFE_OFFSET                       7
 116 #define SPI_TXBUFE_SIZE                         1
 117 #define SPI_NSSR_OFFSET                         8
 118 #define SPI_NSSR_SIZE                           1
 119 #define SPI_TXEMPTY_OFFSET                      9
 120 #define SPI_TXEMPTY_SIZE                        1
 121 #define SPI_SPIENS_OFFSET                       16
 122 #define SPI_SPIENS_SIZE                         1
 123 #define SPI_TXFEF_OFFSET                        24
 124 #define SPI_TXFEF_SIZE                          1
 125 #define SPI_TXFFF_OFFSET                        25
 126 #define SPI_TXFFF_SIZE                          1
 127 #define SPI_TXFTHF_OFFSET                       26
 128 #define SPI_TXFTHF_SIZE                         1
 129 #define SPI_RXFEF_OFFSET                        27
 130 #define SPI_RXFEF_SIZE                          1
 131 #define SPI_RXFFF_OFFSET                        28
 132 #define SPI_RXFFF_SIZE                          1
 133 #define SPI_RXFTHF_OFFSET                       29
 134 #define SPI_RXFTHF_SIZE                         1
 135 #define SPI_TXFPTEF_OFFSET                      30
 136 #define SPI_TXFPTEF_SIZE                        1
 137 #define SPI_RXFPTEF_OFFSET                      31
 138 #define SPI_RXFPTEF_SIZE                        1
 139
 140 /* Bitfields in CSR0 */
 141 #define SPI_CPOL_OFFSET                         0
 142 #define SPI_CPOL_SIZE                           1
 143 #define SPI_NCPHA_OFFSET                        1
 144 #define SPI_NCPHA_SIZE                          1
 145 #define SPI_CSAAT_OFFSET                        3
 146 #define SPI_CSAAT_SIZE                          1
 147 #define SPI_BITS_OFFSET                         4
 148 #define SPI_BITS_SIZE                           4
 149 #define SPI_SCBR_OFFSET                         8
 150 #define SPI_SCBR_SIZE                           8
 151 #define SPI_DLYBS_OFFSET                        16
 152 #define SPI_DLYBS_SIZE                          8
 153 #define SPI_DLYBCT_OFFSET                       24
 154 #define SPI_DLYBCT_SIZE                         8
 155
 156 /* Bitfields in RCR */
 157 #define SPI_RXCTR_OFFSET                        0
 158 #define SPI_RXCTR_SIZE                          16
 159
 160 /* Bitfields in TCR */
 161 #define SPI_TXCTR_OFFSET                        0
 162 #define SPI_TXCTR_SIZE                          16
 163
 164 /* Bitfields in RNCR */
 165 #define SPI_RXNCR_OFFSET                        0
 166 #define SPI_RXNCR_SIZE                          16
 167
 168 /* Bitfields in TNCR */
 169 #define SPI_TXNCR_OFFSET                        0
 170 #define SPI_TXNCR_SIZE                          16
 171
 172 /* Bitfields in PTCR */
 173 #define SPI_RXTEN_OFFSET                        0
 174 #define SPI_RXTEN_SIZE                          1
 175 #define SPI_RXTDIS_OFFSET                       1
 176 #define SPI_RXTDIS_SIZE                         1
 177 #define SPI_TXTEN_OFFSET                        8
 178 #define SPI_TXTEN_SIZE                          1
 179 #define SPI_TXTDIS_OFFSET                       9
 180 #define SPI_TXTDIS_SIZE                         1
 181
 182 /* Bitfields in FMR */
 183 #define SPI_TXRDYM_OFFSET                       0
 184 #define SPI_TXRDYM_SIZE                         2
 185 #define SPI_RXRDYM_OFFSET                       4
 186 #define SPI_RXRDYM_SIZE                         2
 187 #define SPI_TXFTHRES_OFFSET                     16
 188 #define SPI_TXFTHRES_SIZE                       6
 189 #define SPI_RXFTHRES_OFFSET                     24
 190 #define SPI_RXFTHRES_SIZE                       6
 191
 192 /* Bitfields in FLR */
 193 #define SPI_TXFL_OFFSET                         0
 194 #define SPI_TXFL_SIZE                           6
 195 #define SPI_RXFL_OFFSET                         16
 196 #define SPI_RXFL_SIZE                           6
 197
 198 /* Constants for BITS */
 199 #define SPI_BITS_8_BPT                          0
 200 #define SPI_BITS_9_BPT                          1
 201 #define SPI_BITS_10_BPT                         2
 202 #define SPI_BITS_11_BPT                         3
 203 #define SPI_BITS_12_BPT                         4
 204 #define SPI_BITS_13_BPT                         5
 205 #define SPI_BITS_14_BPT                         6
 206 #define SPI_BITS_15_BPT                         7
 207 #define SPI_BITS_16_BPT                         8
 208 #define SPI_ONE_DATA                            0
 209 #define SPI_TWO_DATA                            1
 210 #define SPI_FOUR_DATA                           2
 211
 212 /* Bit manipulation macros */
 213 #define SPI_BIT(name) \
 214         (1 << SPI_##name##_OFFSET)
 215 #define SPI_BF(name, value) \
 216         (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
 217 #define SPI_BFEXT(name, value) \
 218         (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
 219 #define SPI_BFINS(name, value, old) \
 220         (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
 221           | SPI_BF(name, value))
 222
 223 /* Register access macros */
 224 #ifdef CONFIG_AVR32
 225 #define spi_readl(port, reg) \
 226         __raw_readl((port)->regs + SPI_##reg)
 227 #define spi_writel(port, reg, value) \
 228         __raw_writel((value), (port)->regs + SPI_##reg)
 229
 230 #define spi_readw(port, reg) \
 231         __raw_readw((port)->regs + SPI_##reg)
 232 #define spi_writew(port, reg, value) \
 233         __raw_writew((value), (port)->regs + SPI_##reg)
 234
 235 #define spi_readb(port, reg) \
 236         __raw_readb((port)->regs + SPI_##reg)
 237 #define spi_writeb(port, reg, value) \
 238         __raw_writeb((value), (port)->regs + SPI_##reg)
 239 #else
 240 #define spi_readl(port, reg) \
 241         readl_relaxed((port)->regs + SPI_##reg)
 242 #define spi_writel(port, reg, value) \
 243         writel_relaxed((value), (port)->regs + SPI_##reg)
 244
 245 #define spi_readw(port, reg) \
 246         readw_relaxed((port)->regs + SPI_##reg)
 247 #define spi_writew(port, reg, value) \
 248         writew_relaxed((value), (port)->regs + SPI_##reg)
 249
 250 #define spi_readb(port, reg) \
 251         readb_relaxed((port)->regs + SPI_##reg)
 252 #define spi_writeb(port, reg, value) \
 253         writeb_relaxed((value), (port)->regs + SPI_##reg)
 254 #endif
 255 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 256  * cache operations; better heuristics consider wordsize and bitrate.
 257  */
 258 #define DMA_MIN_BYTES   16
 259
 260 #define SPI_DMA_TIMEOUT         (msecs_to_jiffies(1000))
 261
 262 #define AUTOSUSPEND_TIMEOUT     2000
 263
 264 struct atmel_spi_caps {
 265         bool    is_spi2;
 266         bool    has_wdrbt;
 267         bool    has_dma_support;
 268         bool    has_pdc_support;
 269 };
 270
 271 /*
 272  * The core SPI transfer engine just talks to a register bank to set up
 273  * DMA transfers; transfer queue progress is driven by IRQs.  The clock
 274  * framework provides the base clock, subdivided for each spi_device.
 275  */
 276 struct atmel_spi {
 277         spinlock_t              lock;
 278         unsigned long           flags;
 279
 280         phys_addr_t             phybase;
 281         void __iomem            *regs;
 282         int                     irq;
 283         struct clk              *clk;
 284         struct platform_device  *pdev;
 285         unsigned long           spi_clk;
 286
 287         struct spi_transfer     *current_transfer;
 288         int                     current_remaining_bytes;
 289         int                     done_status;
 290         dma_addr_t              dma_addr_rx_bbuf;
 291         dma_addr_t              dma_addr_tx_bbuf;
 292         void                    *addr_rx_bbuf;
 293         void                    *addr_tx_bbuf;
 294
 295         struct completion       xfer_completion;
 296
 297         struct atmel_spi_caps   caps;
 298
 299         bool                    use_dma;
 300         bool                    use_pdc;
 301         bool                    use_cs_gpios;
 302
 303         bool                    keep_cs;
 304         bool                    cs_active;
 305
 306         u32                     fifo_size;
 307 };
 308
 309 /* Controller-specific per-slave state */
 310 struct atmel_spi_device {
 311         struct gpio_desc        *npcs_pin;
 312         u32                     csr;
 313 };
 314
 315 #define SPI_MAX_DMA_XFER        65535 /* true for both PDC and DMA */
 316 #define INVALID_DMA_ADDRESS     0xffffffff
 317
 318 /*
 319  * Version 2 of the SPI controller has
 320  *  - CR.LASTXFER
 321  *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
 322  *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
 323  *  - SPI_CSRx.CSAAT
 324  *  - SPI_CSRx.SBCR allows faster clocking
 325  */
 326 static bool atmel_spi_is_v2(struct atmel_spi *as)
 327 {
 328         return as->caps.is_spi2;
 329 }
 330
 331 /*
 332  * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
 333  * they assume that spi slave device state will not change on deselect, so
 334  * that automagic deselection is OK.  ("NPCSx rises if no data is to be
 335  * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
 336  * controllers have CSAAT and friends.
 337  *
 338  * Since the CSAAT functionality is a bit weird on newer controllers as
 339  * well, we use GPIO to control nCSx pins on all controllers, updating
 340  * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
 341  * support active-high chipselects despite the controller's belief that
 342  * only active-low devices/systems exists.
 343  *
 344  * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
 345  * right when driven with GPIO.  ("Mode Fault does not allow more than one
 346  * Master on Chip Select 0.")  No workaround exists for that ... so for
 347  * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
 348  * and (c) will trigger that first erratum in some cases.
 349  */
 350
 351 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
 352 {
 353         struct atmel_spi_device *asd = spi->controller_state;
 354         u32 mr;
 355
 356         if (atmel_spi_is_v2(as)) {
 357                 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
 358                 /* For the low SPI version, there is a issue that PDC transfer
 359                  * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
 360                  */
 361                 spi_writel(as, CSR0, asd->csr);
 362                 if (as->caps.has_wdrbt) {
 363                         spi_writel(as, MR,
 364                                         SPI_BF(PCS, ~(0x01 << spi->chip_select))
 365                                         | SPI_BIT(WDRBT)
 366                                         | SPI_BIT(MODFDIS)
 367                                         | SPI_BIT(MSTR));
 368                 } else {
 369                         spi_writel(as, MR,
 370                                         SPI_BF(PCS, ~(0x01 << spi->chip_select))
 371                                         | SPI_BIT(MODFDIS)
 372                                         | SPI_BIT(MSTR));
 373                 }
 374
 375                 mr = spi_readl(as, MR);
 376                 if (as->use_cs_gpios)
 377                         gpiod_set_value(asd->npcs_pin, 1);
 378         } else {
 379                 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
 380                 int i;
 381                 u32 csr;
 382
 383                 /* Make sure clock polarity is correct */
 384                 for (i = 0; i < spi->master->num_chipselect; i++) {
 385                         csr = spi_readl(as, CSR0 + 4 * i);
 386                         if ((csr ^ cpol) & SPI_BIT(CPOL))
 387                                 spi_writel(as, CSR0 + 4 * i,
 388                                                 csr ^ SPI_BIT(CPOL));
 389                 }
 390
 391                 mr = spi_readl(as, MR);
 392                 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
 393                 if (as->use_cs_gpios && spi->chip_select != 0)
 394                         gpiod_set_value(asd->npcs_pin, 1);
 395                 spi_writel(as, MR, mr);
 396         }
 397
 398         dev_dbg(&spi->dev, "activate NPCS, mr %08x\n", mr);
 399 }
 400
 401 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
 402 {
 403         struct atmel_spi_device *asd = spi->controller_state;
 404         u32 mr;
 405
 406         /* only deactivate *this* device; sometimes transfers to
 407          * another device may be active when this routine is called.
 408          */
 409         mr = spi_readl(as, MR);
 410         if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
 411                 mr = SPI_BFINS(PCS, 0xf, mr);
 412                 spi_writel(as, MR, mr);
 413         }
 414
 415         dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr);
 416
 417         if (!as->use_cs_gpios)
 418                 spi_writel(as, CR, SPI_BIT(LASTXFER));
 419         else if (atmel_spi_is_v2(as) || spi->chip_select != 0)
 420                 gpiod_set_value(asd->npcs_pin, 0);
 421 }
 422
 423 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
 424 {
 425         spin_lock_irqsave(&as->lock, as->flags);
 426 }
 427
 428 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
 429 {
 430         spin_unlock_irqrestore(&as->lock, as->flags);
 431 }
 432
 433 static inline bool atmel_spi_is_vmalloc_xfer(struct spi_transfer *xfer)
 434 {
 435         return is_vmalloc_addr(xfer->tx_buf) || is_vmalloc_addr(xfer->rx_buf);
 436 }
 437
 438 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
 439                                 struct spi_transfer *xfer)
 440 {
 441         return as->use_dma && xfer->len >= DMA_MIN_BYTES;
 442 }
 443
 444 static bool atmel_spi_can_dma(struct spi_master *master,
 445                               struct spi_device *spi,
 446                               struct spi_transfer *xfer)
 447 {
 448         struct atmel_spi *as = spi_master_get_devdata(master);
 449
 450         if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5))
 451                 return atmel_spi_use_dma(as, xfer) &&
 452                         !atmel_spi_is_vmalloc_xfer(xfer);
 453         else
 454                 return atmel_spi_use_dma(as, xfer);
 455
 456 }
 457
 458 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
 459                                 struct dma_slave_config *slave_config,
 460                                 u8 bits_per_word)
 461 {
 462         struct spi_master *master = platform_get_drvdata(as->pdev);
 463         int err = 0;
 464
 465         if (bits_per_word > 8) {
 466                 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 467                 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 468         } else {
 469                 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 470                 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 471         }
 472
 473         slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
 474         slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
 475         slave_config->src_maxburst = 1;
 476         slave_config->dst_maxburst = 1;
 477         slave_config->device_fc = false;
 478
 479         /*
 480          * This driver uses fixed peripheral select mode (PS bit set to '0' in
 481          * the Mode Register).
 482          * So according to the datasheet, when FIFOs are available (and
 483          * enabled), the Transmit FIFO operates in Multiple Data Mode.
 484          * In this mode, up to 2 data, not 4, can be written into the Transmit
 485          * Data Register in a single access.
 486          * However, the first data has to be written into the lowest 16 bits and
 487          * the second data into the highest 16 bits of the Transmit
 488          * Data Register. For 8bit data (the most frequent case), it would
 489          * require to rework tx_buf so each data would actualy fit 16 bits.
 490          * So we'd rather write only one data at the time. Hence the transmit
 491          * path works the same whether FIFOs are available (and enabled) or not.
 492          */
 493         slave_config->direction = DMA_MEM_TO_DEV;
 494         if (dmaengine_slave_config(master->dma_tx, slave_config)) {
 495                 dev_err(&as->pdev->dev,
 496                         "failed to configure tx dma channel\n");
 497                 err = -EINVAL;
 498         }
 499
 500         /*
 501          * This driver configures the spi controller for master mode (MSTR bit
 502          * set to '1' in the Mode Register).
 503          * So according to the datasheet, when FIFOs are available (and
 504          * enabled), the Receive FIFO operates in Single Data Mode.
 505          * So the receive path works the same whether FIFOs are available (and
 506          * enabled) or not.
 507          */
 508         slave_config->direction = DMA_DEV_TO_MEM;
 509         if (dmaengine_slave_config(master->dma_rx, slave_config)) {
 510                 dev_err(&as->pdev->dev,
 511                         "failed to configure rx dma channel\n");
 512                 err = -EINVAL;
 513         }
 514
 515         return err;
 516 }
 517
 518 static int atmel_spi_configure_dma(struct spi_master *master,
 519                                    struct atmel_spi *as)
 520 {
 521         struct dma_slave_config slave_config;
 522         struct device *dev = &as->pdev->dev;
 523         int err;
 524
 525         dma_cap_mask_t mask;
 526         dma_cap_zero(mask);
 527         dma_cap_set(DMA_SLAVE, mask);
 528
 529         master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
 530         if (IS_ERR(master->dma_tx)) {
 531                 err = PTR_ERR(master->dma_tx);
 532                 if (err == -EPROBE_DEFER) {
 533                         dev_warn(dev, "no DMA channel available at the moment\n");
 534                         goto error_clear;
 535                 }
 536                 dev_err(dev,
 537                         "DMA TX channel not available, SPI unable to use DMA\n");
 538                 err = -EBUSY;
 539                 goto error_clear;
 540         }
 541
 542         /*
 543          * No reason to check EPROBE_DEFER here since we have already requested
 544          * tx channel. If it fails here, it's for another reason.
 545          */
 546         master->dma_rx = dma_request_slave_channel(dev, "rx");
 547
 548         if (!master->dma_rx) {
 549                 dev_err(dev,
 550                         "DMA RX channel not available, SPI unable to use DMA\n");
 551                 err = -EBUSY;
 552                 goto error;
 553         }
 554
 555         err = atmel_spi_dma_slave_config(as, &slave_config, 8);
 556         if (err)
 557                 goto error;
 558
 559         dev_info(&as->pdev->dev,
 560                         "Using %s (tx) and %s (rx) for DMA transfers\n",
 561                         dma_chan_name(master->dma_tx),
 562                         dma_chan_name(master->dma_rx));
 563
 564         return 0;
 565 error:
 566         if (master->dma_rx)
 567                 dma_release_channel(master->dma_rx);
 568         if (!IS_ERR(master->dma_tx))
 569                 dma_release_channel(master->dma_tx);
 570 error_clear:
 571         master->dma_tx = master->dma_rx = NULL;
 572         return err;
 573 }
 574
 575 static void atmel_spi_stop_dma(struct spi_master *master)
 576 {
 577         if (master->dma_rx)
 578                 dmaengine_terminate_all(master->dma_rx);
 579         if (master->dma_tx)
 580                 dmaengine_terminate_all(master->dma_tx);
 581 }
 582
 583 static void atmel_spi_release_dma(struct spi_master *master)
 584 {
 585         if (master->dma_rx) {
 586                 dma_release_channel(master->dma_rx);
 587                 master->dma_rx = NULL;
 588         }
 589         if (master->dma_tx) {
 590                 dma_release_channel(master->dma_tx);
 591                 master->dma_tx = NULL;
 592         }
 593 }
 594
 595 /* This function is called by the DMA driver from tasklet context */
 596 static void dma_callback(void *data)
 597 {
 598         struct spi_master       *master = data;
 599         struct atmel_spi        *as = spi_master_get_devdata(master);
 600
 601         if (is_vmalloc_addr(as->current_transfer->rx_buf) &&
 602             IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
 603                 memcpy(as->current_transfer->rx_buf, as->addr_rx_bbuf,
 604                        as->current_transfer->len);
 605         }
 606         complete(&as->xfer_completion);
 607 }
 608
 609 /*
 610  * Next transfer using PIO without FIFO.
 611  */
 612 static void atmel_spi_next_xfer_single(struct spi_master *master,
 613                                        struct spi_transfer *xfer)
 614 {
 615         struct atmel_spi        *as = spi_master_get_devdata(master);
 616         unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
 617
 618         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
 619
 620         /* Make sure data is not remaining in RDR */
 621         spi_readl(as, RDR);
 622         while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
 623                 spi_readl(as, RDR);
 624                 cpu_relax();
 625         }
 626
 627         if (xfer->bits_per_word > 8)
 628                 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
 629         else
 630                 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
 631
 632         dev_dbg(master->dev.parent,
 633                 "  start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
 634                 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
 635                 xfer->bits_per_word);
 636
 637         /* Enable relevant interrupts */
 638         spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
 639 }
 640
 641 /*
 642  * Next transfer using PIO with FIFO.
 643  */
 644 static void atmel_spi_next_xfer_fifo(struct spi_master *master,
 645                                      struct spi_transfer *xfer)
 646 {
 647         struct atmel_spi *as = spi_master_get_devdata(master);
 648         u32 current_remaining_data, num_data;
 649         u32 offset = xfer->len - as->current_remaining_bytes;
 650         const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset);
 651         const u8  *bytes = (const u8  *)((u8 *)xfer->tx_buf + offset);
 652         u16 td0, td1;
 653         u32 fifomr;
 654
 655         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n");
 656
 657         /* Compute the number of data to transfer in the current iteration */
 658         current_remaining_data = ((xfer->bits_per_word > 8) ?
 659                                   ((u32)as->current_remaining_bytes >> 1) :
 660                                   (u32)as->current_remaining_bytes);
 661         num_data = min(current_remaining_data, as->fifo_size);
 662
 663         /* Flush RX and TX FIFOs */
 664         spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR));
 665         while (spi_readl(as, FLR))
 666                 cpu_relax();
 667
 668         /* Set RX FIFO Threshold to the number of data to transfer */
 669         fifomr = spi_readl(as, FMR);
 670         spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr));
 671
 672         /* Clear FIFO flags in the Status Register, especially RXFTHF */
 673         (void)spi_readl(as, SR);
 674
 675         /* Fill TX FIFO */
 676         while (num_data >= 2) {
 677                 if (xfer->bits_per_word > 8) {
 678                         td0 = *words++;
 679                         td1 = *words++;
 680                 } else {
 681                         td0 = *bytes++;
 682                         td1 = *bytes++;
 683                 }
 684
 685                 spi_writel(as, TDR, (td1 << 16) | td0);
 686                 num_data -= 2;
 687         }
 688
 689         if (num_data) {
 690                 if (xfer->bits_per_word > 8)
 691                         td0 = *words++;
 692                 else
 693                         td0 = *bytes++;
 694
 695                 spi_writew(as, TDR, td0);
 696                 num_data--;
 697         }
 698
 699         dev_dbg(master->dev.parent,
 700                 "  start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
 701                 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
 702                 xfer->bits_per_word);
 703
 704         /*
 705          * Enable RX FIFO Threshold Flag interrupt to be notified about
 706          * transfer completion.
 707          */
 708         spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
 709 }
 710
 711 /*
 712  * Next transfer using PIO.
 713  */
 714 static void atmel_spi_next_xfer_pio(struct spi_master *master,
 715                                     struct spi_transfer *xfer)
 716 {
 717         struct atmel_spi *as = spi_master_get_devdata(master);
 718
 719         if (as->fifo_size)
 720                 atmel_spi_next_xfer_fifo(master, xfer);
 721         else
 722                 atmel_spi_next_xfer_single(master, xfer);
 723 }
 724
 725 /*
 726  * Submit next transfer for DMA.
 727  */
 728 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
 729                                 struct spi_transfer *xfer,
 730                                 u32 *plen)
 731 {
 732         struct atmel_spi        *as = spi_master_get_devdata(master);
 733         struct dma_chan         *rxchan = master->dma_rx;
 734         struct dma_chan         *txchan = master->dma_tx;
 735         struct dma_async_tx_descriptor *rxdesc;
 736         struct dma_async_tx_descriptor *txdesc;
 737         struct dma_slave_config slave_config;
 738         dma_cookie_t            cookie;
 739
 740         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
 741
 742         /* Check that the channels are available */
 743         if (!rxchan || !txchan)
 744                 return -ENODEV;
 745
 746         /* release lock for DMA operations */
 747         atmel_spi_unlock(as);
 748
 749         *plen = xfer->len;
 750
 751         if (atmel_spi_dma_slave_config(as, &slave_config,
 752                                        xfer->bits_per_word))
 753                 goto err_exit;
 754
 755         /* Send both scatterlists */
 756         if (atmel_spi_is_vmalloc_xfer(xfer) &&
 757             IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
 758                 rxdesc = dmaengine_prep_slave_single(rxchan,
 759                                                      as->dma_addr_rx_bbuf,
 760                                                      xfer->len,
 761                                                      DMA_DEV_TO_MEM,
 762                                                      DMA_PREP_INTERRUPT |
 763                                                      DMA_CTRL_ACK);
 764         } else {
 765                 rxdesc = dmaengine_prep_slave_sg(rxchan,
 766                                                  xfer->rx_sg.sgl,
 767                                                  xfer->rx_sg.nents,
 768                                                  DMA_DEV_TO_MEM,
 769                                                  DMA_PREP_INTERRUPT |
 770                                                  DMA_CTRL_ACK);
 771         }
 772         if (!rxdesc)
 773                 goto err_dma;
 774
 775         if (atmel_spi_is_vmalloc_xfer(xfer) &&
 776             IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
 777                 memcpy(as->addr_tx_bbuf, xfer->tx_buf, xfer->len);
 778                 txdesc = dmaengine_prep_slave_single(txchan,
 779                                                      as->dma_addr_tx_bbuf,
 780                                                      xfer->len, DMA_MEM_TO_DEV,
 781                                                      DMA_PREP_INTERRUPT |
 782                                                      DMA_CTRL_ACK);
 783         } else {
 784                 txdesc = dmaengine_prep_slave_sg(txchan,
 785                                                  xfer->tx_sg.sgl,
 786                                                  xfer->tx_sg.nents,
 787                                                  DMA_MEM_TO_DEV,
 788                                                  DMA_PREP_INTERRUPT |
 789                                                  DMA_CTRL_ACK);
 790         }
 791         if (!txdesc)
 792                 goto err_dma;
 793
 794         dev_dbg(master->dev.parent,
 795                 "  start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 796                 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
 797                 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
 798
 799         /* Enable relevant interrupts */
 800         spi_writel(as, IER, SPI_BIT(OVRES));
 801
 802         /* Put the callback on the RX transfer only, that should finish last */
 803         rxdesc->callback = dma_callback;
 804         rxdesc->callback_param = master;
 805
 806         /* Submit and fire RX and TX with TX last so we're ready to read! */
 807         cookie = rxdesc->tx_submit(rxdesc);
 808         if (dma_submit_error(cookie))
 809                 goto err_dma;
 810         cookie = txdesc->tx_submit(txdesc);
 811         if (dma_submit_error(cookie))
 812                 goto err_dma;
 813         rxchan->device->device_issue_pending(rxchan);
 814         txchan->device->device_issue_pending(txchan);
 815
 816         /* take back lock */
 817         atmel_spi_lock(as);
 818         return 0;
 819
 820 err_dma:
 821         spi_writel(as, IDR, SPI_BIT(OVRES));
 822         atmel_spi_stop_dma(master);
 823 err_exit:
 824         atmel_spi_lock(as);
 825         return -ENOMEM;
 826 }
 827
 828 static void atmel_spi_next_xfer_data(struct spi_master *master,
 829                                 struct spi_transfer *xfer,
 830                                 dma_addr_t *tx_dma,
 831                                 dma_addr_t *rx_dma,
 832                                 u32 *plen)
 833 {
 834         *rx_dma = xfer->rx_dma + xfer->len - *plen;
 835         *tx_dma = xfer->tx_dma + xfer->len - *plen;
 836         if (*plen > master->max_dma_len)
 837                 *plen = master->max_dma_len;
 838 }
 839
 840 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
 841                                     struct spi_device *spi,
 842                                     struct spi_transfer *xfer)
 843 {
 844         u32                     scbr, csr;
 845         unsigned long           bus_hz;
 846
 847         /* v1 chips start out at half the peripheral bus speed. */
 848         bus_hz = as->spi_clk;
 849         if (!atmel_spi_is_v2(as))
 850                 bus_hz /= 2;
 851
 852         /*
 853          * Calculate the lowest divider that satisfies the
 854          * constraint, assuming div32/fdiv/mbz == 0.
 855          */
 856         scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
 857
 858         /*
 859          * If the resulting divider doesn't fit into the
 860          * register bitfield, we can't satisfy the constraint.
 861          */
 862         if (scbr >= (1 << SPI_SCBR_SIZE)) {
 863                 dev_err(&spi->dev,
 864                         "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
 865                         xfer->speed_hz, scbr, bus_hz/255);
 866                 return -EINVAL;
 867         }
 868         if (scbr == 0) {
 869                 dev_err(&spi->dev,
 870                         "setup: %d Hz too high, scbr %u; max %ld Hz\n",
 871                         xfer->speed_hz, scbr, bus_hz);
 872                 return -EINVAL;
 873         }
 874         csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
 875         csr = SPI_BFINS(SCBR, scbr, csr);
 876         spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
 877
 878         return 0;
 879 }
 880
 881 /*
 882  * Submit next transfer for PDC.
 883  * lock is held, spi irq is blocked
 884  */
 885 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
 886                                         struct spi_message *msg,
 887                                         struct spi_transfer *xfer)
 888 {
 889         struct atmel_spi        *as = spi_master_get_devdata(master);
 890         u32                     len;
 891         dma_addr_t              tx_dma, rx_dma;
 892
 893         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 894
 895         len = as->current_remaining_bytes;
 896         atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 897         as->current_remaining_bytes -= len;
 898
 899         spi_writel(as, RPR, rx_dma);
 900         spi_writel(as, TPR, tx_dma);
 901
 902         if (msg->spi->bits_per_word > 8)
 903                 len >>= 1;
 904         spi_writel(as, RCR, len);
 905         spi_writel(as, TCR, len);
 906
 907         dev_dbg(&msg->spi->dev,
 908                 "  start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 909                 xfer, xfer->len, xfer->tx_buf,
 910                 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
 911                 (unsigned long long)xfer->rx_dma);
 912
 913         if (as->current_remaining_bytes) {
 914                 len = as->current_remaining_bytes;
 915                 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 916                 as->current_remaining_bytes -= len;
 917
 918                 spi_writel(as, RNPR, rx_dma);
 919                 spi_writel(as, TNPR, tx_dma);
 920
 921                 if (msg->spi->bits_per_word > 8)
 922                         len >>= 1;
 923                 spi_writel(as, RNCR, len);
 924                 spi_writel(as, TNCR, len);
 925
 926                 dev_dbg(&msg->spi->dev,
 927                         "  next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 928                         xfer, xfer->len, xfer->tx_buf,
 929                         (unsigned long long)xfer->tx_dma, xfer->rx_buf,
 930                         (unsigned long long)xfer->rx_dma);
 931         }
 932
 933         /* REVISIT: We're waiting for RXBUFF before we start the next
 934          * transfer because we need to handle some difficult timing
 935          * issues otherwise. If we wait for TXBUFE in one transfer and
 936          * then starts waiting for RXBUFF in the next, it's difficult
 937          * to tell the difference between the RXBUFF interrupt we're
 938          * actually waiting for and the RXBUFF interrupt of the
 939          * previous transfer.
 940          *
 941          * It should be doable, though. Just not now...
 942          */
 943         spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
 944         spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
 945 }
 946
 947 /*
 948  * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
 949  *  - The buffer is either valid for CPU access, else NULL
 950  *  - If the buffer is valid, so is its DMA address
 951  *
 952  * This driver manages the dma address unless message->is_dma_mapped.
 953  */
 954 static int
 955 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
 956 {
 957         struct device   *dev = &as->pdev->dev;
 958
 959         xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
 960         if (xfer->tx_buf) {
 961                 /* tx_buf is a const void* where we need a void * for the dma
 962                  * mapping */
 963                 void *nonconst_tx = (void *)xfer->tx_buf;
 964
 965                 xfer->tx_dma = dma_map_single(dev,
 966                                 nonconst_tx, xfer->len,
 967                                 DMA_TO_DEVICE);
 968                 if (dma_mapping_error(dev, xfer->tx_dma))
 969                         return -ENOMEM;
 970         }
 971         if (xfer->rx_buf) {
 972                 xfer->rx_dma = dma_map_single(dev,
 973                                 xfer->rx_buf, xfer->len,
 974                                 DMA_FROM_DEVICE);
 975                 if (dma_mapping_error(dev, xfer->rx_dma)) {
 976                         if (xfer->tx_buf)
 977                                 dma_unmap_single(dev,
 978                                                 xfer->tx_dma, xfer->len,
 979                                                 DMA_TO_DEVICE);
 980                         return -ENOMEM;
 981                 }
 982         }
 983         return 0;
 984 }
 985
 986 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
 987                                      struct spi_transfer *xfer)
 988 {
 989         if (xfer->tx_dma != INVALID_DMA_ADDRESS)
 990                 dma_unmap_single(master->dev.parent, xfer->tx_dma,
 991                                  xfer->len, DMA_TO_DEVICE);
 992         if (xfer->rx_dma != INVALID_DMA_ADDRESS)
 993                 dma_unmap_single(master->dev.parent, xfer->rx_dma,
 994                                  xfer->len, DMA_FROM_DEVICE);
 995 }
 996
 997 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
 998 {
 999         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1000 }
1001
1002 static void
1003 atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
1004 {
1005         u8              *rxp;
1006         u16             *rxp16;
1007         unsigned long   xfer_pos = xfer->len - as->current_remaining_bytes;
1008
1009         if (xfer->bits_per_word > 8) {
1010                 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
1011                 *rxp16 = spi_readl(as, RDR);
1012         } else {
1013                 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
1014                 *rxp = spi_readl(as, RDR);
1015         }
1016         if (xfer->bits_per_word > 8) {
1017                 if (as->current_remaining_bytes > 2)
1018                         as->current_remaining_bytes -= 2;
1019                 else
1020                         as->current_remaining_bytes = 0;
1021         } else {
1022                 as->current_remaining_bytes--;
1023         }
1024 }
1025
1026 static void
1027 atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
1028 {
1029         u32 fifolr = spi_readl(as, FLR);
1030         u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr);
1031         u32 offset = xfer->len - as->current_remaining_bytes;
1032         u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset);
1033         u8  *bytes = (u8  *)((u8 *)xfer->rx_buf + offset);
1034         u16 rd; /* RD field is the lowest 16 bits of RDR */
1035
1036         /* Update the number of remaining bytes to transfer */
1037         num_bytes = ((xfer->bits_per_word > 8) ?
1038                      (num_data << 1) :
1039                      num_data);
1040
1041         if (as->current_remaining_bytes > num_bytes)
1042                 as->current_remaining_bytes -= num_bytes;
1043         else
1044                 as->current_remaining_bytes = 0;
1045
1046         /* Handle odd number of bytes when data are more than 8bit width */
1047         if (xfer->bits_per_word > 8)
1048                 as->current_remaining_bytes &= ~0x1;
1049
1050         /* Read data */
1051         while (num_data) {
1052                 rd = spi_readl(as, RDR);
1053                 if (xfer->bits_per_word > 8)
1054                         *words++ = rd;
1055                 else
1056                         *bytes++ = rd;
1057                 num_data--;
1058         }
1059 }
1060
1061 /* Called from IRQ
1062  *
1063  * Must update "current_remaining_bytes" to keep track of data
1064  * to transfer.
1065  */
1066 static void
1067 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
1068 {
1069         if (as->fifo_size)
1070                 atmel_spi_pump_fifo_data(as, xfer);
1071         else
1072                 atmel_spi_pump_single_data(as, xfer);
1073 }
1074
1075 /* Interrupt
1076  *
1077  * No need for locking in this Interrupt handler: done_status is the
1078  * only information modified.
1079  */
1080 static irqreturn_t
1081 atmel_spi_pio_interrupt(int irq, void *dev_id)
1082 {
1083         struct spi_master       *master = dev_id;
1084         struct atmel_spi        *as = spi_master_get_devdata(master);
1085         u32                     status, pending, imr;
1086         struct spi_transfer     *xfer;
1087         int                     ret = IRQ_NONE;
1088
1089         imr = spi_readl(as, IMR);
1090         status = spi_readl(as, SR);
1091         pending = status & imr;
1092
1093         if (pending & SPI_BIT(OVRES)) {
1094                 ret = IRQ_HANDLED;
1095                 spi_writel(as, IDR, SPI_BIT(OVRES));
1096                 dev_warn(master->dev.parent, "overrun\n");
1097
1098                 /*
1099                  * When we get an overrun, we disregard the current
1100                  * transfer. Data will not be copied back from any
1101                  * bounce buffer and msg->actual_len will not be
1102                  * updated with the last xfer.
1103                  *
1104                  * We will also not process any remaning transfers in
1105                  * the message.
1106                  */
1107                 as->done_status = -EIO;
1108                 smp_wmb();
1109
1110                 /* Clear any overrun happening while cleaning up */
1111                 spi_readl(as, SR);
1112
1113                 complete(&as->xfer_completion);
1114
1115         } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
1116                 atmel_spi_lock(as);
1117
1118                 if (as->current_remaining_bytes) {
1119                         ret = IRQ_HANDLED;
1120                         xfer = as->current_transfer;
1121                         atmel_spi_pump_pio_data(as, xfer);
1122                         if (!as->current_remaining_bytes)
1123                                 spi_writel(as, IDR, pending);
1124
1125                         complete(&as->xfer_completion);
1126                 }
1127
1128                 atmel_spi_unlock(as);
1129         } else {
1130                 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1131                 ret = IRQ_HANDLED;
1132                 spi_writel(as, IDR, pending);
1133         }
1134
1135         return ret;
1136 }
1137
1138 static irqreturn_t
1139 atmel_spi_pdc_interrupt(int irq, void *dev_id)
1140 {
1141         struct spi_master       *master = dev_id;
1142         struct atmel_spi        *as = spi_master_get_devdata(master);
1143         u32                     status, pending, imr;
1144         int                     ret = IRQ_NONE;
1145
1146         imr = spi_readl(as, IMR);
1147         status = spi_readl(as, SR);
1148         pending = status & imr;
1149
1150         if (pending & SPI_BIT(OVRES)) {
1151
1152                 ret = IRQ_HANDLED;
1153
1154                 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1155                                      | SPI_BIT(OVRES)));
1156
1157                 /* Clear any overrun happening while cleaning up */
1158                 spi_readl(as, SR);
1159
1160                 as->done_status = -EIO;
1161
1162                 complete(&as->xfer_completion);
1163
1164         } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1165                 ret = IRQ_HANDLED;
1166
1167                 spi_writel(as, IDR, pending);
1168
1169                 complete(&as->xfer_completion);
1170         }
1171
1172         return ret;
1173 }
1174
1175 static int atmel_spi_setup(struct spi_device *spi)
1176 {
1177         struct atmel_spi        *as;
1178         struct atmel_spi_device *asd;
1179         u32                     csr;
1180         unsigned int            bits = spi->bits_per_word;
1181
1182         as = spi_master_get_devdata(spi->master);
1183
1184         /* see notes above re chipselect */
1185         if (!atmel_spi_is_v2(as)
1186                         && spi->chip_select == 0
1187                         && (spi->mode & SPI_CS_HIGH)) {
1188                 dev_dbg(&spi->dev, "setup: can't be active-high\n");
1189                 return -EINVAL;
1190         }
1191
1192         csr = SPI_BF(BITS, bits - 8);
1193         if (spi->mode & SPI_CPOL)
1194                 csr |= SPI_BIT(CPOL);
1195         if (!(spi->mode & SPI_CPHA))
1196                 csr |= SPI_BIT(NCPHA);
1197         if (!as->use_cs_gpios)
1198                 csr |= SPI_BIT(CSAAT);
1199
1200         /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1201          */
1202         csr |= SPI_BF(DLYBS, 0);
1203
1204         /* DLYBCT adds delays between words.  This is useful for slow devices
1205          * that need a bit of time to setup the next transfer.
1206          */
1207         csr |= SPI_BF(DLYBCT,
1208                         (as->spi_clk / 1000000 * spi->word_delay_usecs) >> 5);
1209
1210         asd = spi->controller_state;
1211         if (!asd) {
1212                 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1213                 if (!asd)
1214                         return -ENOMEM;
1215
1216                 /*
1217                  * If use_cs_gpios is true this means that we have "cs-gpios"
1218                  * defined in the device tree node so we should have
1219                  * gotten the GPIO lines from the device tree inside the
1220                  * SPI core. Warn if this is not the case but continue since
1221                  * CS GPIOs are after all optional.
1222                  */
1223                 if (as->use_cs_gpios) {
1224                         if (!spi->cs_gpiod) {
1225                                 dev_err(&spi->dev,
1226                                         "host claims to use CS GPIOs but no CS found in DT by the SPI core\n");
1227                         }
1228                         asd->npcs_pin = spi->cs_gpiod;
1229                 }
1230
1231                 spi->controller_state = asd;
1232         }
1233
1234         asd->csr = csr;
1235
1236         dev_dbg(&spi->dev,
1237                 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1238                 bits, spi->mode, spi->chip_select, csr);
1239
1240         if (!atmel_spi_is_v2(as))
1241                 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
1242
1243         return 0;
1244 }
1245
1246 static int atmel_spi_one_transfer(struct spi_master *master,
1247                                         struct spi_message *msg,
1248                                         struct spi_transfer *xfer)
1249 {
1250         struct atmel_spi        *as;
1251         struct spi_device       *spi = msg->spi;
1252         u8                      bits;
1253         u32                     len;
1254         struct atmel_spi_device *asd;
1255         int                     timeout;
1256         int                     ret;
1257         unsigned long           dma_timeout;
1258
1259         as = spi_master_get_devdata(master);
1260
1261         if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1262                 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1263                 return -EINVAL;
1264         }
1265
1266         asd = spi->controller_state;
1267         bits = (asd->csr >> 4) & 0xf;
1268         if (bits != xfer->bits_per_word - 8) {
1269                 dev_dbg(&spi->dev,
1270                         "you can't yet change bits_per_word in transfers\n");
1271                 return -ENOPROTOOPT;
1272         }
1273
1274         /*
1275          * DMA map early, for performance (empties dcache ASAP) and
1276          * better fault reporting.
1277          */
1278         if ((!msg->is_dma_mapped)
1279                 && as->use_pdc) {
1280                 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1281                         return -ENOMEM;
1282         }
1283
1284         atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1285
1286         as->done_status = 0;
1287         as->current_transfer = xfer;
1288         as->current_remaining_bytes = xfer->len;
1289         while (as->current_remaining_bytes) {
1290                 reinit_completion(&as->xfer_completion);
1291
1292                 if (as->use_pdc) {
1293                         atmel_spi_pdc_next_xfer(master, msg, xfer);
1294                 } else if (atmel_spi_use_dma(as, xfer)) {
1295                         len = as->current_remaining_bytes;
1296                         ret = atmel_spi_next_xfer_dma_submit(master,
1297                                                                 xfer, &len);
1298                         if (ret) {
1299                                 dev_err(&spi->dev,
1300                                         "unable to use DMA, fallback to PIO\n");
1301                                 atmel_spi_next_xfer_pio(master, xfer);
1302                         } else {
1303                                 as->current_remaining_bytes -= len;
1304                                 if (as->current_remaining_bytes < 0)
1305                                         as->current_remaining_bytes = 0;
1306                         }
1307                 } else {
1308                         atmel_spi_next_xfer_pio(master, xfer);
1309                 }
1310
1311                 /* interrupts are disabled, so free the lock for schedule */
1312                 atmel_spi_unlock(as);
1313                 dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
1314                                                           SPI_DMA_TIMEOUT);
1315                 atmel_spi_lock(as);
1316                 if (WARN_ON(dma_timeout == 0)) {
1317                         dev_err(&spi->dev, "spi transfer timeout\n");
1318                         as->done_status = -EIO;
1319                 }
1320
1321                 if (as->done_status)
1322                         break;
1323         }
1324
1325         if (as->done_status) {
1326                 if (as->use_pdc) {
1327                         dev_warn(master->dev.parent,
1328                                 "overrun (%u/%u remaining)\n",
1329                                 spi_readl(as, TCR), spi_readl(as, RCR));
1330
1331                         /*
1332                          * Clean up DMA registers and make sure the data
1333                          * registers are empty.
1334                          */
1335                         spi_writel(as, RNCR, 0);
1336                         spi_writel(as, TNCR, 0);
1337                         spi_writel(as, RCR, 0);
1338                         spi_writel(as, TCR, 0);
1339                         for (timeout = 1000; timeout; timeout--)
1340                                 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1341                                         break;
1342                         if (!timeout)
1343                                 dev_warn(master->dev.parent,
1344                                          "timeout waiting for TXEMPTY");
1345                         while (spi_readl(as, SR) & SPI_BIT(RDRF))
1346                                 spi_readl(as, RDR);
1347
1348                         /* Clear any overrun happening while cleaning up */
1349                         spi_readl(as, SR);
1350
1351                 } else if (atmel_spi_use_dma(as, xfer)) {
1352                         atmel_spi_stop_dma(master);
1353                 }
1354
1355                 if (!msg->is_dma_mapped
1356                         && as->use_pdc)
1357                         atmel_spi_dma_unmap_xfer(master, xfer);
1358
1359                 return 0;
1360
1361         } else {
1362                 /* only update length if no error */
1363                 msg->actual_length += xfer->len;
1364         }
1365
1366         if (!msg->is_dma_mapped
1367                 && as->use_pdc)
1368                 atmel_spi_dma_unmap_xfer(master, xfer);
1369
1370         if (xfer->delay_usecs)
1371                 udelay(xfer->delay_usecs);
1372
1373         if (xfer->cs_change) {
1374                 if (list_is_last(&xfer->transfer_list,
1375                                  &msg->transfers)) {
1376                         as->keep_cs = true;
1377                 } else {
1378                         as->cs_active = !as->cs_active;
1379                         if (as->cs_active)
1380                                 cs_activate(as, msg->spi);
1381                         else
1382                                 cs_deactivate(as, msg->spi);
1383                 }
1384         }
1385
1386         return 0;
1387 }
1388
1389 static int atmel_spi_transfer_one_message(struct spi_master *master,
1390                                                 struct spi_message *msg)
1391 {
1392         struct atmel_spi *as;
1393         struct spi_transfer *xfer;
1394         struct spi_device *spi = msg->spi;
1395         int ret = 0;
1396
1397         as = spi_master_get_devdata(master);
1398
1399         dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1400                                         msg, dev_name(&spi->dev));
1401
1402         atmel_spi_lock(as);
1403         cs_activate(as, spi);
1404
1405         as->cs_active = true;
1406         as->keep_cs = false;
1407
1408         msg->status = 0;
1409         msg->actual_length = 0;
1410
1411         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1412                 ret = atmel_spi_one_transfer(master, msg, xfer);
1413                 if (ret)
1414                         goto msg_done;
1415         }
1416
1417         if (as->use_pdc)
1418                 atmel_spi_disable_pdc_transfer(as);
1419
1420         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1421                 dev_dbg(&spi->dev,
1422                         "  xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1423                         xfer, xfer->len,
1424                         xfer->tx_buf, &xfer->tx_dma,
1425                         xfer->rx_buf, &xfer->rx_dma);
1426         }
1427
1428 msg_done:
1429         if (!as->keep_cs)
1430                 cs_deactivate(as, msg->spi);
1431
1432         atmel_spi_unlock(as);
1433
1434         msg->status = as->done_status;
1435         spi_finalize_current_message(spi->master);
1436
1437         return ret;
1438 }
1439
1440 static void atmel_spi_cleanup(struct spi_device *spi)
1441 {
1442         struct atmel_spi_device *asd = spi->controller_state;
1443
1444         if (!asd)
1445                 return;
1446
1447         spi->controller_state = NULL;
1448         kfree(asd);
1449 }
1450
1451 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1452 {
1453         return spi_readl(as, VERSION) & 0x00000fff;
1454 }
1455
1456 static void atmel_get_caps(struct atmel_spi *as)
1457 {
1458         unsigned int version;
1459
1460         version = atmel_get_version(as);
1461
1462         as->caps.is_spi2 = version > 0x121;
1463         as->caps.has_wdrbt = version >= 0x210;
1464         as->caps.has_dma_support = version >= 0x212;
1465         as->caps.has_pdc_support = version < 0x212;
1466 }
1467
1468 static void atmel_spi_init(struct atmel_spi *as)
1469 {
1470         spi_writel(as, CR, SPI_BIT(SWRST));
1471         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1472
1473         /* It is recommended to enable FIFOs first thing after reset */
1474         if (as->fifo_size)
1475                 spi_writel(as, CR, SPI_BIT(FIFOEN));
1476
1477         if (as->caps.has_wdrbt) {
1478                 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1479                                 | SPI_BIT(MSTR));
1480         } else {
1481                 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1482         }
1483
1484         if (as->use_pdc)
1485                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1486         spi_writel(as, CR, SPI_BIT(SPIEN));
1487 }
1488
1489 static int atmel_spi_probe(struct platform_device *pdev)
1490 {
1491         struct resource         *regs;
1492         int                     irq;
1493         struct clk              *clk;
1494         int                     ret;
1495         struct spi_master       *master;
1496         struct atmel_spi        *as;
1497
1498         /* Select default pin state */
1499         pinctrl_pm_select_default_state(&pdev->dev);
1500
1501         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1502         if (!regs)
1503                 return -ENXIO;
1504
1505         irq = platform_get_irq(pdev, 0);
1506         if (irq < 0)
1507                 return irq;
1508
1509         clk = devm_clk_get(&pdev->dev, "spi_clk");
1510         if (IS_ERR(clk))
1511                 return PTR_ERR(clk);
1512
1513         /* setup spi core then atmel-specific driver state */
1514         ret = -ENOMEM;
1515         master = spi_alloc_master(&pdev->dev, sizeof(*as));
1516         if (!master)
1517                 goto out_free;
1518
1519         /* the spi->mode bits understood by this driver: */
1520         master->use_gpio_descriptors = true;
1521         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1522         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1523         master->dev.of_node = pdev->dev.of_node;
1524         master->bus_num = pdev->id;
1525         master->num_chipselect = master->dev.of_node ? 0 : 4;
1526         master->setup = atmel_spi_setup;
1527         master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
1528         master->transfer_one_message = atmel_spi_transfer_one_message;
1529         master->cleanup = atmel_spi_cleanup;
1530         master->auto_runtime_pm = true;
1531         master->max_dma_len = SPI_MAX_DMA_XFER;
1532         master->can_dma = atmel_spi_can_dma;
1533         platform_set_drvdata(pdev, master);
1534
1535         as = spi_master_get_devdata(master);
1536
1537         spin_lock_init(&as->lock);
1538
1539         as->pdev = pdev;
1540         as->regs = devm_ioremap_resource(&pdev->dev, regs);
1541         if (IS_ERR(as->regs)) {
1542                 ret = PTR_ERR(as->regs);
1543                 goto out_unmap_regs;
1544         }
1545         as->phybase = regs->start;
1546         as->irq = irq;
1547         as->clk = clk;
1548
1549         init_completion(&as->xfer_completion);
1550
1551         atmel_get_caps(as);
1552
1553         /*
1554          * If there are chip selects in the device tree, those will be
1555          * discovered by the SPI core when registering the SPI master
1556          * and assigned to each SPI device.
1557          */
1558         as->use_cs_gpios = true;
1559         if (atmel_spi_is_v2(as) &&
1560             pdev->dev.of_node &&
1561             !of_get_property(pdev->dev.of_node, "cs-gpios", NULL)) {
1562                 as->use_cs_gpios = false;
1563                 master->num_chipselect = 4;
1564         }
1565
1566         as->use_dma = false;
1567         as->use_pdc = false;
1568         if (as->caps.has_dma_support) {
1569                 ret = atmel_spi_configure_dma(master, as);
1570                 if (ret == 0) {
1571                         as->use_dma = true;
1572                 } else if (ret == -EPROBE_DEFER) {
1573                         return ret;
1574                 }
1575         } else if (as->caps.has_pdc_support) {
1576                 as->use_pdc = true;
1577         }
1578
1579         if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1580                 as->addr_rx_bbuf = dma_alloc_coherent(&pdev->dev,
1581                                                       SPI_MAX_DMA_XFER,
1582                                                       &as->dma_addr_rx_bbuf,
1583                                                       GFP_KERNEL | GFP_DMA);
1584                 if (!as->addr_rx_bbuf) {
1585                         as->use_dma = false;
1586                 } else {
1587                         as->addr_tx_bbuf = dma_alloc_coherent(&pdev->dev,
1588                                         SPI_MAX_DMA_XFER,
1589                                         &as->dma_addr_tx_bbuf,
1590                                         GFP_KERNEL | GFP_DMA);
1591                         if (!as->addr_tx_bbuf) {
1592                                 as->use_dma = false;
1593                                 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1594                                                   as->addr_rx_bbuf,
1595                                                   as->dma_addr_rx_bbuf);
1596                         }
1597                 }
1598                 if (!as->use_dma)
1599                         dev_info(master->dev.parent,
1600                                  "  can not allocate dma coherent memory\n");
1601         }
1602
1603         if (as->caps.has_dma_support && !as->use_dma)
1604                 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1605
1606         if (as->use_pdc) {
1607                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1608                                         0, dev_name(&pdev->dev), master);
1609         } else {
1610                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1611                                         0, dev_name(&pdev->dev), master);
1612         }
1613         if (ret)
1614                 goto out_unmap_regs;
1615
1616         /* Initialize the hardware */
1617         ret = clk_prepare_enable(clk);
1618         if (ret)
1619                 goto out_free_irq;
1620
1621         as->spi_clk = clk_get_rate(clk);
1622
1623         as->fifo_size = 0;
1624         if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1625                                   &as->fifo_size)) {
1626                 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
1627         }
1628
1629         atmel_spi_init(as);
1630
1631         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1632         pm_runtime_use_autosuspend(&pdev->dev);
1633         pm_runtime_set_active(&pdev->dev);
1634         pm_runtime_enable(&pdev->dev);
1635
1636         ret = devm_spi_register_master(&pdev->dev, master);
1637         if (ret)
1638                 goto out_free_dma;
1639
1640         /* go! */
1641         dev_info(&pdev->dev, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n",
1642                         atmel_get_version(as), (unsigned long)regs->start,
1643                         irq);
1644
1645         return 0;
1646
1647 out_free_dma:
1648         pm_runtime_disable(&pdev->dev);
1649         pm_runtime_set_suspended(&pdev->dev);
1650
1651         if (as->use_dma)
1652                 atmel_spi_release_dma(master);
1653
1654         spi_writel(as, CR, SPI_BIT(SWRST));
1655         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1656         clk_disable_unprepare(clk);
1657 out_free_irq:
1658 out_unmap_regs:
1659 out_free:
1660         spi_master_put(master);
1661         return ret;
1662 }
1663
1664 static int atmel_spi_remove(struct platform_device *pdev)
1665 {
1666         struct spi_master       *master = platform_get_drvdata(pdev);
1667         struct atmel_spi        *as = spi_master_get_devdata(master);
1668
1669         pm_runtime_get_sync(&pdev->dev);
1670
1671         /* reset the hardware and block queue progress */
1672         if (as->use_dma) {
1673                 atmel_spi_stop_dma(master);
1674                 atmel_spi_release_dma(master);
1675                 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1676                         dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1677                                           as->addr_tx_bbuf,
1678                                           as->dma_addr_tx_bbuf);
1679                         dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1680                                           as->addr_rx_bbuf,
1681                                           as->dma_addr_rx_bbuf);
1682                 }
1683         }
1684
1685         spin_lock_irq(&as->lock);
1686         spi_writel(as, CR, SPI_BIT(SWRST));
1687         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1688         spi_readl(as, SR);
1689         spin_unlock_irq(&as->lock);
1690
1691         clk_disable_unprepare(as->clk);
1692
1693         pm_runtime_put_noidle(&pdev->dev);
1694         pm_runtime_disable(&pdev->dev);
1695
1696         return 0;
1697 }
1698
1699 #ifdef CONFIG_PM
1700 static int atmel_spi_runtime_suspend(struct device *dev)
1701 {
1702         struct spi_master *master = dev_get_drvdata(dev);
1703         struct atmel_spi *as = spi_master_get_devdata(master);
1704
1705         clk_disable_unprepare(as->clk);
1706         pinctrl_pm_select_sleep_state(dev);
1707
1708         return 0;
1709 }
1710
1711 static int atmel_spi_runtime_resume(struct device *dev)
1712 {
1713         struct spi_master *master = dev_get_drvdata(dev);
1714         struct atmel_spi *as = spi_master_get_devdata(master);
1715
1716         pinctrl_pm_select_default_state(dev);
1717
1718         return clk_prepare_enable(as->clk);
1719 }
1720
1721 #ifdef CONFIG_PM_SLEEP
1722 static int atmel_spi_suspend(struct device *dev)
1723 {
1724         struct spi_master *master = dev_get_drvdata(dev);
1725         int ret;
1726
1727         /* Stop the queue running */
1728         ret = spi_master_suspend(master);
1729         if (ret)
1730                 return ret;
1731
1732         if (!pm_runtime_suspended(dev))
1733                 atmel_spi_runtime_suspend(dev);
1734
1735         return 0;
1736 }
1737
1738 static int atmel_spi_resume(struct device *dev)
1739 {
1740         struct spi_master *master = dev_get_drvdata(dev);
1741         struct atmel_spi *as = spi_master_get_devdata(master);
1742         int ret;
1743
1744         ret = clk_prepare_enable(as->clk);
1745         if (ret)
1746                 return ret;
1747
1748         atmel_spi_init(as);
1749
1750         clk_disable_unprepare(as->clk);
1751
1752         if (!pm_runtime_suspended(dev)) {
1753                 ret = atmel_spi_runtime_resume(dev);
1754                 if (ret)
1755                         return ret;
1756         }
1757
1758         /* Start the queue running */
1759         return spi_master_resume(master);
1760 }
1761 #endif
1762
1763 static const struct dev_pm_ops atmel_spi_pm_ops = {
1764         SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1765         SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1766                            atmel_spi_runtime_resume, NULL)
1767 };
1768 #define ATMEL_SPI_PM_OPS        (&atmel_spi_pm_ops)
1769 #else
1770 #define ATMEL_SPI_PM_OPS        NULL
1771 #endif
1772
1773 #if defined(CONFIG_OF)
1774 static const struct of_device_id atmel_spi_dt_ids[] = {
1775         { .compatible = "atmel,at91rm9200-spi" },
1776         { /* sentinel */ }
1777 };
1778
1779 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1780 #endif
1781
1782 static struct platform_driver atmel_spi_driver = {
1783         .driver         = {
1784                 .name   = "atmel_spi",
1785                 .pm     = ATMEL_SPI_PM_OPS,
1786                 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
1787         },
1788         .probe          = atmel_spi_probe,
1789         .remove         = atmel_spi_remove,
1790 };
1791 module_platform_driver(atmel_spi_driver);
1792
1793 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1794 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1795 MODULE_LICENSE("GPL");
1796 MODULE_ALIAS("platform:atmel_spi");