drivers/spi/spi-atmel.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for Atmel AT32 and AT91 SPI Controllers
   4  *
   5  * Copyright (C) 2006 Atmel Corporation
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/clk.h>
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/delay.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/err.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/spi/spi.h>
  18 #include <linux/slab.h>
  19 #include <linux/of.h>
  20
  21 #include <linux/io.h>
  22 #include <linux/gpio/consumer.h>
  23 #include <linux/pinctrl/consumer.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/iopoll.h>
  26 #include <trace/events/spi.h>
  27
  28 /* SPI register offsets */
  29 #define SPI_CR                                  0x0000
  30 #define SPI_MR                                  0x0004
  31 #define SPI_RDR                                 0x0008
  32 #define SPI_TDR                                 0x000c
  33 #define SPI_SR                                  0x0010
  34 #define SPI_IER                                 0x0014
  35 #define SPI_IDR                                 0x0018
  36 #define SPI_IMR                                 0x001c
  37 #define SPI_CSR0                                0x0030
  38 #define SPI_CSR1                                0x0034
  39 #define SPI_CSR2                                0x0038
  40 #define SPI_CSR3                                0x003c
  41 #define SPI_FMR                                 0x0040
  42 #define SPI_FLR                                 0x0044
  43 #define SPI_VERSION                             0x00fc
  44 #define SPI_RPR                                 0x0100
  45 #define SPI_RCR                                 0x0104
  46 #define SPI_TPR                                 0x0108
  47 #define SPI_TCR                                 0x010c
  48 #define SPI_RNPR                                0x0110
  49 #define SPI_RNCR                                0x0114
  50 #define SPI_TNPR                                0x0118
  51 #define SPI_TNCR                                0x011c
  52 #define SPI_PTCR                                0x0120
  53 #define SPI_PTSR                                0x0124
  54
  55 /* Bitfields in CR */
  56 #define SPI_SPIEN_OFFSET                        0
  57 #define SPI_SPIEN_SIZE                          1
  58 #define SPI_SPIDIS_OFFSET                       1
  59 #define SPI_SPIDIS_SIZE                         1
  60 #define SPI_SWRST_OFFSET                        7
  61 #define SPI_SWRST_SIZE                          1
  62 #define SPI_LASTXFER_OFFSET                     24
  63 #define SPI_LASTXFER_SIZE                       1
  64 #define SPI_TXFCLR_OFFSET                       16
  65 #define SPI_TXFCLR_SIZE                         1
  66 #define SPI_RXFCLR_OFFSET                       17
  67 #define SPI_RXFCLR_SIZE                         1
  68 #define SPI_FIFOEN_OFFSET                       30
  69 #define SPI_FIFOEN_SIZE                         1
  70 #define SPI_FIFODIS_OFFSET                      31
  71 #define SPI_FIFODIS_SIZE                        1
  72
  73 /* Bitfields in MR */
  74 #define SPI_MSTR_OFFSET                         0
  75 #define SPI_MSTR_SIZE                           1
  76 #define SPI_PS_OFFSET                           1
  77 #define SPI_PS_SIZE                             1
  78 #define SPI_PCSDEC_OFFSET                       2
  79 #define SPI_PCSDEC_SIZE                         1
  80 #define SPI_FDIV_OFFSET                         3
  81 #define SPI_FDIV_SIZE                           1
  82 #define SPI_MODFDIS_OFFSET                      4
  83 #define SPI_MODFDIS_SIZE                        1
  84 #define SPI_WDRBT_OFFSET                        5
  85 #define SPI_WDRBT_SIZE                          1
  86 #define SPI_LLB_OFFSET                          7
  87 #define SPI_LLB_SIZE                            1
  88 #define SPI_PCS_OFFSET                          16
  89 #define SPI_PCS_SIZE                            4
  90 #define SPI_DLYBCS_OFFSET                       24
  91 #define SPI_DLYBCS_SIZE                         8
  92
  93 /* Bitfields in RDR */
  94 #define SPI_RD_OFFSET                           0
  95 #define SPI_RD_SIZE                             16
  96
  97 /* Bitfields in TDR */
  98 #define SPI_TD_OFFSET                           0
  99 #define SPI_TD_SIZE                             16
 100
 101 /* Bitfields in SR */
 102 #define SPI_RDRF_OFFSET                         0
 103 #define SPI_RDRF_SIZE                           1
 104 #define SPI_TDRE_OFFSET                         1
 105 #define SPI_TDRE_SIZE                           1
 106 #define SPI_MODF_OFFSET                         2
 107 #define SPI_MODF_SIZE                           1
 108 #define SPI_OVRES_OFFSET                        3
 109 #define SPI_OVRES_SIZE                          1
 110 #define SPI_ENDRX_OFFSET                        4
 111 #define SPI_ENDRX_SIZE                          1
 112 #define SPI_ENDTX_OFFSET                        5
 113 #define SPI_ENDTX_SIZE                          1
 114 #define SPI_RXBUFF_OFFSET                       6
 115 #define SPI_RXBUFF_SIZE                         1
 116 #define SPI_TXBUFE_OFFSET                       7
 117 #define SPI_TXBUFE_SIZE                         1
 118 #define SPI_NSSR_OFFSET                         8
 119 #define SPI_NSSR_SIZE                           1
 120 #define SPI_TXEMPTY_OFFSET                      9
 121 #define SPI_TXEMPTY_SIZE                        1
 122 #define SPI_SPIENS_OFFSET                       16
 123 #define SPI_SPIENS_SIZE                         1
 124 #define SPI_TXFEF_OFFSET                        24
 125 #define SPI_TXFEF_SIZE                          1
 126 #define SPI_TXFFF_OFFSET                        25
 127 #define SPI_TXFFF_SIZE                          1
 128 #define SPI_TXFTHF_OFFSET                       26
 129 #define SPI_TXFTHF_SIZE                         1
 130 #define SPI_RXFEF_OFFSET                        27
 131 #define SPI_RXFEF_SIZE                          1
 132 #define SPI_RXFFF_OFFSET                        28
 133 #define SPI_RXFFF_SIZE                          1
 134 #define SPI_RXFTHF_OFFSET                       29
 135 #define SPI_RXFTHF_SIZE                         1
 136 #define SPI_TXFPTEF_OFFSET                      30
 137 #define SPI_TXFPTEF_SIZE                        1
 138 #define SPI_RXFPTEF_OFFSET                      31
 139 #define SPI_RXFPTEF_SIZE                        1
 140
 141 /* Bitfields in CSR0 */
 142 #define SPI_CPOL_OFFSET                         0
 143 #define SPI_CPOL_SIZE                           1
 144 #define SPI_NCPHA_OFFSET                        1
 145 #define SPI_NCPHA_SIZE                          1
 146 #define SPI_CSAAT_OFFSET                        3
 147 #define SPI_CSAAT_SIZE                          1
 148 #define SPI_BITS_OFFSET                         4
 149 #define SPI_BITS_SIZE                           4
 150 #define SPI_SCBR_OFFSET                         8
 151 #define SPI_SCBR_SIZE                           8
 152 #define SPI_DLYBS_OFFSET                        16
 153 #define SPI_DLYBS_SIZE                          8
 154 #define SPI_DLYBCT_OFFSET                       24
 155 #define SPI_DLYBCT_SIZE                         8
 156
 157 /* Bitfields in RCR */
 158 #define SPI_RXCTR_OFFSET                        0
 159 #define SPI_RXCTR_SIZE                          16
 160
 161 /* Bitfields in TCR */
 162 #define SPI_TXCTR_OFFSET                        0
 163 #define SPI_TXCTR_SIZE                          16
 164
 165 /* Bitfields in RNCR */
 166 #define SPI_RXNCR_OFFSET                        0
 167 #define SPI_RXNCR_SIZE                          16
 168
 169 /* Bitfields in TNCR */
 170 #define SPI_TXNCR_OFFSET                        0
 171 #define SPI_TXNCR_SIZE                          16
 172
 173 /* Bitfields in PTCR */
 174 #define SPI_RXTEN_OFFSET                        0
 175 #define SPI_RXTEN_SIZE                          1
 176 #define SPI_RXTDIS_OFFSET                       1
 177 #define SPI_RXTDIS_SIZE                         1
 178 #define SPI_TXTEN_OFFSET                        8
 179 #define SPI_TXTEN_SIZE                          1
 180 #define SPI_TXTDIS_OFFSET                       9
 181 #define SPI_TXTDIS_SIZE                         1
 182
 183 /* Bitfields in FMR */
 184 #define SPI_TXRDYM_OFFSET                       0
 185 #define SPI_TXRDYM_SIZE                         2
 186 #define SPI_RXRDYM_OFFSET                       4
 187 #define SPI_RXRDYM_SIZE                         2
 188 #define SPI_TXFTHRES_OFFSET                     16
 189 #define SPI_TXFTHRES_SIZE                       6
 190 #define SPI_RXFTHRES_OFFSET                     24
 191 #define SPI_RXFTHRES_SIZE                       6
 192
 193 /* Bitfields in FLR */
 194 #define SPI_TXFL_OFFSET                         0
 195 #define SPI_TXFL_SIZE                           6
 196 #define SPI_RXFL_OFFSET                         16
 197 #define SPI_RXFL_SIZE                           6
 198
 199 /* Constants for BITS */
 200 #define SPI_BITS_8_BPT                          0
 201 #define SPI_BITS_9_BPT                          1
 202 #define SPI_BITS_10_BPT                         2
 203 #define SPI_BITS_11_BPT                         3
 204 #define SPI_BITS_12_BPT                         4
 205 #define SPI_BITS_13_BPT                         5
 206 #define SPI_BITS_14_BPT                         6
 207 #define SPI_BITS_15_BPT                         7
 208 #define SPI_BITS_16_BPT                         8
 209 #define SPI_ONE_DATA                            0
 210 #define SPI_TWO_DATA                            1
 211 #define SPI_FOUR_DATA                           2
 212
 213 /* Bit manipulation macros */
 214 #define SPI_BIT(name) \
 215         (1 << SPI_##name##_OFFSET)
 216 #define SPI_BF(name, value) \
 217         (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
 218 #define SPI_BFEXT(name, value) \
 219         (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
 220 #define SPI_BFINS(name, value, old) \
 221         (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
 222           | SPI_BF(name, value))
 223
 224 /* Register access macros */
 225 #define spi_readl(port, reg) \
 226         readl_relaxed((port)->regs + SPI_##reg)
 227 #define spi_writel(port, reg, value) \
 228         writel_relaxed((value), (port)->regs + SPI_##reg)
 229 #define spi_writew(port, reg, value) \
 230         writew_relaxed((value), (port)->regs + SPI_##reg)
 231
 232 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 233  * cache operations; better heuristics consider wordsize and bitrate.
 234  */
 235 #define DMA_MIN_BYTES   16
 236
 237 #define SPI_DMA_MIN_TIMEOUT     (msecs_to_jiffies(1000))
 238 #define SPI_DMA_TIMEOUT_PER_10K (msecs_to_jiffies(4))
 239
 240 #define AUTOSUSPEND_TIMEOUT     2000
 241
 242 struct atmel_spi_caps {
 243         bool    is_spi2;
 244         bool    has_wdrbt;
 245         bool    has_dma_support;
 246         bool    has_pdc_support;
 247 };
 248
 249 /*
 250  * The core SPI transfer engine just talks to a register bank to set up
 251  * DMA transfers; transfer queue progress is driven by IRQs.  The clock
 252  * framework provides the base clock, subdivided for each spi_device.
 253  */
 254 struct atmel_spi {
 255         spinlock_t              lock;
 256         unsigned long           flags;
 257
 258         phys_addr_t             phybase;
 259         void __iomem            *regs;
 260         int                     irq;
 261         struct clk              *clk;
 262         struct platform_device  *pdev;
 263         unsigned long           spi_clk;
 264
 265         struct spi_transfer     *current_transfer;
 266         int                     current_remaining_bytes;
 267         int                     done_status;
 268         dma_addr_t              dma_addr_rx_bbuf;
 269         dma_addr_t              dma_addr_tx_bbuf;
 270         void                    *addr_rx_bbuf;
 271         void                    *addr_tx_bbuf;
 272
 273         struct completion       xfer_completion;
 274
 275         struct atmel_spi_caps   caps;
 276
 277         bool                    use_dma;
 278         bool                    use_pdc;
 279
 280         bool                    keep_cs;
 281
 282         u32                     fifo_size;
 283         bool                    last_polarity;
 284         u8                      native_cs_free;
 285         u8                      native_cs_for_gpio;
 286 };
 287
 288 /* Controller-specific per-slave state */
 289 struct atmel_spi_device {
 290         u32                     csr;
 291 };
 292
 293 #define SPI_MAX_DMA_XFER        65535 /* true for both PDC and DMA */
 294 #define INVALID_DMA_ADDRESS     0xffffffff
 295
 296 /*
 297  * This frequency can be anything supported by the controller, but to avoid
 298  * unnecessary delay, the highest possible frequency is chosen.
 299  *
 300  * This frequency is the highest possible which is not interfering with other
 301  * chip select registers (see Note for Serial Clock Bit Rate configuration in
 302  * Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16, page 1283)
 303  */
 304 #define DUMMY_MSG_FREQUENCY     0x02
 305 /*
 306  * 8 bits is the minimum data the controller is capable of sending.
 307  *
 308  * This message can be anything as it should not be treated by any SPI device.
 309  */
 310 #define DUMMY_MSG               0xAA
 311
 312 /*
 313  * Version 2 of the SPI controller has
 314  *  - CR.LASTXFER
 315  *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
 316  *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
 317  *  - SPI_CSRx.CSAAT
 318  *  - SPI_CSRx.SBCR allows faster clocking
 319  */
 320 static bool atmel_spi_is_v2(struct atmel_spi *as)
 321 {
 322         return as->caps.is_spi2;
 323 }
 324
 325 /*
 326  * Send a dummy message.
 327  *
 328  * This is sometimes needed when using a CS GPIO to force clock transition when
 329  * switching between devices with different polarities.
 330  */
 331 static void atmel_spi_send_dummy(struct atmel_spi *as, struct spi_device *spi, int chip_select)
 332 {
 333         u32 status;
 334         u32 csr;
 335
 336         /*
 337          * Set a clock frequency to allow sending message on SPI bus.
 338          * The frequency here can be anything, but is needed for
 339          * the controller to send the data.
 340          */
 341         csr = spi_readl(as, CSR0 + 4 * chip_select);
 342         csr = SPI_BFINS(SCBR, DUMMY_MSG_FREQUENCY, csr);
 343         spi_writel(as, CSR0 + 4 * chip_select, csr);
 344
 345         /*
 346          * Read all data coming from SPI bus, needed to be able to send
 347          * the message.
 348          */
 349         spi_readl(as, RDR);
 350         while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
 351                 spi_readl(as, RDR);
 352                 cpu_relax();
 353         }
 354
 355         spi_writel(as, TDR, DUMMY_MSG);
 356
 357         readl_poll_timeout_atomic(as->regs + SPI_SR, status,
 358                                   (status & SPI_BIT(TXEMPTY)), 1, 1000);
 359 }
 360
 361
 362 /*
 363  * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
 364  * they assume that spi slave device state will not change on deselect, so
 365  * that automagic deselection is OK.  ("NPCSx rises if no data is to be
 366  * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
 367  * controllers have CSAAT and friends.
 368  *
 369  * Even controller newer than ar91rm9200, using GPIOs can make sens as
 370  * it lets us support active-high chipselects despite the controller's
 371  * belief that only active-low devices/systems exists.
 372  *
 373  * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
 374  * right when driven with GPIO.  ("Mode Fault does not allow more than one
 375  * Master on Chip Select 0.")  No workaround exists for that ... so for
 376  * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
 377  * and (c) will trigger that first erratum in some cases.
 378  *
 379  * When changing the clock polarity, the SPI controller waits for the next
 380  * transmission to enforce the default clock state. This may be an issue when
 381  * using a GPIO as Chip Select: the clock level is applied only when the first
 382  * packet is sent, once the CS has already been asserted. The workaround is to
 383  * avoid this by sending a first (dummy) message before toggling the CS state.
 384  */
 385 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
 386 {
 387         struct atmel_spi_device *asd = spi->controller_state;
 388         bool new_polarity;
 389         int chip_select;
 390         u32 mr;
 391
 392         if (spi_get_csgpiod(spi, 0))
 393                 chip_select = as->native_cs_for_gpio;
 394         else
 395                 chip_select = spi_get_chipselect(spi, 0);
 396
 397         if (atmel_spi_is_v2(as)) {
 398                 spi_writel(as, CSR0 + 4 * chip_select, asd->csr);
 399                 /* For the low SPI version, there is a issue that PDC transfer
 400                  * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
 401                  */
 402                 spi_writel(as, CSR0, asd->csr);
 403                 if (as->caps.has_wdrbt) {
 404                         spi_writel(as, MR,
 405                                         SPI_BF(PCS, ~(0x01 << chip_select))
 406                                         | SPI_BIT(WDRBT)
 407                                         | SPI_BIT(MODFDIS)
 408                                         | SPI_BIT(MSTR));
 409                 } else {
 410                         spi_writel(as, MR,
 411                                         SPI_BF(PCS, ~(0x01 << chip_select))
 412                                         | SPI_BIT(MODFDIS)
 413                                         | SPI_BIT(MSTR));
 414                 }
 415
 416                 mr = spi_readl(as, MR);
 417
 418                 /*
 419                  * Ensures the clock polarity is valid before we actually
 420                  * assert the CS to avoid spurious clock edges to be
 421                  * processed by the spi devices.
 422                  */
 423                 if (spi_get_csgpiod(spi, 0)) {
 424                         new_polarity = (asd->csr & SPI_BIT(CPOL)) != 0;
 425                         if (new_polarity != as->last_polarity) {
 426                                 /*
 427                                  * Need to disable the GPIO before sending the dummy
 428                                  * message because it is already set by the spi core.
 429                                  */
 430                                 gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), 0);
 431                                 atmel_spi_send_dummy(as, spi, chip_select);
 432                                 as->last_polarity = new_polarity;
 433                                 gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), 1);
 434                         }
 435                 }
 436         } else {
 437                 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
 438                 int i;
 439                 u32 csr;
 440
 441                 /* Make sure clock polarity is correct */
 442                 for (i = 0; i < spi->controller->num_chipselect; i++) {
 443                         csr = spi_readl(as, CSR0 + 4 * i);
 444                         if ((csr ^ cpol) & SPI_BIT(CPOL))
 445                                 spi_writel(as, CSR0 + 4 * i,
 446                                                 csr ^ SPI_BIT(CPOL));
 447                 }
 448
 449                 mr = spi_readl(as, MR);
 450                 mr = SPI_BFINS(PCS, ~(1 << chip_select), mr);
 451                 spi_writel(as, MR, mr);
 452         }
 453
 454         dev_dbg(&spi->dev, "activate NPCS, mr %08x\n", mr);
 455 }
 456
 457 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
 458 {
 459         int chip_select;
 460         u32 mr;
 461
 462         if (spi_get_csgpiod(spi, 0))
 463                 chip_select = as->native_cs_for_gpio;
 464         else
 465                 chip_select = spi_get_chipselect(spi, 0);
 466
 467         /* only deactivate *this* device; sometimes transfers to
 468          * another device may be active when this routine is called.
 469          */
 470         mr = spi_readl(as, MR);
 471         if (~SPI_BFEXT(PCS, mr) & (1 << chip_select)) {
 472                 mr = SPI_BFINS(PCS, 0xf, mr);
 473                 spi_writel(as, MR, mr);
 474         }
 475
 476         dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr);
 477
 478         if (!spi_get_csgpiod(spi, 0))
 479                 spi_writel(as, CR, SPI_BIT(LASTXFER));
 480 }
 481
 482 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
 483 {
 484         spin_lock_irqsave(&as->lock, as->flags);
 485 }
 486
 487 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
 488 {
 489         spin_unlock_irqrestore(&as->lock, as->flags);
 490 }
 491
 492 static inline bool atmel_spi_is_vmalloc_xfer(struct spi_transfer *xfer)
 493 {
 494         return is_vmalloc_addr(xfer->tx_buf) || is_vmalloc_addr(xfer->rx_buf);
 495 }
 496
 497 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
 498                                 struct spi_transfer *xfer)
 499 {
 500         return as->use_dma && xfer->len >= DMA_MIN_BYTES;
 501 }
 502
 503 static bool atmel_spi_can_dma(struct spi_controller *host,
 504                               struct spi_device *spi,
 505                               struct spi_transfer *xfer)
 506 {
 507         struct atmel_spi *as = spi_controller_get_devdata(host);
 508
 509         if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5))
 510                 return atmel_spi_use_dma(as, xfer) &&
 511                         !atmel_spi_is_vmalloc_xfer(xfer);
 512         else
 513                 return atmel_spi_use_dma(as, xfer);
 514
 515 }
 516
 517 static int atmel_spi_dma_slave_config(struct atmel_spi *as, u8 bits_per_word)
 518 {
 519         struct spi_controller *host = platform_get_drvdata(as->pdev);
 520         struct dma_slave_config slave_config;
 521         int err = 0;
 522
 523         if (bits_per_word > 8) {
 524                 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 525                 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 526         } else {
 527                 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 528                 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 529         }
 530
 531         slave_config.dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
 532         slave_config.src_addr = (dma_addr_t)as->phybase + SPI_RDR;
 533         slave_config.src_maxburst = 1;
 534         slave_config.dst_maxburst = 1;
 535         slave_config.device_fc = false;
 536
 537         /*
 538          * This driver uses fixed peripheral select mode (PS bit set to '0' in
 539          * the Mode Register).
 540          * So according to the datasheet, when FIFOs are available (and
 541          * enabled), the Transmit FIFO operates in Multiple Data Mode.
 542          * In this mode, up to 2 data, not 4, can be written into the Transmit
 543          * Data Register in a single access.
 544          * However, the first data has to be written into the lowest 16 bits and
 545          * the second data into the highest 16 bits of the Transmit
 546          * Data Register. For 8bit data (the most frequent case), it would
 547          * require to rework tx_buf so each data would actually fit 16 bits.
 548          * So we'd rather write only one data at the time. Hence the transmit
 549          * path works the same whether FIFOs are available (and enabled) or not.
 550          */
 551         if (dmaengine_slave_config(host->dma_tx, &slave_config)) {
 552                 dev_err(&as->pdev->dev,
 553                         "failed to configure tx dma channel\n");
 554                 err = -EINVAL;
 555         }
 556
 557         /*
 558          * This driver configures the spi controller for host mode (MSTR bit
 559          * set to '1' in the Mode Register).
 560          * So according to the datasheet, when FIFOs are available (and
 561          * enabled), the Receive FIFO operates in Single Data Mode.
 562          * So the receive path works the same whether FIFOs are available (and
 563          * enabled) or not.
 564          */
 565         if (dmaengine_slave_config(host->dma_rx, &slave_config)) {
 566                 dev_err(&as->pdev->dev,
 567                         "failed to configure rx dma channel\n");
 568                 err = -EINVAL;
 569         }
 570
 571         return err;
 572 }
 573
 574 static int atmel_spi_configure_dma(struct spi_controller *host,
 575                                    struct atmel_spi *as)
 576 {
 577         struct device *dev = &as->pdev->dev;
 578         int err;
 579
 580         host->dma_tx = dma_request_chan(dev, "tx");
 581         if (IS_ERR(host->dma_tx)) {
 582                 err = PTR_ERR(host->dma_tx);
 583                 dev_dbg(dev, "No TX DMA channel, DMA is disabled\n");
 584                 goto error_clear;
 585         }
 586
 587         host->dma_rx = dma_request_chan(dev, "rx");
 588         if (IS_ERR(host->dma_rx)) {
 589                 err = PTR_ERR(host->dma_rx);
 590                 /*
 591                  * No reason to check EPROBE_DEFER here since we have already
 592                  * requested tx channel.
 593                  */
 594                 dev_dbg(dev, "No RX DMA channel, DMA is disabled\n");
 595                 goto error;
 596         }
 597
 598         err = atmel_spi_dma_slave_config(as, 8);
 599         if (err)
 600                 goto error;
 601
 602         dev_info(&as->pdev->dev,
 603                         "Using %s (tx) and %s (rx) for DMA transfers\n",
 604                         dma_chan_name(host->dma_tx),
 605                         dma_chan_name(host->dma_rx));
 606
 607         return 0;
 608 error:
 609         if (!IS_ERR(host->dma_rx))
 610                 dma_release_channel(host->dma_rx);
 611         if (!IS_ERR(host->dma_tx))
 612                 dma_release_channel(host->dma_tx);
 613 error_clear:
 614         host->dma_tx = host->dma_rx = NULL;
 615         return err;
 616 }
 617
 618 static void atmel_spi_stop_dma(struct spi_controller *host)
 619 {
 620         if (host->dma_rx)
 621                 dmaengine_terminate_all(host->dma_rx);
 622         if (host->dma_tx)
 623                 dmaengine_terminate_all(host->dma_tx);
 624 }
 625
 626 static void atmel_spi_release_dma(struct spi_controller *host)
 627 {
 628         if (host->dma_rx) {
 629                 dma_release_channel(host->dma_rx);
 630                 host->dma_rx = NULL;
 631         }
 632         if (host->dma_tx) {
 633                 dma_release_channel(host->dma_tx);
 634                 host->dma_tx = NULL;
 635         }
 636 }
 637
 638 /* This function is called by the DMA driver from tasklet context */
 639 static void dma_callback(void *data)
 640 {
 641         struct spi_controller   *host = data;
 642         struct atmel_spi        *as = spi_controller_get_devdata(host);
 643
 644         if (is_vmalloc_addr(as->current_transfer->rx_buf) &&
 645             IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
 646                 memcpy(as->current_transfer->rx_buf, as->addr_rx_bbuf,
 647                        as->current_transfer->len);
 648         }
 649         complete(&as->xfer_completion);
 650 }
 651
 652 /*
 653  * Next transfer using PIO without FIFO.
 654  */
 655 static void atmel_spi_next_xfer_single(struct spi_controller *host,
 656                                        struct spi_transfer *xfer)
 657 {
 658         struct atmel_spi        *as = spi_controller_get_devdata(host);
 659         unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
 660
 661         dev_vdbg(host->dev.parent, "atmel_spi_next_xfer_pio\n");
 662
 663         /* Make sure data is not remaining in RDR */
 664         spi_readl(as, RDR);
 665         while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
 666                 spi_readl(as, RDR);
 667                 cpu_relax();
 668         }
 669
 670         if (xfer->bits_per_word > 8)
 671                 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
 672         else
 673                 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
 674
 675         dev_dbg(host->dev.parent,
 676                 "  start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
 677                 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
 678                 xfer->bits_per_word);
 679
 680         /* Enable relevant interrupts */
 681         spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
 682 }
 683
 684 /*
 685  * Next transfer using PIO with FIFO.
 686  */
 687 static void atmel_spi_next_xfer_fifo(struct spi_controller *host,
 688                                      struct spi_transfer *xfer)
 689 {
 690         struct atmel_spi *as = spi_controller_get_devdata(host);
 691         u32 current_remaining_data, num_data;
 692         u32 offset = xfer->len - as->current_remaining_bytes;
 693         const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset);
 694         const u8  *bytes = (const u8  *)((u8 *)xfer->tx_buf + offset);
 695         u16 td0, td1;
 696         u32 fifomr;
 697
 698         dev_vdbg(host->dev.parent, "atmel_spi_next_xfer_fifo\n");
 699
 700         /* Compute the number of data to transfer in the current iteration */
 701         current_remaining_data = ((xfer->bits_per_word > 8) ?
 702                                   ((u32)as->current_remaining_bytes >> 1) :
 703                                   (u32)as->current_remaining_bytes);
 704         num_data = min(current_remaining_data, as->fifo_size);
 705
 706         /* Flush RX and TX FIFOs */
 707         spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR));
 708         while (spi_readl(as, FLR))
 709                 cpu_relax();
 710
 711         /* Set RX FIFO Threshold to the number of data to transfer */
 712         fifomr = spi_readl(as, FMR);
 713         spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr));
 714
 715         /* Clear FIFO flags in the Status Register, especially RXFTHF */
 716         (void)spi_readl(as, SR);
 717
 718         /* Fill TX FIFO */
 719         while (num_data >= 2) {
 720                 if (xfer->bits_per_word > 8) {
 721                         td0 = *words++;
 722                         td1 = *words++;
 723                 } else {
 724                         td0 = *bytes++;
 725                         td1 = *bytes++;
 726                 }
 727
 728                 spi_writel(as, TDR, (td1 << 16) | td0);
 729                 num_data -= 2;
 730         }
 731
 732         if (num_data) {
 733                 if (xfer->bits_per_word > 8)
 734                         td0 = *words++;
 735                 else
 736                         td0 = *bytes++;
 737
 738                 spi_writew(as, TDR, td0);
 739                 num_data--;
 740         }
 741
 742         dev_dbg(host->dev.parent,
 743                 "  start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
 744                 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
 745                 xfer->bits_per_word);
 746
 747         /*
 748          * Enable RX FIFO Threshold Flag interrupt to be notified about
 749          * transfer completion.
 750          */
 751         spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
 752 }
 753
 754 /*
 755  * Next transfer using PIO.
 756  */
 757 static void atmel_spi_next_xfer_pio(struct spi_controller *host,
 758                                     struct spi_transfer *xfer)
 759 {
 760         struct atmel_spi *as = spi_controller_get_devdata(host);
 761
 762         if (as->fifo_size)
 763                 atmel_spi_next_xfer_fifo(host, xfer);
 764         else
 765                 atmel_spi_next_xfer_single(host, xfer);
 766 }
 767
 768 /*
 769  * Submit next transfer for DMA.
 770  */
 771 static int atmel_spi_next_xfer_dma_submit(struct spi_controller *host,
 772                                 struct spi_transfer *xfer,
 773                                 u32 *plen)
 774 {
 775         struct atmel_spi        *as = spi_controller_get_devdata(host);
 776         struct dma_chan         *rxchan = host->dma_rx;
 777         struct dma_chan         *txchan = host->dma_tx;
 778         struct dma_async_tx_descriptor *rxdesc;
 779         struct dma_async_tx_descriptor *txdesc;
 780         dma_cookie_t            cookie;
 781
 782         dev_vdbg(host->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
 783
 784         /* Check that the channels are available */
 785         if (!rxchan || !txchan)
 786                 return -ENODEV;
 787
 788
 789         *plen = xfer->len;
 790
 791         if (atmel_spi_dma_slave_config(as, xfer->bits_per_word))
 792                 goto err_exit;
 793
 794         /* Send both scatterlists */
 795         if (atmel_spi_is_vmalloc_xfer(xfer) &&
 796             IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
 797                 rxdesc = dmaengine_prep_slave_single(rxchan,
 798                                                      as->dma_addr_rx_bbuf,
 799                                                      xfer->len,
 800                                                      DMA_DEV_TO_MEM,
 801                                                      DMA_PREP_INTERRUPT |
 802                                                      DMA_CTRL_ACK);
 803         } else {
 804                 rxdesc = dmaengine_prep_slave_sg(rxchan,
 805                                                  xfer->rx_sg.sgl,
 806                                                  xfer->rx_sg.nents,
 807                                                  DMA_DEV_TO_MEM,
 808                                                  DMA_PREP_INTERRUPT |
 809                                                  DMA_CTRL_ACK);
 810         }
 811         if (!rxdesc)
 812                 goto err_dma;
 813
 814         if (atmel_spi_is_vmalloc_xfer(xfer) &&
 815             IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
 816                 memcpy(as->addr_tx_bbuf, xfer->tx_buf, xfer->len);
 817                 txdesc = dmaengine_prep_slave_single(txchan,
 818                                                      as->dma_addr_tx_bbuf,
 819                                                      xfer->len, DMA_MEM_TO_DEV,
 820                                                      DMA_PREP_INTERRUPT |
 821                                                      DMA_CTRL_ACK);
 822         } else {
 823                 txdesc = dmaengine_prep_slave_sg(txchan,
 824                                                  xfer->tx_sg.sgl,
 825                                                  xfer->tx_sg.nents,
 826                                                  DMA_MEM_TO_DEV,
 827                                                  DMA_PREP_INTERRUPT |
 828                                                  DMA_CTRL_ACK);
 829         }
 830         if (!txdesc)
 831                 goto err_dma;
 832
 833         dev_dbg(host->dev.parent,
 834                 "  start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 835                 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
 836                 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
 837
 838         /* Enable relevant interrupts */
 839         spi_writel(as, IER, SPI_BIT(OVRES));
 840
 841         /* Put the callback on the RX transfer only, that should finish last */
 842         rxdesc->callback = dma_callback;
 843         rxdesc->callback_param = host;
 844
 845         /* Submit and fire RX and TX with TX last so we're ready to read! */
 846         cookie = rxdesc->tx_submit(rxdesc);
 847         if (dma_submit_error(cookie))
 848                 goto err_dma;
 849         cookie = txdesc->tx_submit(txdesc);
 850         if (dma_submit_error(cookie))
 851                 goto err_dma;
 852         rxchan->device->device_issue_pending(rxchan);
 853         txchan->device->device_issue_pending(txchan);
 854
 855         return 0;
 856
 857 err_dma:
 858         spi_writel(as, IDR, SPI_BIT(OVRES));
 859         atmel_spi_stop_dma(host);
 860 err_exit:
 861         return -ENOMEM;
 862 }
 863
 864 static void atmel_spi_next_xfer_data(struct spi_controller *host,
 865                                 struct spi_transfer *xfer,
 866                                 dma_addr_t *tx_dma,
 867                                 dma_addr_t *rx_dma,
 868                                 u32 *plen)
 869 {
 870         *rx_dma = xfer->rx_dma + xfer->len - *plen;
 871         *tx_dma = xfer->tx_dma + xfer->len - *plen;
 872         if (*plen > host->max_dma_len)
 873                 *plen = host->max_dma_len;
 874 }
 875
 876 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
 877                                     struct spi_device *spi,
 878                                     struct spi_transfer *xfer)
 879 {
 880         u32                     scbr, csr;
 881         unsigned long           bus_hz;
 882         int chip_select;
 883
 884         if (spi_get_csgpiod(spi, 0))
 885                 chip_select = as->native_cs_for_gpio;
 886         else
 887                 chip_select = spi_get_chipselect(spi, 0);
 888
 889         /* v1 chips start out at half the peripheral bus speed. */
 890         bus_hz = as->spi_clk;
 891         if (!atmel_spi_is_v2(as))
 892                 bus_hz /= 2;
 893
 894         /*
 895          * Calculate the lowest divider that satisfies the
 896          * constraint, assuming div32/fdiv/mbz == 0.
 897          */
 898         scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
 899
 900         /*
 901          * If the resulting divider doesn't fit into the
 902          * register bitfield, we can't satisfy the constraint.
 903          */
 904         if (scbr >= (1 << SPI_SCBR_SIZE)) {
 905                 dev_err(&spi->dev,
 906                         "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
 907                         xfer->speed_hz, scbr, bus_hz/255);
 908                 return -EINVAL;
 909         }
 910         if (scbr == 0) {
 911                 dev_err(&spi->dev,
 912                         "setup: %d Hz too high, scbr %u; max %ld Hz\n",
 913                         xfer->speed_hz, scbr, bus_hz);
 914                 return -EINVAL;
 915         }
 916         csr = spi_readl(as, CSR0 + 4 * chip_select);
 917         csr = SPI_BFINS(SCBR, scbr, csr);
 918         spi_writel(as, CSR0 + 4 * chip_select, csr);
 919         xfer->effective_speed_hz = bus_hz / scbr;
 920
 921         return 0;
 922 }
 923
 924 /*
 925  * Submit next transfer for PDC.
 926  * lock is held, spi irq is blocked
 927  */
 928 static void atmel_spi_pdc_next_xfer(struct spi_controller *host,
 929                                         struct spi_transfer *xfer)
 930 {
 931         struct atmel_spi        *as = spi_controller_get_devdata(host);
 932         u32                     len;
 933         dma_addr_t              tx_dma, rx_dma;
 934
 935         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 936
 937         len = as->current_remaining_bytes;
 938         atmel_spi_next_xfer_data(host, xfer, &tx_dma, &rx_dma, &len);
 939         as->current_remaining_bytes -= len;
 940
 941         spi_writel(as, RPR, rx_dma);
 942         spi_writel(as, TPR, tx_dma);
 943
 944         if (xfer->bits_per_word > 8)
 945                 len >>= 1;
 946         spi_writel(as, RCR, len);
 947         spi_writel(as, TCR, len);
 948
 949         dev_dbg(&host->dev,
 950                 "  start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 951                 xfer, xfer->len, xfer->tx_buf,
 952                 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
 953                 (unsigned long long)xfer->rx_dma);
 954
 955         if (as->current_remaining_bytes) {
 956                 len = as->current_remaining_bytes;
 957                 atmel_spi_next_xfer_data(host, xfer, &tx_dma, &rx_dma, &len);
 958                 as->current_remaining_bytes -= len;
 959
 960                 spi_writel(as, RNPR, rx_dma);
 961                 spi_writel(as, TNPR, tx_dma);
 962
 963                 if (xfer->bits_per_word > 8)
 964                         len >>= 1;
 965                 spi_writel(as, RNCR, len);
 966                 spi_writel(as, TNCR, len);
 967
 968                 dev_dbg(&host->dev,
 969                         "  next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 970                         xfer, xfer->len, xfer->tx_buf,
 971                         (unsigned long long)xfer->tx_dma, xfer->rx_buf,
 972                         (unsigned long long)xfer->rx_dma);
 973         }
 974
 975         /* REVISIT: We're waiting for RXBUFF before we start the next
 976          * transfer because we need to handle some difficult timing
 977          * issues otherwise. If we wait for TXBUFE in one transfer and
 978          * then starts waiting for RXBUFF in the next, it's difficult
 979          * to tell the difference between the RXBUFF interrupt we're
 980          * actually waiting for and the RXBUFF interrupt of the
 981          * previous transfer.
 982          *
 983          * It should be doable, though. Just not now...
 984          */
 985         spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
 986         spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
 987 }
 988
 989 /*
 990  * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
 991  *  - The buffer is either valid for CPU access, else NULL
 992  *  - If the buffer is valid, so is its DMA address
 993  *
 994  * This driver manages the dma address unless message->is_dma_mapped.
 995  */
 996 static int
 997 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
 998 {
 999         struct device   *dev = &as->pdev->dev;
1000
1001         xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
1002         if (xfer->tx_buf) {
1003                 /* tx_buf is a const void* where we need a void * for the dma
1004                  * mapping */
1005                 void *nonconst_tx = (void *)xfer->tx_buf;
1006
1007                 xfer->tx_dma = dma_map_single(dev,
1008                                 nonconst_tx, xfer->len,
1009                                 DMA_TO_DEVICE);
1010                 if (dma_mapping_error(dev, xfer->tx_dma))
1011                         return -ENOMEM;
1012         }
1013         if (xfer->rx_buf) {
1014                 xfer->rx_dma = dma_map_single(dev,
1015                                 xfer->rx_buf, xfer->len,
1016                                 DMA_FROM_DEVICE);
1017                 if (dma_mapping_error(dev, xfer->rx_dma)) {
1018                         if (xfer->tx_buf)
1019                                 dma_unmap_single(dev,
1020                                                 xfer->tx_dma, xfer->len,
1021                                                 DMA_TO_DEVICE);
1022                         return -ENOMEM;
1023                 }
1024         }
1025         return 0;
1026 }
1027
1028 static void atmel_spi_dma_unmap_xfer(struct spi_controller *host,
1029                                      struct spi_transfer *xfer)
1030 {
1031         if (xfer->tx_dma != INVALID_DMA_ADDRESS)
1032                 dma_unmap_single(host->dev.parent, xfer->tx_dma,
1033                                  xfer->len, DMA_TO_DEVICE);
1034         if (xfer->rx_dma != INVALID_DMA_ADDRESS)
1035                 dma_unmap_single(host->dev.parent, xfer->rx_dma,
1036                                  xfer->len, DMA_FROM_DEVICE);
1037 }
1038
1039 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
1040 {
1041         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1042 }
1043
1044 static void
1045 atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
1046 {
1047         u8              *rxp;
1048         u16             *rxp16;
1049         unsigned long   xfer_pos = xfer->len - as->current_remaining_bytes;
1050
1051         if (xfer->bits_per_word > 8) {
1052                 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
1053                 *rxp16 = spi_readl(as, RDR);
1054         } else {
1055                 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
1056                 *rxp = spi_readl(as, RDR);
1057         }
1058         if (xfer->bits_per_word > 8) {
1059                 if (as->current_remaining_bytes > 2)
1060                         as->current_remaining_bytes -= 2;
1061                 else
1062                         as->current_remaining_bytes = 0;
1063         } else {
1064                 as->current_remaining_bytes--;
1065         }
1066 }
1067
1068 static void
1069 atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
1070 {
1071         u32 fifolr = spi_readl(as, FLR);
1072         u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr);
1073         u32 offset = xfer->len - as->current_remaining_bytes;
1074         u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset);
1075         u8  *bytes = (u8  *)((u8 *)xfer->rx_buf + offset);
1076         u16 rd; /* RD field is the lowest 16 bits of RDR */
1077
1078         /* Update the number of remaining bytes to transfer */
1079         num_bytes = ((xfer->bits_per_word > 8) ?
1080                      (num_data << 1) :
1081                      num_data);
1082
1083         if (as->current_remaining_bytes > num_bytes)
1084                 as->current_remaining_bytes -= num_bytes;
1085         else
1086                 as->current_remaining_bytes = 0;
1087
1088         /* Handle odd number of bytes when data are more than 8bit width */
1089         if (xfer->bits_per_word > 8)
1090                 as->current_remaining_bytes &= ~0x1;
1091
1092         /* Read data */
1093         while (num_data) {
1094                 rd = spi_readl(as, RDR);
1095                 if (xfer->bits_per_word > 8)
1096                         *words++ = rd;
1097                 else
1098                         *bytes++ = rd;
1099                 num_data--;
1100         }
1101 }
1102
1103 /* Called from IRQ
1104  *
1105  * Must update "current_remaining_bytes" to keep track of data
1106  * to transfer.
1107  */
1108 static void
1109 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
1110 {
1111         if (as->fifo_size)
1112                 atmel_spi_pump_fifo_data(as, xfer);
1113         else
1114                 atmel_spi_pump_single_data(as, xfer);
1115 }
1116
1117 /* Interrupt
1118  *
1119  */
1120 static irqreturn_t
1121 atmel_spi_pio_interrupt(int irq, void *dev_id)
1122 {
1123         struct spi_controller   *host = dev_id;
1124         struct atmel_spi        *as = spi_controller_get_devdata(host);
1125         u32                     status, pending, imr;
1126         struct spi_transfer     *xfer;
1127         int                     ret = IRQ_NONE;
1128
1129         imr = spi_readl(as, IMR);
1130         status = spi_readl(as, SR);
1131         pending = status & imr;
1132
1133         if (pending & SPI_BIT(OVRES)) {
1134                 ret = IRQ_HANDLED;
1135                 spi_writel(as, IDR, SPI_BIT(OVRES));
1136                 dev_warn(host->dev.parent, "overrun\n");
1137
1138                 /*
1139                  * When we get an overrun, we disregard the current
1140                  * transfer. Data will not be copied back from any
1141                  * bounce buffer and msg->actual_len will not be
1142                  * updated with the last xfer.
1143                  *
1144                  * We will also not process any remaning transfers in
1145                  * the message.
1146                  */
1147                 as->done_status = -EIO;
1148                 smp_wmb();
1149
1150                 /* Clear any overrun happening while cleaning up */
1151                 spi_readl(as, SR);
1152
1153                 complete(&as->xfer_completion);
1154
1155         } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
1156                 atmel_spi_lock(as);
1157
1158                 if (as->current_remaining_bytes) {
1159                         ret = IRQ_HANDLED;
1160                         xfer = as->current_transfer;
1161                         atmel_spi_pump_pio_data(as, xfer);
1162                         if (!as->current_remaining_bytes)
1163                                 spi_writel(as, IDR, pending);
1164
1165                         complete(&as->xfer_completion);
1166                 }
1167
1168                 atmel_spi_unlock(as);
1169         } else {
1170                 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1171                 ret = IRQ_HANDLED;
1172                 spi_writel(as, IDR, pending);
1173         }
1174
1175         return ret;
1176 }
1177
1178 static irqreturn_t
1179 atmel_spi_pdc_interrupt(int irq, void *dev_id)
1180 {
1181         struct spi_controller   *host = dev_id;
1182         struct atmel_spi        *as = spi_controller_get_devdata(host);
1183         u32                     status, pending, imr;
1184         int                     ret = IRQ_NONE;
1185
1186         imr = spi_readl(as, IMR);
1187         status = spi_readl(as, SR);
1188         pending = status & imr;
1189
1190         if (pending & SPI_BIT(OVRES)) {
1191
1192                 ret = IRQ_HANDLED;
1193
1194                 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1195                                      | SPI_BIT(OVRES)));
1196
1197                 /* Clear any overrun happening while cleaning up */
1198                 spi_readl(as, SR);
1199
1200                 as->done_status = -EIO;
1201
1202                 complete(&as->xfer_completion);
1203
1204         } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1205                 ret = IRQ_HANDLED;
1206
1207                 spi_writel(as, IDR, pending);
1208
1209                 complete(&as->xfer_completion);
1210         }
1211
1212         return ret;
1213 }
1214
1215 static int atmel_word_delay_csr(struct spi_device *spi, struct atmel_spi *as)
1216 {
1217         struct spi_delay *delay = &spi->word_delay;
1218         u32 value = delay->value;
1219
1220         switch (delay->unit) {
1221         case SPI_DELAY_UNIT_NSECS:
1222                 value /= 1000;
1223                 break;
1224         case SPI_DELAY_UNIT_USECS:
1225                 break;
1226         default:
1227                 return -EINVAL;
1228         }
1229
1230         return (as->spi_clk / 1000000 * value) >> 5;
1231 }
1232
1233 static void initialize_native_cs_for_gpio(struct atmel_spi *as)
1234 {
1235         int i;
1236         struct spi_controller *host = platform_get_drvdata(as->pdev);
1237
1238         if (!as->native_cs_free)
1239                 return; /* already initialized */
1240
1241         if (!host->cs_gpiods)
1242                 return; /* No CS GPIO */
1243
1244         /*
1245          * On the first version of the controller (AT91RM9200), CS0
1246          * can't be used associated with GPIO
1247          */
1248         if (atmel_spi_is_v2(as))
1249                 i = 0;
1250         else
1251                 i = 1;
1252
1253         for (; i < 4; i++)
1254                 if (host->cs_gpiods[i])
1255                         as->native_cs_free |= BIT(i);
1256
1257         if (as->native_cs_free)
1258                 as->native_cs_for_gpio = ffs(as->native_cs_free);
1259 }
1260
1261 static int atmel_spi_setup(struct spi_device *spi)
1262 {
1263         struct atmel_spi        *as;
1264         struct atmel_spi_device *asd;
1265         u32                     csr;
1266         unsigned int            bits = spi->bits_per_word;
1267         int chip_select;
1268         int                     word_delay_csr;
1269
1270         as = spi_controller_get_devdata(spi->controller);
1271
1272         /* see notes above re chipselect */
1273         if (!spi_get_csgpiod(spi, 0) && (spi->mode & SPI_CS_HIGH)) {
1274                 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
1275                 return -EINVAL;
1276         }
1277
1278         /* Setup() is called during spi_register_controller(aka
1279          * spi_register_master) but after all membmers of the cs_gpiod
1280          * array have been filled, so we can looked for which native
1281          * CS will be free for using with GPIO
1282          */
1283         initialize_native_cs_for_gpio(as);
1284
1285         if (spi_get_csgpiod(spi, 0) && as->native_cs_free) {
1286                 dev_err(&spi->dev,
1287                         "No native CS available to support this GPIO CS\n");
1288                 return -EBUSY;
1289         }
1290
1291         if (spi_get_csgpiod(spi, 0))
1292                 chip_select = as->native_cs_for_gpio;
1293         else
1294                 chip_select = spi_get_chipselect(spi, 0);
1295
1296         csr = SPI_BF(BITS, bits - 8);
1297         if (spi->mode & SPI_CPOL)
1298                 csr |= SPI_BIT(CPOL);
1299         if (!(spi->mode & SPI_CPHA))
1300                 csr |= SPI_BIT(NCPHA);
1301
1302         if (!spi_get_csgpiod(spi, 0))
1303                 csr |= SPI_BIT(CSAAT);
1304         csr |= SPI_BF(DLYBS, 0);
1305
1306         word_delay_csr = atmel_word_delay_csr(spi, as);
1307         if (word_delay_csr < 0)
1308                 return word_delay_csr;
1309
1310         /* DLYBCT adds delays between words.  This is useful for slow devices
1311          * that need a bit of time to setup the next transfer.
1312          */
1313         csr |= SPI_BF(DLYBCT, word_delay_csr);
1314
1315         asd = spi->controller_state;
1316         if (!asd) {
1317                 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1318                 if (!asd)
1319                         return -ENOMEM;
1320
1321                 spi->controller_state = asd;
1322         }
1323
1324         asd->csr = csr;
1325
1326         dev_dbg(&spi->dev,
1327                 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1328                 bits, spi->mode, spi_get_chipselect(spi, 0), csr);
1329
1330         if (!atmel_spi_is_v2(as))
1331                 spi_writel(as, CSR0 + 4 * chip_select, csr);
1332
1333         return 0;
1334 }
1335
1336 static void atmel_spi_set_cs(struct spi_device *spi, bool enable)
1337 {
1338         struct atmel_spi *as = spi_controller_get_devdata(spi->controller);
1339         /* the core doesn't really pass us enable/disable, but CS HIGH vs CS LOW
1340          * since we already have routines for activate/deactivate translate
1341          * high/low to active/inactive
1342          */
1343         enable = (!!(spi->mode & SPI_CS_HIGH) == enable);
1344
1345         if (enable) {
1346                 cs_activate(as, spi);
1347         } else {
1348                 cs_deactivate(as, spi);
1349         }
1350
1351 }
1352
1353 static int atmel_spi_one_transfer(struct spi_controller *host,
1354                                         struct spi_device *spi,
1355                                         struct spi_transfer *xfer)
1356 {
1357         struct atmel_spi        *as;
1358         u8                      bits;
1359         u32                     len;
1360         struct atmel_spi_device *asd;
1361         int                     timeout;
1362         int                     ret;
1363         unsigned int            dma_timeout;
1364         long                    ret_timeout;
1365
1366         as = spi_controller_get_devdata(host);
1367
1368         asd = spi->controller_state;
1369         bits = (asd->csr >> 4) & 0xf;
1370         if (bits != xfer->bits_per_word - 8) {
1371                 dev_dbg(&spi->dev,
1372                         "you can't yet change bits_per_word in transfers\n");
1373                 return -ENOPROTOOPT;
1374         }
1375
1376         /*
1377          * DMA map early, for performance (empties dcache ASAP) and
1378          * better fault reporting.
1379          */
1380         if ((!host->cur_msg->is_dma_mapped)
1381                 && as->use_pdc) {
1382                 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1383                         return -ENOMEM;
1384         }
1385
1386         atmel_spi_set_xfer_speed(as, spi, xfer);
1387
1388         as->done_status = 0;
1389         as->current_transfer = xfer;
1390         as->current_remaining_bytes = xfer->len;
1391         while (as->current_remaining_bytes) {
1392                 reinit_completion(&as->xfer_completion);
1393
1394                 if (as->use_pdc) {
1395                         atmel_spi_lock(as);
1396                         atmel_spi_pdc_next_xfer(host, xfer);
1397                         atmel_spi_unlock(as);
1398                 } else if (atmel_spi_use_dma(as, xfer)) {
1399                         len = as->current_remaining_bytes;
1400                         ret = atmel_spi_next_xfer_dma_submit(host,
1401                                                                 xfer, &len);
1402                         if (ret) {
1403                                 dev_err(&spi->dev,
1404                                         "unable to use DMA, fallback to PIO\n");
1405                                 as->done_status = ret;
1406                                 break;
1407                         } else {
1408                                 as->current_remaining_bytes -= len;
1409                                 if (as->current_remaining_bytes < 0)
1410                                         as->current_remaining_bytes = 0;
1411                         }
1412                 } else {
1413                         atmel_spi_lock(as);
1414                         atmel_spi_next_xfer_pio(host, xfer);
1415                         atmel_spi_unlock(as);
1416                 }
1417
1418                 dma_timeout = msecs_to_jiffies(spi_controller_xfer_timeout(host, xfer));
1419                 ret_timeout = wait_for_completion_timeout(&as->xfer_completion, dma_timeout);
1420                 if (!ret_timeout) {
1421                         dev_err(&spi->dev, "spi transfer timeout\n");
1422                         as->done_status = -EIO;
1423                 }
1424
1425                 if (as->done_status)
1426                         break;
1427         }
1428
1429         if (as->done_status) {
1430                 if (as->use_pdc) {
1431                         dev_warn(host->dev.parent,
1432                                 "overrun (%u/%u remaining)\n",
1433                                 spi_readl(as, TCR), spi_readl(as, RCR));
1434
1435                         /*
1436                          * Clean up DMA registers and make sure the data
1437                          * registers are empty.
1438                          */
1439                         spi_writel(as, RNCR, 0);
1440                         spi_writel(as, TNCR, 0);
1441                         spi_writel(as, RCR, 0);
1442                         spi_writel(as, TCR, 0);
1443                         for (timeout = 1000; timeout; timeout--)
1444                                 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1445                                         break;
1446                         if (!timeout)
1447                                 dev_warn(host->dev.parent,
1448                                          "timeout waiting for TXEMPTY");
1449                         while (spi_readl(as, SR) & SPI_BIT(RDRF))
1450                                 spi_readl(as, RDR);
1451
1452                         /* Clear any overrun happening while cleaning up */
1453                         spi_readl(as, SR);
1454
1455                 } else if (atmel_spi_use_dma(as, xfer)) {
1456                         atmel_spi_stop_dma(host);
1457                 }
1458         }
1459
1460         if (!host->cur_msg->is_dma_mapped
1461                 && as->use_pdc)
1462                 atmel_spi_dma_unmap_xfer(host, xfer);
1463
1464         if (as->use_pdc)
1465                 atmel_spi_disable_pdc_transfer(as);
1466
1467         return as->done_status;
1468 }
1469
1470 static void atmel_spi_cleanup(struct spi_device *spi)
1471 {
1472         struct atmel_spi_device *asd = spi->controller_state;
1473
1474         if (!asd)
1475                 return;
1476
1477         spi->controller_state = NULL;
1478         kfree(asd);
1479 }
1480
1481 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1482 {
1483         return spi_readl(as, VERSION) & 0x00000fff;
1484 }
1485
1486 static void atmel_get_caps(struct atmel_spi *as)
1487 {
1488         unsigned int version;
1489
1490         version = atmel_get_version(as);
1491
1492         as->caps.is_spi2 = version > 0x121;
1493         as->caps.has_wdrbt = version >= 0x210;
1494         as->caps.has_dma_support = version >= 0x212;
1495         as->caps.has_pdc_support = version < 0x212;
1496 }
1497
1498 static void atmel_spi_init(struct atmel_spi *as)
1499 {
1500         spi_writel(as, CR, SPI_BIT(SWRST));
1501         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1502
1503         /* It is recommended to enable FIFOs first thing after reset */
1504         if (as->fifo_size)
1505                 spi_writel(as, CR, SPI_BIT(FIFOEN));
1506
1507         if (as->caps.has_wdrbt) {
1508                 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1509                                 | SPI_BIT(MSTR));
1510         } else {
1511                 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1512         }
1513
1514         if (as->use_pdc)
1515                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1516         spi_writel(as, CR, SPI_BIT(SPIEN));
1517 }
1518
1519 static int atmel_spi_probe(struct platform_device *pdev)
1520 {
1521         struct resource         *regs;
1522         int                     irq;
1523         struct clk              *clk;
1524         int                     ret;
1525         struct spi_controller   *host;
1526         struct atmel_spi        *as;
1527
1528         /* Select default pin state */
1529         pinctrl_pm_select_default_state(&pdev->dev);
1530
1531         irq = platform_get_irq(pdev, 0);
1532         if (irq < 0)
1533                 return irq;
1534
1535         clk = devm_clk_get(&pdev->dev, "spi_clk");
1536         if (IS_ERR(clk))
1537                 return PTR_ERR(clk);
1538
1539         /* setup spi core then atmel-specific driver state */
1540         host = spi_alloc_host(&pdev->dev, sizeof(*as));
1541         if (!host)
1542                 return -ENOMEM;
1543
1544         /* the spi->mode bits understood by this driver: */
1545         host->use_gpio_descriptors = true;
1546         host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1547         host->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1548         host->dev.of_node = pdev->dev.of_node;
1549         host->bus_num = pdev->id;
1550         host->num_chipselect = 4;
1551         host->setup = atmel_spi_setup;
1552         host->flags = (SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX |
1553                         SPI_CONTROLLER_GPIO_SS);
1554         host->transfer_one = atmel_spi_one_transfer;
1555         host->set_cs = atmel_spi_set_cs;
1556         host->cleanup = atmel_spi_cleanup;
1557         host->auto_runtime_pm = true;
1558         host->max_dma_len = SPI_MAX_DMA_XFER;
1559         host->can_dma = atmel_spi_can_dma;
1560         platform_set_drvdata(pdev, host);
1561
1562         as = spi_controller_get_devdata(host);
1563
1564         spin_lock_init(&as->lock);
1565
1566         as->pdev = pdev;
1567         as->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &regs);
1568         if (IS_ERR(as->regs)) {
1569                 ret = PTR_ERR(as->regs);
1570                 goto out_unmap_regs;
1571         }
1572         as->phybase = regs->start;
1573         as->irq = irq;
1574         as->clk = clk;
1575
1576         init_completion(&as->xfer_completion);
1577
1578         atmel_get_caps(as);
1579
1580         as->use_dma = false;
1581         as->use_pdc = false;
1582         if (as->caps.has_dma_support) {
1583                 ret = atmel_spi_configure_dma(host, as);
1584                 if (ret == 0) {
1585                         as->use_dma = true;
1586                 } else if (ret == -EPROBE_DEFER) {
1587                         goto out_unmap_regs;
1588                 }
1589         } else if (as->caps.has_pdc_support) {
1590                 as->use_pdc = true;
1591         }
1592
1593         if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1594                 as->addr_rx_bbuf = dma_alloc_coherent(&pdev->dev,
1595                                                       SPI_MAX_DMA_XFER,
1596                                                       &as->dma_addr_rx_bbuf,
1597                                                       GFP_KERNEL | GFP_DMA);
1598                 if (!as->addr_rx_bbuf) {
1599                         as->use_dma = false;
1600                 } else {
1601                         as->addr_tx_bbuf = dma_alloc_coherent(&pdev->dev,
1602                                         SPI_MAX_DMA_XFER,
1603                                         &as->dma_addr_tx_bbuf,
1604                                         GFP_KERNEL | GFP_DMA);
1605                         if (!as->addr_tx_bbuf) {
1606                                 as->use_dma = false;
1607                                 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1608                                                   as->addr_rx_bbuf,
1609                                                   as->dma_addr_rx_bbuf);
1610                         }
1611                 }
1612                 if (!as->use_dma)
1613                         dev_info(host->dev.parent,
1614                                  "  can not allocate dma coherent memory\n");
1615         }
1616
1617         if (as->caps.has_dma_support && !as->use_dma)
1618                 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1619
1620         if (as->use_pdc) {
1621                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1622                                         0, dev_name(&pdev->dev), host);
1623         } else {
1624                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1625                                         0, dev_name(&pdev->dev), host);
1626         }
1627         if (ret)
1628                 goto out_unmap_regs;
1629
1630         /* Initialize the hardware */
1631         ret = clk_prepare_enable(clk);
1632         if (ret)
1633                 goto out_free_irq;
1634
1635         as->spi_clk = clk_get_rate(clk);
1636
1637         as->fifo_size = 0;
1638         if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1639                                   &as->fifo_size)) {
1640                 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
1641         }
1642
1643         atmel_spi_init(as);
1644
1645         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1646         pm_runtime_use_autosuspend(&pdev->dev);
1647         pm_runtime_set_active(&pdev->dev);
1648         pm_runtime_enable(&pdev->dev);
1649
1650         ret = devm_spi_register_controller(&pdev->dev, host);
1651         if (ret)
1652                 goto out_free_dma;
1653
1654         /* go! */
1655         dev_info(&pdev->dev, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n",
1656                         atmel_get_version(as), (unsigned long)regs->start,
1657                         irq);
1658
1659         return 0;
1660
1661 out_free_dma:
1662         pm_runtime_disable(&pdev->dev);
1663         pm_runtime_set_suspended(&pdev->dev);
1664
1665         if (as->use_dma)
1666                 atmel_spi_release_dma(host);
1667
1668         spi_writel(as, CR, SPI_BIT(SWRST));
1669         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1670         clk_disable_unprepare(clk);
1671 out_free_irq:
1672 out_unmap_regs:
1673         spi_controller_put(host);
1674         return ret;
1675 }
1676
1677 static void atmel_spi_remove(struct platform_device *pdev)
1678 {
1679         struct spi_controller   *host = platform_get_drvdata(pdev);
1680         struct atmel_spi        *as = spi_controller_get_devdata(host);
1681
1682         pm_runtime_get_sync(&pdev->dev);
1683
1684         /* reset the hardware and block queue progress */
1685         if (as->use_dma) {
1686                 atmel_spi_stop_dma(host);
1687                 atmel_spi_release_dma(host);
1688                 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
1689                         dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1690                                           as->addr_tx_bbuf,
1691                                           as->dma_addr_tx_bbuf);
1692                         dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
1693                                           as->addr_rx_bbuf,
1694                                           as->dma_addr_rx_bbuf);
1695                 }
1696         }
1697
1698         spin_lock_irq(&as->lock);
1699         spi_writel(as, CR, SPI_BIT(SWRST));
1700         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1701         spi_readl(as, SR);
1702         spin_unlock_irq(&as->lock);
1703
1704         clk_disable_unprepare(as->clk);
1705
1706         pm_runtime_put_noidle(&pdev->dev);
1707         pm_runtime_disable(&pdev->dev);
1708 }
1709
1710 static int atmel_spi_runtime_suspend(struct device *dev)
1711 {
1712         struct spi_controller *host = dev_get_drvdata(dev);
1713         struct atmel_spi *as = spi_controller_get_devdata(host);
1714
1715         clk_disable_unprepare(as->clk);
1716         pinctrl_pm_select_sleep_state(dev);
1717
1718         return 0;
1719 }
1720
1721 static int atmel_spi_runtime_resume(struct device *dev)
1722 {
1723         struct spi_controller *host = dev_get_drvdata(dev);
1724         struct atmel_spi *as = spi_controller_get_devdata(host);
1725
1726         pinctrl_pm_select_default_state(dev);
1727
1728         return clk_prepare_enable(as->clk);
1729 }
1730
1731 static int atmel_spi_suspend(struct device *dev)
1732 {
1733         struct spi_controller *host = dev_get_drvdata(dev);
1734         int ret;
1735
1736         /* Stop the queue running */
1737         ret = spi_controller_suspend(host);
1738         if (ret)
1739                 return ret;
1740
1741         if (!pm_runtime_suspended(dev))
1742                 atmel_spi_runtime_suspend(dev);
1743
1744         return 0;
1745 }
1746
1747 static int atmel_spi_resume(struct device *dev)
1748 {
1749         struct spi_controller *host = dev_get_drvdata(dev);
1750         struct atmel_spi *as = spi_controller_get_devdata(host);
1751         int ret;
1752
1753         ret = clk_prepare_enable(as->clk);
1754         if (ret)
1755                 return ret;
1756
1757         atmel_spi_init(as);
1758
1759         clk_disable_unprepare(as->clk);
1760
1761         if (!pm_runtime_suspended(dev)) {
1762                 ret = atmel_spi_runtime_resume(dev);
1763                 if (ret)
1764                         return ret;
1765         }
1766
1767         /* Start the queue running */
1768         return spi_controller_resume(host);
1769 }
1770
1771 static const struct dev_pm_ops atmel_spi_pm_ops = {
1772         SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1773         RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1774                        atmel_spi_runtime_resume, NULL)
1775 };
1776
1777 static const struct of_device_id atmel_spi_dt_ids[] = {
1778         { .compatible = "atmel,at91rm9200-spi" },
1779         { /* sentinel */ }
1780 };
1781
1782 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1783
1784 static struct platform_driver atmel_spi_driver = {
1785         .driver         = {
1786                 .name   = "atmel_spi",
1787                 .pm     = pm_ptr(&atmel_spi_pm_ops),
1788                 .of_match_table = atmel_spi_dt_ids,
1789         },
1790         .probe          = atmel_spi_probe,
1791         .remove_new     = atmel_spi_remove,
1792 };
1793 module_platform_driver(atmel_spi_driver);
1794
1795 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1796 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1797 MODULE_LICENSE("GPL");
1798 MODULE_ALIAS("platform:atmel_spi");